X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Fide_disk.hh;h=6ccca985eba3c50b43dcc5467dc2dad47000dbef;hb=ad3f75dc81efc8818786c32d6190e3ed069b9fc6;hp=fb0614d4d343cc182def273f42278f4aed721e0e;hpb=15a8f050605919579e81b6abb98a0b596334216d;p=gem5.git diff --git a/src/dev/ide_disk.hh b/src/dev/ide_disk.hh index fb0614d4d..6ccca985e 100644 --- a/src/dev/ide_disk.hh +++ b/src/dev/ide_disk.hh @@ -1,4 +1,16 @@ /* + * Copyright (c) 2013 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2004-2005 The Regents of The University of Michigan * All rights reserved. * @@ -41,12 +53,16 @@ #include "dev/ide_ctrl.hh" #include "dev/ide_wdcreg.h" #include "dev/io_device.hh" +#include "params/IdeDisk.hh" #include "sim/eventq.hh" -#define DMA_BACKOFF_PERIOD 200 +class ChunkGenerator; + +#define DMA_BACKOFF_PERIOD 200 -#define MAX_DMA_SIZE (131072) // 128K -#define MAX_MULTSECT (128) +#define MAX_DMA_SIZE 0x20000 // 128K +#define MAX_SINGLE_DMA_SIZE 0x10000 +#define MAX_MULTSECT (128) #define PRD_BASE_MASK 0xfffffffe #define PRD_COUNT_MASK 0xfffe @@ -69,7 +85,7 @@ class PrdTableEntry { uint32_t getByteCount() { - return ((entry.byteCount == 0) ? MAX_DMA_SIZE : + return ((entry.byteCount == 0) ? MAX_SINGLE_DMA_SIZE : (entry.byteCount & PRD_COUNT_MASK)); } @@ -173,7 +189,8 @@ typedef enum DevState { // DMA protocol Prepare_Data_Dma, - Transfer_Data_Dma + Transfer_Data_Dma, + Device_Dma_Abort } DevState_t; typedef enum DmaState { @@ -182,7 +199,6 @@ typedef enum DmaState { Dma_Transfer } DmaState_t; -class PhysicalMemory; class IdeController; /** @@ -233,23 +249,19 @@ class IdeDisk : public SimObject int devID; /** Interrupt pending */ bool intrPending; + /** DMA Aborted */ + bool dmaAborted; - Stats::Scalar<> dmaReadFullPages; - Stats::Scalar<> dmaReadBytes; - Stats::Scalar<> dmaReadTxs; - Stats::Scalar<> dmaWriteFullPages; - Stats::Scalar<> dmaWriteBytes; - Stats::Scalar<> dmaWriteTxs; + Stats::Scalar dmaReadFullPages; + Stats::Scalar dmaReadBytes; + Stats::Scalar dmaReadTxs; + Stats::Scalar dmaWriteFullPages; + Stats::Scalar dmaWriteBytes; + Stats::Scalar dmaWriteTxs; public: - /** - * Create and initialize this Disk. - * @param name The name of this disk. - * @param img The disk image of this disk. - * @param id The disk ID (master=0/slave=1) - * @param disk_delay The disk delay in milliseconds - */ - IdeDisk(const std::string &name, DiskImage *img, int id, Tick disk_delay); + typedef IdeDiskParams Params; + IdeDisk(const Params *p); /** * Delete the data buffer. @@ -276,8 +288,10 @@ class IdeDisk : public SimObject } // Device register read/write - void read(const Addr &offset, IdeRegType regtype, uint8_t *data); - void write(const Addr &offset, IdeRegType regtype, const uint8_t *data); + void readCommand(const Addr offset, int size, uint8_t *data); + void readControl(const Addr offset, int size, uint8_t *data); + void writeCommand(const Addr offset, int size, const uint8_t *data); + void writeControl(const Addr offset, int size, const uint8_t *data); // Start/abort functions void startDma(const uint32_t &prdTableBase);