X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Fisa_fake.cc;h=407d08ca458bedf720f2e64aba3fa5b7f21c7110;hb=abd33d6fd26bb69d3bf53ceb6c2dc8f90d893e34;hp=9d62aecbaa6bca3222d7ea33694938bde108442f;hpb=c4c8a121863fcbde7ba67823f06a3f7564c27cba;p=gem5.git diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc index 9d62aecba..407d08ca4 100644 --- a/src/dev/isa_fake.cc +++ b/src/dev/isa_fake.cc @@ -32,8 +32,10 @@ * Isa Fake Device implementation */ -#include "base/trace.hh" #include "dev/isa_fake.hh" + +#include "base/trace.hh" +#include "debug/IsaFake.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" #include "sim/system.hh" @@ -41,11 +43,8 @@ using namespace std; IsaFake::IsaFake(Params *p) - : BasicPioDevice(p) + : BasicPioDevice(p, p->ret_bad_addr ? 0 : p->pio_size) { - if (!p->ret_bad_addr) - pioSize = p->pio_size; - retData8 = p->ret_data8; retData16 = p->ret_data16; retData32 = p->ret_data32; @@ -55,35 +54,38 @@ IsaFake::IsaFake(Params *p) Tick IsaFake::read(PacketPtr pkt) { + pkt->makeAtomicResponse(); if (params()->warn_access != "") warn("Device %s accessed by read to address %#x size=%d\n", name(), pkt->getAddr(), pkt->getSize()); if (params()->ret_bad_addr) { - DPRINTF(Tsunami, "read to bad address va=%#x size=%d\n", + DPRINTF(IsaFake, "read to bad address va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); pkt->setBadAddress(); } else { assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); - DPRINTF(Tsunami, "read va=%#x size=%d\n", + DPRINTF(IsaFake, "read va=%#x size=%d\n", pkt->getAddr(), pkt->getSize()); switch (pkt->getSize()) { case sizeof(uint64_t): - pkt->set(retData64); + pkt->setLE(retData64); break; case sizeof(uint32_t): - pkt->set(retData32); + pkt->setLE(retData32); break; case sizeof(uint16_t): - pkt->set(retData16); + pkt->setLE(retData16); break; case sizeof(uint8_t): - pkt->set(retData8); + pkt->setLE(retData8); break; default: - panic("invalid access size!\n"); + if (params()->fake_mem) + std::memset(pkt->getPtr(), 0, pkt->getSize()); + else + panic("invalid access size! Device being accessed by cache?\n"); } - pkt->makeAtomicResponse(); } return pioDelay; } @@ -91,54 +93,54 @@ IsaFake::read(PacketPtr pkt) Tick IsaFake::write(PacketPtr pkt) { + pkt->makeAtomicResponse(); if (params()->warn_access != "") { uint64_t data; switch (pkt->getSize()) { case sizeof(uint64_t): - data = pkt->get(); + data = pkt->getLE(); break; case sizeof(uint32_t): - data = pkt->get(); + data = pkt->getLE(); break; case sizeof(uint16_t): - data = pkt->get(); + data = pkt->getLE(); break; case sizeof(uint8_t): - data = pkt->get(); + data = pkt->getLE(); break; default: - panic("invalid access size!\n"); + panic("invalid access size: %u\n", pkt->getSize()); } warn("Device %s accessed by write to address %#x size=%d data=%#x\n", name(), pkt->getAddr(), pkt->getSize(), data); } if (params()->ret_bad_addr) { - DPRINTF(Tsunami, "write to bad address va=%#x size=%d \n", + DPRINTF(IsaFake, "write to bad address va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); pkt->setBadAddress(); } else { - DPRINTF(Tsunami, "write - va=%#x size=%d \n", + DPRINTF(IsaFake, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize()); if (params()->update_data) { switch (pkt->getSize()) { case sizeof(uint64_t): - retData64 = pkt->get(); + retData64 = pkt->getLE(); break; case sizeof(uint32_t): - retData32 = pkt->get(); + retData32 = pkt->getLE(); break; case sizeof(uint16_t): - retData16 = pkt->get(); + retData16 = pkt->getLE(); break; case sizeof(uint8_t): - retData8 = pkt->get(); + retData8 = pkt->getLE(); break; default: panic("invalid access size!\n"); } } - pkt->makeAtomicResponse(); } return pioDelay; }