X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Fns_gige.hh;h=87cf56962e3e05b6d0fe0e8218fe44324541b447;hb=2eae11be6499effbcf33e4f3ea747a7280adf86c;hp=2f47026f3810a6a01f66a52701d055bb98cac581;hpb=cd6da4569e9c6ed86357cfcf4eed53535c713e02;p=gem5.git

diff --git a/src/dev/ns_gige.hh b/src/dev/ns_gige.hh
index 2f47026f3..87cf56962 100644
--- a/src/dev/ns_gige.hh
+++ b/src/dev/ns_gige.hh
@@ -38,13 +38,13 @@
 #define __DEV_NS_GIGE_HH__
 
 #include "base/inet.hh"
-#include "base/statistics.hh"
+#include "dev/etherdevice.hh"
 #include "dev/etherint.hh"
 #include "dev/etherpkt.hh"
 #include "dev/io_device.hh"
 #include "dev/ns_gige_reg.h"
-#include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
+#include "params/NSGigE.hh"
 #include "sim/eventq.hh"
 
 // Hash filtering constants
@@ -62,10 +62,10 @@ const uint8_t  EEPROM_PMATCH0_ADDR = 0xC; // EEPROM Address of PMATCH word 0
  * Ethernet device registers
  */
 struct dp_regs {
-    uint32_t	command;
-    uint32_t	config;
-    uint32_t	mear;
-    uint32_t	ptscr;
+    uint32_t    command;
+    uint32_t    config;
+    uint32_t    mear;
+    uint32_t    ptscr;
     uint32_t    isr;
     uint32_t    imr;
     uint32_t    ier;
@@ -114,12 +114,11 @@ struct dp_rom {
 
 class NSGigEInt;
 class Packet;
-class PciConfigAll;
 
 /**
  * NS DP83820 Ethernet device model
  */
-class NSGigE : public PciDev
+class NSGigE : public EtherDevice
 {
   public:
     /** Transmit State Machine states */
@@ -199,7 +198,7 @@ class NSGigE : public PciDev
 
     /* state machine cycle time */
     Tick clock;
-    inline Tick cycles(int numCycles) const { return numCycles * clock; }
+    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
     /* tx State Machine */
     TxState txState;
@@ -350,36 +349,17 @@ class NSGigE : public PciDev
     NSGigEInt *interface;
 
   public:
-    struct Params : public PciDev::Params
-    {
-        Tick clock;
-        Tick intr_delay;
-        Tick tx_delay;
-        Tick rx_delay;
-        bool dma_desc_free;
-        bool dma_data_free;
-        Tick dma_read_delay;
-        Tick dma_write_delay;
-        Tick dma_read_factor;
-        Tick dma_write_factor;
-        bool rx_filter;
-        Net::EthAddr eaddr;
-        uint32_t tx_fifo_size;
-        uint32_t rx_fifo_size;
-        bool rx_thread;
-        bool tx_thread;
-        bool rss;
-        bool dma_no_allocate;
-    };
-
+    typedef NSGigEParams Params;
+    const Params *params() const { return (const Params *)_params; }
     NSGigE(Params *params);
     ~NSGigE();
-    const Params *params() const { return (const Params *)_params; }
 
-    virtual void writeConfig(int offset, const uint16_t data);
+    virtual EtherInt *getEthPort(const std::string &if_name, int idx);
 
-    virtual Tick read(Packet *pkt);
-    virtual Tick write(Packet *pkt);
+    virtual Tick writeConfig(PacketPtr pkt);
+
+    virtual Tick read(PacketPtr pkt);
+    virtual Tick write(PacketPtr pkt);
 
     bool cpuIntrPending() const;
     void cpuIntrAck() { cpuIntrClear(); }
@@ -387,64 +367,10 @@ class NSGigE : public PciDev
     bool recvPacket(EthPacketPtr packet);
     void transferDone();
 
-    void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
-
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-  public:
-    void regStats();
-
-  private:
-    Stats::Scalar<> txBytes;
-    Stats::Scalar<> rxBytes;
-    Stats::Scalar<> txPackets;
-    Stats::Scalar<> rxPackets;
-    Stats::Scalar<> txIpChecksums;
-    Stats::Scalar<> rxIpChecksums;
-    Stats::Scalar<> txTcpChecksums;
-    Stats::Scalar<> rxTcpChecksums;
-    Stats::Scalar<> txUdpChecksums;
-    Stats::Scalar<> rxUdpChecksums;
-    Stats::Scalar<> descDmaReads;
-    Stats::Scalar<> descDmaWrites;
-    Stats::Scalar<> descDmaRdBytes;
-    Stats::Scalar<> descDmaWrBytes;
-    Stats::Formula totBandwidth;
-    Stats::Formula totPackets;
-    Stats::Formula totBytes;
-    Stats::Formula totPacketRate;
-    Stats::Formula txBandwidth;
-    Stats::Formula rxBandwidth;
-    Stats::Formula txPacketRate;
-    Stats::Formula rxPacketRate;
-    Stats::Scalar<> postedSwi;
-    Stats::Formula coalescedSwi;
-    Stats::Scalar<> totalSwi;
-    Stats::Scalar<> postedRxIdle;
-    Stats::Formula coalescedRxIdle;
-    Stats::Scalar<> totalRxIdle;
-    Stats::Scalar<> postedRxOk;
-    Stats::Formula coalescedRxOk;
-    Stats::Scalar<> totalRxOk;
-    Stats::Scalar<> postedRxDesc;
-    Stats::Formula coalescedRxDesc;
-    Stats::Scalar<> totalRxDesc;
-    Stats::Scalar<> postedTxOk;
-    Stats::Formula coalescedTxOk;
-    Stats::Scalar<> totalTxOk;
-    Stats::Scalar<> postedTxIdle;
-    Stats::Formula coalescedTxIdle;
-    Stats::Scalar<> totalTxIdle;
-    Stats::Scalar<> postedTxDesc;
-    Stats::Formula coalescedTxDesc;
-    Stats::Scalar<> totalTxDesc;
-    Stats::Scalar<> postedRxOrn;
-    Stats::Formula coalescedRxOrn;
-    Stats::Scalar<> totalRxOrn;
-    Stats::Formula coalescedTotal;
-    Stats::Scalar<> postedInterrupts;
-    Stats::Scalar<> droppedPackets;
+    virtual void resume();
 };
 
 /*
@@ -457,7 +383,8 @@ class NSGigEInt : public EtherInt
 
   public:
     NSGigEInt(const std::string &name, NSGigE *d)
-        : EtherInt(name), dev(d) { dev->setInterface(this); }
+        : EtherInt(name), dev(d)
+    { }
 
     virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
     virtual void sendDone() { dev->transferDone(); }