X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fdev%2Fx86%2Fpc.cc;h=dd8e34d9e55685168fb6166334177a6577463432;hb=e88165a431a90cf7e33e205794caed898ca6fcb1;hp=d23474c67c955521ff6e0cbef429774f0c4bcca8;hpb=70cd5bfce5549495c6e969fa509bfd5f56190e10;p=gem5.git

diff --git a/src/dev/x86/pc.cc b/src/dev/x86/pc.cc
index d23474c67..dd8e34d9e 100644
--- a/src/dev/x86/pc.cc
+++ b/src/dev/x86/pc.cc
@@ -38,13 +38,14 @@
 
 #include "arch/x86/intmessage.hh"
 #include "arch/x86/x86_traits.hh"
+#include "config/the_isa.hh"
 #include "cpu/intr_control.hh"
-#include "dev/terminal.hh"
 #include "dev/x86/i82094aa.hh"
 #include "dev/x86/i8254.hh"
 #include "dev/x86/i8259.hh"
 #include "dev/x86/pc.hh"
 #include "dev/x86/south_bridge.hh"
+#include "dev/terminal.hh"
 #include "sim/system.hh"
 
 using namespace std;
@@ -54,8 +55,6 @@ Pc::Pc(const Params *p)
     : Platform(p), system(p->system)
 {
     southBridge = NULL;
-    // set the back pointer from the system to myself
-    system->platform = this;
 }
 
 void
@@ -107,13 +106,13 @@ Pc::init()
     entry.vector = 0x30;
     ioApic.writeReg(0x30, entry.bottomDW);
     ioApic.writeReg(0x31, entry.topDW);
-}
 
-Tick
-Pc::intrFrequency()
-{
-    panic("Need implementation\n");
-    M5_DUMMY_RETURN
+    /*
+     * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared
+     * these out and masked them before passing control to the OS.
+     */
+    southBridge->pic1->maskAll();
+    southBridge->pic2->maskAll();
 }
 
 void
@@ -145,8 +144,7 @@ Pc::clearPciInt(int line)
 Addr
 Pc::pciToDma(Addr pciAddr) const
 {
-    panic("Need implementation\n");
-    M5_DUMMY_RETURN
+    return pciAddr;
 }
 
 Addr