X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fexperiment%2Fcompalu.py;fp=src%2Fexperiment%2Fcompalu.py;h=74489360d1a3a10dc892471781515110a2dc03d3;hb=d888bf3415f6aca6aa31148445065dc89f0c5ce2;hp=662ebec3ddb12b4d06ec1cf73b95159493d9c409;hpb=b8237f119afe9f79ebe8bb00b9f6ed8cf75605c7;p=soc.git

diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py
index 662ebec3..74489360 100644
--- a/src/experiment/compalu.py
+++ b/src/experiment/compalu.py
@@ -48,7 +48,7 @@ class ComputationUnitNoDelay(Elaboratable):
         self.go_wr_i = Signal(reset_less=True) # go write in
         self.issue_i = Signal(reset_less=True) # fn issue in
         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
-        self.go_die_i = Signal(reset_less=True) # go die (reset)
+        self.go_die_i = Signal() # go die (reset)
 
         self.oper_i = Signal(opwid, reset_less=True) # opcode in
         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
@@ -69,8 +69,10 @@ class ComputationUnitNoDelay(Elaboratable):
         # shadow/go_die
         reset_w = Signal(reset_less=True)
         reset_r = Signal(reset_less=True)
-        m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
-        m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
+        #m.d.comb += reset_w.eq(self.go_wr_i)# | self.go_die_i)
+        #m.d.comb += reset_r.eq(self.go_rd_i)# | self.go_die_i)
+        reset_w = self.go_wr_i
+        reset_r = self.go_rd_i
 
         # This is fascinating and very important to observe that this
         # is in effect a "3-way revolving door".  At no time may all 3
@@ -109,7 +111,7 @@ class ComputationUnitNoDelay(Elaboratable):
             m.d.sync += self.counter.eq(self.counter - 1)
         with m.If(self.counter == 1):
             # write req release out.  waits until shadow is dropped.
-            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q & self.shadown_i)
+            m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q)# & self.shadown_i)
 
         # create a latch/register for src1/src2
         latchregister(m, self.src1_i, self.alu.a, src_l.q)