X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Ffreedreno%2Fir3%2Fir3_compiler_nir.c;h=8172e113c1a141586b4cd030c786ae5fcb109882;hb=2b2524099379b96a6dbeab037a25cbf5d71da7df;hp=812ce7f9489cfeefdef82ece49233208b173af34;hpb=88dcfaf0ee24b6c858f13b684212951d3077856c;p=mesa.git diff --git a/src/freedreno/ir3/ir3_compiler_nir.c b/src/freedreno/ir3/ir3_compiler_nir.c index 812ce7f9489..8172e113c1a 100644 --- a/src/freedreno/ir3/ir3_compiler_nir.c +++ b/src/freedreno/ir3/ir3_compiler_nir.c @@ -39,6 +39,16 @@ #include "ir3.h" #include "ir3_context.h" +void +ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc) +{ + nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc); + if (!intrin) + return; + + instr->flags |= IR3_INSTR_B; + instr->cat6.base = nir_intrinsic_desc_set(intrin); +} static struct ir3_instruction * create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n, @@ -88,7 +98,7 @@ create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n) instr->cat6.type = TYPE_U32; instr->cat6.iim_val = 1; } else { - instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0); + instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0); instr->regs[2]->wrmask = 0x3; } @@ -100,7 +110,7 @@ create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp) { /* first four vec4 sysval's reserved for UBOs: */ /* NOTE: dp is in scalar, but there can be >4 dp components: */ - struct ir3_const_state *const_state = &ctx->so->shader->const_state; + struct ir3_const_state *const_state = ir3_const_state(ctx->so); unsigned n = const_state->offsets.driver_param; unsigned r = regid(n + dp / 4, dp % 4); return create_uniform(ctx->block, r); @@ -430,9 +440,14 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) * src instruction and create a mov. This is easier for cp * to eliminate. * + * NOTE: a3xx definitely seen not working with flat bary.f. Same test + * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply + * everywhere. + * * TODO probably opc_cat==4 is ok too */ if (alu->src[0].src.is_ssa && + src[0]->opc != OPC_BARY_F && (list_length(&alu->src[0].src.ssa->uses) == 1) && ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) { src[0]->flags |= IR3_INSTR_SAT; @@ -463,7 +478,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0]->cat5.type = TYPE_F32; break; case nir_op_fddx_fine: - dst[0] = ir3_DSXPP_1(b, src[0], 0); + dst[0] = ir3_DSXPP_MACRO(b, src[0], 0); dst[0]->cat5.type = TYPE_F32; break; case nir_op_fddy: @@ -473,7 +488,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) break; break; case nir_op_fddy_fine: - dst[0] = ir3_DSYPP_1(b, src[0], 0); + dst[0] = ir3_DSYPP_MACRO(b, src[0], 0); dst[0]->cat5.type = TYPE_F32; break; case nir_op_flt: @@ -488,7 +503,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu) dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_EQ; break; - case nir_op_fne: + case nir_op_fneu: dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0); dst[0]->cat2.condition = IR3_COND_NE; break; @@ -739,15 +754,12 @@ emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0); ldc->regs[0]->wrmask = MASK(ncomp); ldc->cat6.iim_val = ncomp; - ldc->cat6.d = nir_intrinsic_base(intr); + ldc->cat6.d = nir_intrinsic_component(intr); ldc->cat6.type = TYPE_U32; - nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]); - if (bindless) { - ldc->flags |= IR3_INSTR_B; - ldc->cat6.base = nir_intrinsic_desc_set(bindless); + ir3_handle_bindless_cat6(ldc, intr->src[0]); + if (ldc->flags & IR3_INSTR_B) ctx->so->bindless_ubo = true; - } ir3_split_dest(b, dst, ldc, 0, ncomp); } @@ -760,11 +772,8 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, { struct ir3_block *b = ctx->block; struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1; - /* UBO addresses are the first driver params, but subtract 2 here to - * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0 - * is the uniforms: */ - struct ir3_const_state *const_state = &ctx->so->shader->const_state; - unsigned ubo = regid(const_state->offsets.ubo, 0) - 2; + const struct ir3_const_state *const_state = ir3_const_state(ctx->so); + unsigned ubo = regid(const_state->offsets.ubo, 0); const unsigned ptrsz = ir3_pointer_size(ctx->compiler); int off = 0; @@ -776,8 +785,8 @@ emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr, base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz)); base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1); } else { - base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz)); - base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz)); + base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz)); + base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz)); /* NOTE: since relative addressing is used, make sure constlen is * at least big enough to cover all the UBO addresses, since the @@ -838,8 +847,30 @@ static void emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction **dst) { + if (ir3_bindless_resource(intr->src[0])) { + struct ir3_block *b = ctx->block; + struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]); + struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0); + resinfo->cat6.iim_val = 1; + resinfo->cat6.d = 1; + resinfo->cat6.type = TYPE_U32; + resinfo->cat6.typed = false; + /* resinfo has no writemask and always writes out 3 components */ + resinfo->regs[0]->wrmask = MASK(3); + ir3_handle_bindless_cat6(resinfo, intr->src[0]); + struct ir3_instruction *resinfo_dst; + ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1); + /* Unfortunately resinfo returns the array length, i.e. in dwords, + * while NIR expects us to return the size in bytes. + * + * TODO: fix this in NIR. + */ + *dst = ir3_SHL_B(b, resinfo_dst, 0, create_immed(b, 2), 0); + return; + } + /* SSBO size stored as a const starting at ssbo_sizes: */ - struct ir3_const_state *const_state = &ctx->so->shader->const_state; + const struct ir3_const_state *const_state = ir3_const_state(ctx->so); unsigned blk_idx = nir_src_as_uint(intr->src[0]); unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) + const_state->ssbo_size.off[blk_idx]; @@ -881,40 +912,26 @@ emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr) struct ir3_block *b = ctx->block; struct ir3_instruction *stl, *offset; struct ir3_instruction * const *value; - unsigned base, wrmask; + unsigned base, wrmask, ncomp; value = ir3_get_src(ctx, &intr->src[0]); offset = ir3_get_src(ctx, &intr->src[1])[0]; base = nir_intrinsic_base(intr); wrmask = nir_intrinsic_write_mask(intr); + ncomp = ffs(~wrmask) - 1; - /* Combine groups of consecutive enabled channels in one write - * message. We use ffs to find the first enabled channel and then ffs on - * the bit-inverse, down-shifted writemask to determine the length of - * the block of enabled bits. - * - * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic()) - */ - while (wrmask) { - unsigned first_component = ffs(wrmask) - 1; - unsigned length = ffs(~(wrmask >> first_component)) - 1; - - stl = ir3_STL(b, offset, 0, - ir3_create_collect(ctx, &value[first_component], length), 0, - create_immed(b, length), 0); - stl->cat6.dst_offset = first_component + base; - stl->cat6.type = utype_src(intr->src[0]); - stl->barrier_class = IR3_BARRIER_SHARED_W; - stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; - - array_insert(b, b->keeps, stl); - - /* Clear the bits in the writemask that we just wrote, then try - * again to see if more channels are left. - */ - wrmask &= (15 << (first_component + length)); - } + assert(wrmask == BITFIELD_MASK(intr->num_components)); + + stl = ir3_STL(b, offset, 0, + ir3_create_collect(ctx, value, ncomp), 0, + create_immed(b, ncomp), 0); + stl->cat6.dst_offset = base; + stl->cat6.type = utype_src(intr->src[0]); + stl->barrier_class = IR3_BARRIER_SHARED_W; + stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; + + array_insert(b, b->keeps, stl); } /* src[] = { offset }. const_index[] = { base } */ @@ -933,6 +950,10 @@ emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *int create_immed(b, intr->num_components), 0, create_immed(b, base), 0); + /* for a650, use LDL for tess ctrl inputs: */ + if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared) + load->opc = OPC_LDL; + load->cat6.type = utype_dst(intr->dest); load->regs[0]->wrmask = MASK(intr->num_components); @@ -942,48 +963,32 @@ emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *int ir3_split_dest(b, dst, load, 0, intr->num_components); } -/* src[] = { value, offset }. const_index[] = { base, write_mask } */ +/* src[] = { value, offset }. const_index[] = { base } */ static void emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr) { struct ir3_block *b = ctx->block; struct ir3_instruction *store, *offset; struct ir3_instruction * const *value; - unsigned base, wrmask; value = ir3_get_src(ctx, &intr->src[0]); offset = ir3_get_src(ctx, &intr->src[1])[0]; - base = nir_intrinsic_base(intr); - wrmask = nir_intrinsic_write_mask(intr); - - /* Combine groups of consecutive enabled channels in one write - * message. We use ffs to find the first enabled channel and then ffs on - * the bit-inverse, down-shifted writemask to determine the length of - * the block of enabled bits. - * - * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic()) - */ - while (wrmask) { - unsigned first_component = ffs(wrmask) - 1; - unsigned length = ffs(~(wrmask >> first_component)) - 1; - - store = ir3_STLW(b, offset, 0, - ir3_create_collect(ctx, &value[first_component], length), 0, - create_immed(b, length), 0); + store = ir3_STLW(b, offset, 0, + ir3_create_collect(ctx, value, intr->num_components), 0, + create_immed(b, intr->num_components), 0); - store->cat6.dst_offset = first_component + base; - store->cat6.type = utype_src(intr->src[0]); - store->barrier_class = IR3_BARRIER_SHARED_W; - store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; + /* for a650, use STL for vertex outputs used by tess ctrl shader: */ + if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation && + ctx->compiler->tess_use_shared) + store->opc = OPC_STL; - array_insert(b, b->keeps, store); + store->cat6.dst_offset = nir_intrinsic_base(intr); + store->cat6.type = utype_src(intr->src[0]); + store->barrier_class = IR3_BARRIER_SHARED_W; + store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W; - /* Clear the bits in the writemask that we just wrote, then try - * again to see if more channels are left. - */ - wrmask &= (15 << (first_component + length)); - } + array_insert(b, b->keeps, store); } /* @@ -1201,8 +1206,9 @@ emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr, ir3_split_dest(b, dst, sam, 0, 4); } -static void -emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, +/* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */ +void +emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr, struct ir3_instruction **dst) { struct ir3_block *b = ctx->block; @@ -1213,6 +1219,7 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, TYPE_U16 : TYPE_U32; info.flags |= flags; + assert(nir_src_as_uint(intr->src[1]) == 0); lod = create_immed(b, 0); sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL); @@ -1244,7 +1251,8 @@ emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr, * bytes-per-pixel should have been emitted in 2nd slot of * image_dims. See ir3_shader::emit_image_dims(). */ - struct ir3_const_state *const_state = &ctx->so->shader->const_state; + const struct ir3_const_state *const_state = + ir3_const_state(ctx->so); unsigned cb = regid(const_state->offsets.image_dims, 0) + const_state->image_dims.off[nir_src_as_uint(intr->src[0])]; struct ir3_instruction *aux = create_uniform(b, cb + 1); @@ -1370,48 +1378,88 @@ create_sysval_input(struct ir3_context *ctx, gl_system_value slot, } static struct ir3_instruction * -get_barycentric_centroid(struct ir3_context *ctx) +get_barycentric(struct ir3_context *ctx, enum ir3_bary bary) { - if (!ctx->ij_centroid) { + static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL; + + STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL); + STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE); + STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID); + STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE); + STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL); + STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID); + STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE); + + if (!ctx->ij[bary]) { struct ir3_instruction *xy[2]; struct ir3_instruction *ij; - ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3); + ij = create_sysval_input(ctx, sysval_base + bary, 0x3); ir3_split_dest(ctx->block, xy, ij, 0, 2); - ctx->ij_centroid = ir3_create_collect(ctx, xy, 2); + ctx->ij[bary] = ir3_create_collect(ctx, xy, 2); } - return ctx->ij_centroid; + return ctx->ij[bary]; } -static struct ir3_instruction * -get_barycentric_sample(struct ir3_context *ctx) +/* TODO: make this a common NIR helper? + * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it + * can't be extended to work with this + */ +static gl_system_value +nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr) { - if (!ctx->ij_sample) { - struct ir3_instruction *xy[2]; - struct ir3_instruction *ij; - - ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3); - ir3_split_dest(ctx->block, xy, ij, 0, 2); + enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr); + gl_system_value sysval; - ctx->ij_sample = ir3_create_collect(ctx, xy, 2); + switch (intr->intrinsic) { + case nir_intrinsic_load_barycentric_pixel: + if (interp_mode == INTERP_MODE_NOPERSPECTIVE) + sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL; + else + sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL; + break; + case nir_intrinsic_load_barycentric_centroid: + if (interp_mode == INTERP_MODE_NOPERSPECTIVE) + sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID; + else + sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID; + break; + case nir_intrinsic_load_barycentric_sample: + if (interp_mode == INTERP_MODE_NOPERSPECTIVE) + sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE; + else + sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE; + break; + default: + unreachable("invalid barycentric intrinsic"); } - return ctx->ij_sample; + return sysval; } -static struct ir3_instruction * -get_barycentric_pixel(struct ir3_context *ctx) +static void +emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr, + struct ir3_instruction **dst) { - /* TODO when tgsi_to_nir supports "new-style" FS inputs switch - * this to create ij_pixel only on demand: - */ - return ctx->ij_pixel; + gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr); + + if (!ctx->so->key.msaa) { + if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE) + sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL; + if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE) + sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL; + } + + enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL; + + struct ir3_instruction *ij = get_barycentric(ctx, bary); + ir3_split_dest(ctx->block, dst, ij, 0, 2); } static struct ir3_instruction * -get_frag_coord(struct ir3_context *ctx) +get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr) { if (!ctx->frag_coord) { struct ir3_block *b = ctx->in_block; @@ -1436,9 +1484,11 @@ get_frag_coord(struct ir3_context *ctx) } ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4); - ctx->so->frag_coord = true; } + ctx->so->fragcoord_compmask |= + nir_ssa_def_components_read(&intr->dest.ssa); + return ctx->frag_coord; } @@ -1449,31 +1499,33 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) struct ir3_instruction **dst; struct ir3_instruction * const *src; struct ir3_block *b = ctx->block; + unsigned dest_components = nir_intrinsic_dest_components(intr); int idx, comp; if (info->has_dest) { - unsigned n = nir_intrinsic_dest_components(intr); - dst = ir3_get_dst(ctx, &intr->dest, n); + dst = ir3_get_dst(ctx, &intr->dest, dest_components); } else { dst = NULL; } - const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4; - const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4; + const struct ir3_const_state *const_state = ir3_const_state(ctx->so); + const unsigned primitive_param = const_state->offsets.primitive_param * 4; + const unsigned primitive_map = const_state->offsets.primitive_map * 4; switch (intr->intrinsic) { case nir_intrinsic_load_uniform: idx = nir_intrinsic_base(intr); if (nir_src_is_const(intr->src[0])) { idx += nir_src_as_uint(intr->src[0]); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { dst[i] = create_uniform_typed(b, idx + i, nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32); } } else { src = ir3_get_src(ctx, &intr->src[0]); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { dst[i] = create_uniform_indirect(b, idx + i, + nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32, ir3_get_addr0(ctx, src[0], 1)); } /* NOTE: if relative addressing is used, we set @@ -1482,7 +1534,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) * addr reg value can be: */ ctx->so->constlen = MAX2(ctx->so->constlen, - ctx->so->shader->ubo_state.size / 16); + const_state->ubo_state.size / 16); } break; @@ -1536,7 +1588,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_end_patch_ir3: assert(ctx->so->type == MESA_SHADER_TESS_CTRL); - struct ir3_instruction *end = ir3_ENDIF(b); + struct ir3_instruction *end = ir3_PREDE(b); array_insert(b, b->keeps, end); end->barrier_class = IR3_BARRIER_EVERYTHING; @@ -1545,6 +1597,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) case nir_intrinsic_store_global_ir3: { struct ir3_instruction *value, *addr, *offset; + unsigned ncomp = nir_intrinsic_src_components(intr, 0); addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ ir3_get_src(ctx, &intr->src[1])[0], @@ -1553,12 +1606,11 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) offset = ir3_get_src(ctx, &intr->src[2])[0]; - value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), - intr->num_components); + value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp); struct ir3_instruction *stg = ir3_STG_G(ctx->block, addr, 0, value, 0, - create_immed(ctx->block, intr->num_components), 0, offset, 0); + create_immed(ctx->block, ncomp), 0, offset, 0); stg->cat6.type = TYPE_U32; stg->cat6.iim_val = 1; @@ -1580,26 +1632,26 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) offset = ir3_get_src(ctx, &intr->src[1])[0]; struct ir3_instruction *load = - ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components), + ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components), 0, offset, 0); load->cat6.type = TYPE_U32; - load->regs[0]->wrmask = MASK(intr->num_components); + load->regs[0]->wrmask = MASK(dest_components); load->barrier_class = IR3_BARRIER_BUFFER_R; load->barrier_conflict = IR3_BARRIER_BUFFER_W; - ir3_split_dest(b, dst, load, 0, intr->num_components); + ir3_split_dest(b, dst, load, 0, dest_components); break; } case nir_intrinsic_load_ubo: emit_intrinsic_load_ubo(ctx, intr, dst); break; - case nir_intrinsic_load_ubo_ir3: + case nir_intrinsic_load_ubo_vec4: emit_intrinsic_load_ubo_ldc(ctx, intr, dst); break; case nir_intrinsic_load_frag_coord: - ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4); + ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4); break; case nir_intrinsic_load_sample_pos_from_id: { /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32, @@ -1615,24 +1667,16 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) break; } case nir_intrinsic_load_size_ir3: - if (!ctx->ij_size) { - ctx->ij_size = + if (!ctx->ij[IJ_PERSP_SIZE]) { + ctx->ij[IJ_PERSP_SIZE] = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1); } - dst[0] = ctx->ij_size; + dst[0] = ctx->ij[IJ_PERSP_SIZE]; break; case nir_intrinsic_load_barycentric_centroid: - ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2); - break; case nir_intrinsic_load_barycentric_sample: - if (ctx->so->key.msaa) { - ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2); - } else { - ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2); - } - break; case nir_intrinsic_load_barycentric_pixel: - ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2); + emit_intrinsic_barycentric(ctx, intr, dst); break; case nir_intrinsic_load_interpolated_input: idx = nir_intrinsic_base(intr); @@ -1641,7 +1685,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) if (nir_src_is_const(intr->src[1])) { struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2); idx += nir_src_as_uint(intr->src[1]); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { unsigned inloc = idx * 4 + i + comp; if (ctx->so->inputs[idx].bary && !ctx->so->inputs[idx].use_ldlv) { @@ -1664,7 +1708,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) comp = nir_intrinsic_component(intr); if (nir_src_is_const(intr->src[0])) { idx += nir_src_as_uint(intr->src[0]); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { unsigned n = idx * 4 + i + comp; dst[i] = ctx->inputs[n]; compile_assert(ctx, ctx->inputs[n]); @@ -1674,7 +1718,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) struct ir3_instruction *collect = ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs); struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { unsigned n = idx * 4 + i + comp; dst[i] = create_indirect_load(ctx, ctx->ninputs, n, addr, collect); @@ -1750,7 +1794,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_image_size: case nir_intrinsic_bindless_image_size: - emit_intrinsic_image_size(ctx, intr, dst); + ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst); break; case nir_intrinsic_image_atomic_add: case nir_intrinsic_bindless_image_atomic_add: @@ -1794,7 +1838,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) idx += nir_src_as_uint(intr->src[1]); src = ir3_get_src(ctx, &intr->src[0]); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < nir_intrinsic_src_components(intr, 0); i++) { unsigned n = idx * 4 + i + comp; ctx->outputs[n] = src[i]; } @@ -1806,12 +1850,24 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) } dst[0] = ctx->basevertex; break; + case nir_intrinsic_load_draw_id: + if (!ctx->draw_id) { + ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID); + } + dst[0] = ctx->draw_id; + break; case nir_intrinsic_load_base_instance: if (!ctx->base_instance) { ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE); } dst[0] = ctx->base_instance; break; + case nir_intrinsic_load_view_index: + if (!ctx->view_index) { + ctx->view_index = create_sysval_input(ctx, SYSTEM_VALUE_VIEW_INDEX, 0x1); + } + dst[0] = ctx->view_index; + break; case nir_intrinsic_load_vertex_id_zero_base: case nir_intrinsic_load_vertex_id: if (!ctx->vertex_id) { @@ -1845,7 +1901,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) break; case nir_intrinsic_load_user_clip_plane: idx = nir_intrinsic_ucp_id(intr); - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { unsigned n = idx * 4 + i; dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n); } @@ -1880,12 +1936,12 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) ir3_split_dest(b, dst, ctx->work_group_id, 0, 3); break; case nir_intrinsic_load_num_work_groups: - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i); } break; case nir_intrinsic_load_local_group_size: - for (int i = 0; i < intr->num_components; i++) { + for (int i = 0; i < dest_components; i++) { dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i); } break; @@ -1915,7 +1971,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) array_insert(ctx->ir, ctx->ir->predicates, kill); array_insert(b, b->keeps, kill); - ctx->so->no_earlyz = true; + ctx->so->has_kill = true; break; } @@ -1933,7 +1989,7 @@ emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr) /* condition always goes in predicate register: */ cond->regs[0]->num = regid(REG_P0, 0); - kill = ir3_IF(b, cond, 0); + kill = ir3_PREDT(b, cond, 0); kill->barrier_class = IR3_BARRIER_EVERYTHING; kill->barrier_conflict = IR3_BARRIER_EVERYTHING; @@ -2262,7 +2318,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0); compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0); - if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) { + if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) { opc = OPC_META_TEX_PREFETCH; ctx->so->num_sampler_prefetch++; break; @@ -2438,7 +2494,7 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex) sam = ir3_META_TEX_PREFETCH(b); __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */ - __ssa_src(sam, get_barycentric_pixel(ctx), 0); + __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0); sam->prefetch.input_offset = ir3_nir_coord_offset(tex->src[idx].src.ssa); /* make sure not to add irrelevant flags like S2EN */ @@ -2828,7 +2884,8 @@ emit_stream_out(struct ir3_context *ctx) * stripped out in the backend. */ for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) { - struct ir3_const_state *const_state = &ctx->so->shader->const_state; + const struct ir3_const_state *const_state = + ir3_const_state(ctx->so); unsigned stride = strmout->stride[i]; struct ir3_instruction *base, *off; @@ -2994,8 +3051,11 @@ setup_input(struct ir3_context *ctx, nir_variable *in) ctx->inputs[idx] = instr; } } else if (ctx->so->type == MESA_SHADER_VERTEX) { - struct ir3_instruction *input = NULL, *in; + struct ir3_instruction *input = NULL; struct ir3_instruction *components[4]; + /* input as setup as frac=0 with "ncomp + frac" components, + * this avoids getting a sparse writemask + */ unsigned mask = (1 << (ncomp + frac)) - 1; foreach_input (in, ctx->ir) { @@ -3009,20 +3069,52 @@ setup_input(struct ir3_context *ctx, nir_variable *in) input = create_input(ctx, mask); input->input.inidx = n; } else { + /* For aliased inputs, just append to the wrmask.. ie. if we + * first see a vec2 index at slot N, and then later a vec4, + * the wrmask of the resulting overlapped vec2 and vec4 is 0xf + * + * If the new input that aliases a previously processed input + * sets no new bits, then just bail as there is nothing to see + * here. + */ + if (!(mask & ~input->regs[0]->wrmask)) + return; input->regs[0]->wrmask |= mask; } - ir3_split_dest(ctx->block, components, input, frac, ncomp); + ir3_split_dest(ctx->block, components, input, 0, ncomp + frac); - for (int i = 0; i < ncomp; i++) { - unsigned idx = (n * 4) + i + frac; + for (int i = 0; i < ncomp + frac; i++) { + unsigned idx = (n * 4) + i; compile_assert(ctx, idx < ctx->ninputs); + + /* With aliased inputs, since we add to the wrmask above, we + * can end up with stale meta:split instructions in the inputs + * table. This is basically harmless, since eventually they + * will get swept away by DCE, but the mismatch wrmask (since + * they would be using the previous wrmask before we OR'd in + * more bits) angers ir3_validate. So just preemptively clean + * them up. See: + * + * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2 + * + * Note however that split_dest() will return the src if it is + * scalar, so the previous ctx->inputs[idx] could be the input + * itself (which we don't want to remove) + */ + if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) { + list_del(&ctx->inputs[idx]->node); + } + ctx->inputs[idx] = components[i]; } } else { ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type); } + /* note: this can be wrong for sparse vertex inputs, this happens with + * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter + */ if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) { so->total_in += ncomp; } @@ -3130,7 +3222,8 @@ static void setup_output(struct ir3_context *ctx, nir_variable *out) { struct ir3_shader_variant *so = ctx->so; - unsigned ncomp = glsl_get_components(out->type); + unsigned slots = glsl_count_vec4_slots(out->type, false, false); + unsigned ncomp = glsl_get_components(glsl_without_array(out->type)); unsigned n = out->data.driver_location; unsigned frac = out->data.location_frac; unsigned slot = out->data.location; @@ -3146,7 +3239,11 @@ setup_output(struct ir3_context *ctx, nir_variable *out) case FRAG_RESULT_SAMPLE_MASK: so->writes_smask = true; break; + case FRAG_RESULT_STENCIL: + so->writes_stencilref = true; + break; default: + slot += out->data.index; /* For dual-src blend */ if (slot >= FRAG_RESULT_DATA0) break; ir3_context_error(ctx, "unknown FS output name: %s\n", @@ -3192,30 +3289,34 @@ setup_output(struct ir3_context *ctx, nir_variable *out) ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type); } - compile_assert(ctx, n < ARRAY_SIZE(so->outputs)); - so->outputs[n].slot = slot; - so->outputs_count = MAX2(so->outputs_count, n + 1); + so->outputs_count = out->data.driver_location + slots; + compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs)); - for (int i = 0; i < ncomp; i++) { - unsigned idx = (n * 4) + i + frac; - compile_assert(ctx, idx < ctx->noutputs); - ctx->outputs[idx] = create_immed(ctx->block, fui(0.0)); - } + for (int i = 0; i < slots; i++) { + int slot_base = n + i; + so->outputs[slot_base].slot = slot + i; - /* if varying packing doesn't happen, we could end up in a situation - * with "holes" in the output, and since the per-generation code that - * sets up varying linkage registers doesn't expect to have more than - * one varying per vec4 slot, pad the holes. - * - * Note that this should probably generate a performance warning of - * some sort. - */ - for (int i = 0; i < frac; i++) { - unsigned idx = (n * 4) + i; - if (!ctx->outputs[idx]) { + for (int i = 0; i < ncomp; i++) { + unsigned idx = (slot_base * 4) + i + frac; + compile_assert(ctx, idx < ctx->noutputs); ctx->outputs[idx] = create_immed(ctx->block, fui(0.0)); } + + /* if varying packing doesn't happen, we could end up in a situation + * with "holes" in the output, and since the per-generation code that + * sets up varying linkage registers doesn't expect to have more than + * one varying per vec4 slot, pad the holes. + * + * Note that this should probably generate a performance warning of + * some sort. + */ + for (int i = 0; i < frac; i++) { + unsigned idx = (slot_base * 4) + i; + if (!ctx->outputs[idx]) { + ctx->outputs[idx] = create_immed(ctx->block, fui(0.0)); + } + } } } @@ -3229,7 +3330,7 @@ emit_instructions(struct ir3_context *ctx) ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs); ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs); - ctx->ir = ir3_create(ctx->compiler, ctx->so->type); + ctx->ir = ir3_create(ctx->compiler, ctx->so); /* Create inputs in first block: */ ctx->block = get_block(ctx, nir_start_block(fxn)); @@ -3245,20 +3346,20 @@ emit_instructions(struct ir3_context *ctx) * tgsi_to_nir) */ if (ctx->so->type == MESA_SHADER_FRAGMENT) { - ctx->ij_pixel = create_input(ctx, 0x3); + ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3); } /* Setup inputs: */ - nir_foreach_variable (var, &ctx->s->inputs) { + nir_foreach_shader_in_variable (var, ctx->s) { setup_input(ctx, var); } /* Defer add_sysval_input() stuff until after setup_inputs(), * because sysvals need to be appended after varyings: */ - if (ctx->ij_pixel) { + if (ctx->ij[IJ_PERSP_PIXEL]) { add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL, - 0x3, ctx->ij_pixel); + 0x3, ctx->ij[IJ_PERSP_PIXEL]); } @@ -3297,19 +3398,15 @@ emit_instructions(struct ir3_context *ctx) } /* Setup outputs: */ - nir_foreach_variable (var, &ctx->s->outputs) { + nir_foreach_shader_out_variable (var, ctx->s) { setup_output(ctx, var); } - /* Find # of samplers: */ - nir_foreach_variable (var, &ctx->s->uniforms) { - ctx->so->num_samp += glsl_type_get_sampler_count(var->type); - /* just assume that we'll be reading from images.. if it - * is write-only we don't have to count it, but not sure - * if there is a good way to know? - */ - ctx->so->num_samp += glsl_type_get_image_count(var->type); - } + /* Find # of samplers. Just assume that we'll be reading from images.. if + * it is write-only we don't have to count it, but after lowering derefs + * is too late to compact indices for that. + */ + ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images; /* NOTE: need to do something more clever when we support >1 fxn */ nir_foreach_register (reg, &fxn->registers) { @@ -3387,7 +3484,6 @@ fixup_binning_pass(struct ir3_context *ctx) so->outputs[j] = so->outputs[i]; /* fixup outidx to point to new output table entry: */ - struct ir3_instruction *out; foreach_output (out, ir) { if (out->collect.outidx == i) { out->collect.outidx = j; @@ -3431,10 +3527,16 @@ collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir) fetch->dst = instr->regs[0]->num; fetch->src = instr->prefetch.input_offset; + /* These are the limits on a5xx/a6xx, we might need to + * revisit if SP_FS_PREFETCH[n] changes on later gens: + */ + assert(fetch->dst <= 0x3f); + assert(fetch->tex_id <= 0x1f); + assert(fetch->samp_id < 0xf); + ctx->so->total_in = MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2); - /* Disable half precision until supported. */ fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF); /* Remove the prefetch placeholder instruction: */ @@ -3451,6 +3553,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, struct ir3_context *ctx; struct ir3 *ir; int ret = 0, max_bary; + bool progress; assert(!so->ir); @@ -3547,26 +3650,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, } } - /* at this point, for binning pass, throw away unneeded outputs: */ - if (so->binning_pass && (ctx->compiler->gpu_id < 600)) - fixup_binning_pass(ctx); - - ir3_debug_print(ir, "BEFORE CF"); - - ir3_cf(ir); - - ir3_debug_print(ir, "BEFORE CP"); - - ir3_cp(ir, so); - - /* at this point, for binning pass, throw away unneeded outputs: - * Note that for a6xx and later, we do this after ir3_cp to ensure - * that the uniform/constant layout for BS and VS matches, so that - * we can re-use same VS_CONST state group. - */ - if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) - fixup_binning_pass(ctx); - /* for a6xx+, binning and draw pass VS use same VBO state, so we * need to make sure not to remove any inputs that are used by * the nonbinning VS. @@ -3593,23 +3676,41 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, } } - ir3_debug_print(ir, "BEFORE GROUPING"); + /* at this point, for binning pass, throw away unneeded outputs: */ + if (so->binning_pass && (ctx->compiler->gpu_id < 600)) + fixup_binning_pass(ctx); - ir3_sched_add_deps(ir); + ir3_debug_print(ir, "AFTER: nir->ir3"); + ir3_validate(ir); - /* Group left/right neighbors, inserting mov's where needed to - * solve conflicts: - */ - ir3_group(ir); + do { + progress = false; - ir3_debug_print(ir, "AFTER GROUPING"); + progress |= IR3_PASS(ir, ir3_cf); + progress |= IR3_PASS(ir, ir3_cp, so); + progress |= IR3_PASS(ir, ir3_dce, so); + } while (progress); - ir3_dce(ir, so); + /* at this point, for binning pass, throw away unneeded outputs: + * Note that for a6xx and later, we do this after ir3_cp to ensure + * that the uniform/constant layout for BS and VS matches, so that + * we can re-use same VS_CONST state group. + */ + if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) { + fixup_binning_pass(ctx); + /* cleanup the result of removing unneeded outputs: */ + while (IR3_PASS(ir, ir3_dce, so)) {} + } - ir3_debug_print(ir, "AFTER DCE"); + IR3_PASS(ir, ir3_sched_add_deps); - /* do Sethi–Ullman numbering before scheduling: */ - ir3_sun(ir); + /* Group left/right neighbors, inserting mov's where needed to + * solve conflicts: + */ + IR3_PASS(ir, ir3_group); + + /* At this point, all the dead code should be long gone: */ + assert(!IR3_PASS(ir, ir3_dce, so)); ret = ir3_sched(ir); if (ret) { @@ -3617,7 +3718,12 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, goto out; } - ir3_debug_print(ir, "AFTER SCHED"); + ir3_debug_print(ir, "AFTER: ir3_sched"); + + if (IR3_PASS(ir, ir3_cp_postsched)) { + /* cleanup the result of removing unneeded mov's: */ + while (IR3_PASS(ir, ir3_dce, so)) {} + } /* Pre-assign VS inputs on a6xx+ binning pass shader, to align * with draw pass VS, so binning and draw pass can both use the @@ -3665,7 +3771,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor)); } else if (so->num_sampler_prefetch) { assert(so->type == MESA_SHADER_FRAGMENT); - struct ir3_instruction *instr, *precolor[2]; + struct ir3_instruction *precolor[2]; int idx = 0; foreach_input (instr, ir) { @@ -3689,13 +3795,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, goto out; } - ir3_postsched(ctx); - ir3_debug_print(ir, "AFTER POSTSCHED"); + IR3_PASS(ir, ir3_postsched, so); if (compiler->gpu_id >= 600) { - if (ir3_a6xx_fixup_atomic_dests(ir, so)) { - ir3_debug_print(ir, "AFTER ATOMIC FIXUP"); - } + IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so); } if (so->type == MESA_SHADER_FRAGMENT) @@ -3715,7 +3818,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, for (unsigned i = 0; i < so->outputs_count; i++) so->outputs[i].regid = INVALID_REG; - struct ir3_instruction *out; foreach_output (out, ir) { assert(out->opc == OPC_META_COLLECT); unsigned outidx = out->collect.outidx; @@ -3724,7 +3826,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF); } - struct ir3_instruction *in; foreach_input (in, ir) { assert(in->opc == OPC_META_INPUT); unsigned inidx = in->input.inidx; @@ -3750,9 +3851,7 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, /* We need to do legalize after (for frag shader's) the "bary.f" * offsets (inloc) have been assigned. */ - ir3_legalize(ir, so, &max_bary); - - ir3_debug_print(ir, "AFTER LEGALIZE"); + IR3_PASS(ir, ir3_legalize, so, &max_bary); /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't * know what we might have to wait on when coming in from VS chsh. @@ -3773,8 +3872,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler, if (so->type == MESA_SHADER_FRAGMENT) so->total_in = max_bary + 1; - so->max_sun = ir->max_sun; - /* Collect sampling instructions eligible for pre-dispatch. */ collect_tex_prefetches(ctx, ir);