X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Ffreedreno%2Fir3%2Fir3_shader.c;h=99cacbf3301308dc8f0b536a99d62244520e46f4;hb=f7bd3456d79aaeccb5f5e8d1408e85ad198f4f38;hp=92e3e7b251d5d1a91993a950f6e1bc77ecbddb86;hpb=8c97b3c5466e45f5139040e17c136d62fdd31c8a;p=mesa.git

diff --git a/src/freedreno/ir3/ir3_shader.c b/src/freedreno/ir3/ir3_shader.c
index 92e3e7b251d..99cacbf3301 100644
--- a/src/freedreno/ir3/ir3_shader.c
+++ b/src/freedreno/ir3/ir3_shader.c
@@ -24,9 +24,11 @@
  *    Rob Clark <robclark@freedesktop.org>
  */
 
+#include "util/u_atomic.h"
 #include "util/u_string.h"
+#include "util/u_math.h"
 #include "util/u_memory.h"
-#include "util/u_format.h"
+#include "util/format/u_format.h"
 
 #include "drm/freedreno_drmif.h"
 
@@ -34,24 +36,14 @@
 #include "ir3_compiler.h"
 #include "ir3_nir.h"
 
+#include "disasm.h"
+
 int
 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
 {
 	return glsl_count_attribute_slots(type, false);
 }
 
-static void
-delete_variant(struct ir3_shader_variant *v)
-{
-	if (v->ir)
-		ir3_destroy(v->ir);
-	if (v->bo)
-		fd_bo_del(v->bo);
-	if (v->immediates)
-		free(v->immediates);
-	free(v);
-}
-
 /* for vertex shader, the inputs are loaded into registers before the shader
  * is executed, so max_regs from the shader instructions might not properly
  * reflect the # of registers actually used, especially in case passthrough
@@ -63,7 +55,7 @@ delete_variant(struct ir3_shader_variant *v)
  * the reg off.
  */
 static void
-fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
+fixup_regfootprint(struct ir3_shader_variant *v)
 {
 	unsigned i;
 
@@ -85,7 +77,7 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
 			unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
 			int32_t regid = v->inputs[i].regid + n;
 			if (v->inputs[i].half) {
-				if (gpu_id < 500) {
+				if (!v->mergedregs) {
 					v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 				} else {
 					v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
@@ -97,9 +89,26 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
 	}
 
 	for (i = 0; i < v->outputs_count; i++) {
+		/* for ex, VS shaders with tess don't have normal varying outs: */
+		if (!VALIDREG(v->outputs[i].regid))
+			continue;
 		int32_t regid = v->outputs[i].regid + 3;
 		if (v->outputs[i].half) {
-			if (gpu_id < 500) {
+			if (!v->mergedregs) {
+				v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
+			} else {
+				v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
+			}
+		} else {
+			v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
+		}
+	}
+
+	for (i = 0; i < v->num_sampler_prefetch; i++) {
+		unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
+		int32_t regid = v->sampler_prefetch[i].dst + n;
+		if (v->sampler_prefetch[i].half_precision) {
+			if (!v->mergedregs) {
 				v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 			} else {
 				v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
@@ -113,11 +122,12 @@ fixup_regfootprint(struct ir3_shader_variant *v, uint32_t gpu_id)
 /* wrapper for ir3_assemble() which does some info fixup based on
  * shader state.  Non-static since used by ir3_cmdline too.
  */
-void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
+void * ir3_shader_assemble(struct ir3_shader_variant *v)
 {
+	unsigned gpu_id = v->shader->compiler->gpu_id;
 	void *bin;
 
-	bin = ir3_assemble(v->ir, &v->info, gpu_id);
+	bin = ir3_assemble(v);
 	if (!bin)
 		return NULL;
 
@@ -133,7 +143,14 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 	 */
 	v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 
-	fixup_regfootprint(v, gpu_id);
+	/* On a4xx and newer, constlen must be a multiple of 16 dwords even though
+	 * uploads are in units of 4 dwords. Round it up here to make calculations
+	 * regarding the shared constlen simpler.
+	 */
+	if (gpu_id >= 400)
+		v->constlen = align(v->constlen, 4);
+
+	fixup_regfootprint(v);
 
 	return bin;
 }
@@ -141,169 +158,335 @@ void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id)
 static void
 assemble_variant(struct ir3_shader_variant *v)
 {
-	struct ir3_compiler *compiler = v->shader->compiler;
-	struct shader_info *info = &v->shader->nir->info;
-	uint32_t gpu_id = compiler->gpu_id;
-	uint32_t sz, *bin;
-
-	bin = ir3_shader_assemble(v, gpu_id);
-	sz = v->info.sizedwords * 4;
-
-	v->bo = fd_bo_new(compiler->dev, sz,
-			DRM_FREEDRENO_GEM_CACHE_WCOMBINE |
-			DRM_FREEDRENO_GEM_TYPE_KMEM,
-			"%s:%s", ir3_shader_stage(v->shader), info->name);
-
-	memcpy(fd_bo_map(v->bo), bin, sz);
-
-	if (ir3_shader_debug & IR3_DBG_DISASM) {
-		struct ir3_shader_key key = v->key;
-		printf("disassemble: type=%d, k={bp=%u,cts=%u,hp=%u}", v->type,
-			v->binning_pass, key.color_two_side, key.half_precision);
-		ir3_shader_disasm(v, bin, stdout);
-	}
+	v->bin = ir3_shader_assemble(v);
 
 	if (shader_debug_enabled(v->shader->type)) {
-		fprintf(stderr, "Native code for unnamed %s shader %s:\n",
-			_mesa_shader_stage_to_string(v->shader->type),
-			v->shader->nir->info.name);
+		fprintf(stdout, "Native code for unnamed %s shader %s:\n",
+			ir3_shader_stage(v), v->shader->nir->info.name);
 		if (v->shader->type == MESA_SHADER_FRAGMENT)
-			fprintf(stderr, "SIMD0\n");
-		ir3_shader_disasm(v, bin, stderr);
+			fprintf(stdout, "SIMD0\n");
+		ir3_shader_disasm(v, v->bin, stdout);
 	}
 
-	free(bin);
-
 	/* no need to keep the ir around beyond this point: */
 	ir3_destroy(v->ir);
 	v->ir = NULL;
 }
 
+static bool
+compile_variant(struct ir3_shader_variant *v)
+{
+	int ret = ir3_compile_shader_nir(v->shader->compiler, v);
+	if (ret) {
+		_debug_printf("compile failed! (%s:%s)", v->shader->nir->info.name,
+				v->shader->nir->info.label);
+		return false;
+	}
+
+	assemble_variant(v);
+	if (!v->bin) {
+		_debug_printf("assemble failed! (%s:%s)", v->shader->nir->info.name,
+				v->shader->nir->info.label);
+		return false;
+	}
+
+	return true;
+}
+
+/*
+ * For creating normal shader variants, 'nonbinning' is NULL.  For
+ * creating binning pass shader, it is link to corresponding normal
+ * (non-binning) variant.
+ */
 static struct ir3_shader_variant *
-create_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
-		bool binning_pass)
+alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
+		struct ir3_shader_variant *nonbinning)
 {
-	struct ir3_shader_variant *v = CALLOC_STRUCT(ir3_shader_variant);
-	int ret;
+	void *mem_ctx = shader;
+	/* hang the binning variant off it's non-binning counterpart instead
+	 * of the shader, to simplify the error cleanup paths
+	 */
+	if (nonbinning)
+		mem_ctx = nonbinning;
+	struct ir3_shader_variant *v = rzalloc_size(mem_ctx, sizeof(*v));
 
 	if (!v)
 		return NULL;
 
 	v->id = ++shader->variant_count;
 	v->shader = shader;
-	v->binning_pass = binning_pass;
+	v->binning_pass = !!nonbinning;
+	v->nonbinning = nonbinning;
 	v->key = *key;
 	v->type = shader->type;
+	v->mergedregs = shader->compiler->gpu_id >= 600;
 
-	ret = ir3_compile_shader_nir(shader->compiler, v);
-	if (ret) {
-		debug_error("compile failed!");
+	if (!v->binning_pass)
+		v->const_state = rzalloc_size(v, sizeof(*v->const_state));
+
+	return v;
+}
+
+static bool
+needs_binning_variant(struct ir3_shader_variant *v)
+{
+	if ((v->type == MESA_SHADER_VERTEX) && ir3_has_binning_vs(&v->key))
+		return true;
+	return false;
+}
+
+static struct ir3_shader_variant *
+create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
+{
+	struct ir3_shader_variant *v = alloc_variant(shader, key, NULL);
+
+	if (!v)
 		goto fail;
+
+	if (needs_binning_variant(v)) {
+		v->binning = alloc_variant(shader, key, v);
+		if (!v->binning)
+			goto fail;
 	}
 
-	assemble_variant(v);
-	if (!v->bo) {
-		debug_error("assemble failed!");
-		goto fail;
+	if (ir3_disk_cache_retrieve(shader->compiler, v))
+		return v;
+
+	if (!shader->nir_finalized) {
+		ir3_nir_post_finalize(shader->compiler, shader->nir);
+
+		if (ir3_shader_debug & IR3_DBG_DISASM) {
+			printf("dump nir%d: type=%d", shader->id, shader->type);
+			nir_print_shader(shader->nir, stdout);
+		}
+
+		shader->nir_finalized = true;
 	}
 
+	if (!compile_variant(v))
+		goto fail;
+
+	if (needs_binning_variant(v) && !compile_variant(v->binning))
+		goto fail;
+
+	ir3_disk_cache_store(shader->compiler, v);
+
 	return v;
 
 fail:
-	delete_variant(v);
+	ralloc_free(v);
 	return NULL;
 }
 
 static inline struct ir3_shader_variant *
-shader_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
-		bool *created)
+shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
 {
 	struct ir3_shader_variant *v;
 
-	*created = false;
-
 	for (v = shader->variants; v; v = v->next)
 		if (ir3_shader_key_equal(key, &v->key))
 			return v;
 
-	/* compile new variant if it doesn't exist already: */
-	v = create_variant(shader, key, false);
-	if (v) {
-		v->next = shader->variants;
-		shader->variants = v;
-		*created = true;
-	}
-
-	return v;
+	return NULL;
 }
 
 struct ir3_shader_variant *
-ir3_shader_get_variant(struct ir3_shader *shader, struct ir3_shader_key *key,
+ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 		bool binning_pass, bool *created)
 {
-	struct ir3_shader_variant *v =
-			shader_variant(shader, key, created);
+	mtx_lock(&shader->variants_lock);
+	struct ir3_shader_variant *v = shader_variant(shader, key);
+
+	if (!v) {
+		/* compile new variant if it doesn't exist already: */
+		v = create_variant(shader, key);
+		if (v) {
+			v->next = shader->variants;
+			shader->variants = v;
+			*created = true;
+		}
+	}
 
 	if (v && binning_pass) {
-		if (!v->binning)
-			v->binning = create_variant(shader, key, true);
-		return v->binning;
+		v = v->binning;
+		assert(v);
 	}
 
+	mtx_unlock(&shader->variants_lock);
+
 	return v;
 }
 
 void
 ir3_shader_destroy(struct ir3_shader *shader)
 {
-	struct ir3_shader_variant *v, *t;
-	for (v = shader->variants; v; ) {
-		t = v;
-		v = v->next;
-		delete_variant(t);
-	}
 	ralloc_free(shader->nir);
-	free(shader);
+	mtx_destroy(&shader->variants_lock);
+	ralloc_free(shader);
 }
 
-struct ir3_shader *
-ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir)
+/**
+ * Creates a bitmask of the used bits of the shader key by this particular
+ * shader.  Used by the gallium driver to skip state-dependent recompiles when
+ * possible.
+ */
+static void
+ir3_setup_used_key(struct ir3_shader *shader)
 {
-	struct ir3_shader *shader = CALLOC_STRUCT(ir3_shader);
+	nir_shader *nir = shader->nir;
+	struct shader_info *info = &nir->info;
+	struct ir3_shader_key *key = &shader->key_mask;
 
-	shader->compiler = compiler;
-	shader->id = ++shader->compiler->shader_count;
-	shader->type = nir->info.stage;
+	/* This key flag is just used to make for a cheaper ir3_shader_key_equal
+	 * check in the common case.
+	 */
+	key->has_per_samp = true;
 
-	NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
-			   (nir_lower_io_options)0);
+	key->safe_constlen = true;
+
+	key->ucp_enables = 0xff;
+
+	if (info->stage == MESA_SHADER_FRAGMENT) {
+		key->fsaturate_s = ~0;
+		key->fsaturate_t = ~0;
+		key->fsaturate_r = ~0;
+		key->fastc_srgb = ~0;
+		key->fsamples = ~0;
+
+		if (info->inputs_read & VARYING_BITS_COLOR) {
+			key->rasterflat = true;
+			key->color_two_side = true;
+		}
 
-	if (nir->info.stage == MESA_SHADER_FRAGMENT) {
-		/* NOTE: lower load_barycentric_at_sample first, since it
-		 * produces load_barycentric_at_offset:
+		if (info->inputs_read & VARYING_BIT_LAYER) {
+			key->layer_zero = true;
+		}
+
+		if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
+								FRAG_RESULT_STENCIL |
+								FRAG_RESULT_SAMPLE_MASK)) != 0) {
+			key->fclamp_color = true;
+		}
+
+		/* Only used for deciding on behavior of
+		 * nir_intrinsic_load_barycentric_sample
 		 */
-		NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
-		NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
+		key->msaa = info->fs.uses_sample_qualifier;
+	} else {
+		key->tessellation = ~0;
+		key->has_gs = true;
+
+		if (info->outputs_written & VARYING_BITS_COLOR)
+			key->vclamp_color = true;
+
+		if (info->stage == MESA_SHADER_VERTEX) {
+			key->vsaturate_s = ~0;
+			key->vsaturate_t = ~0;
+			key->vsaturate_r = ~0;
+			key->vastc_srgb = ~0;
+			key->vsamples = ~0;
+		}
+	}
+}
 
-		NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
+
+/* Given an array of constlen's, decrease some of them so that the sum stays
+ * within "combined_limit" while trying to fairly share the reduction. Returns
+ * a bitfield of which stages should be trimmed.
+ */
+static uint32_t
+trim_constlens(unsigned *constlens,
+			   unsigned first_stage, unsigned last_stage,
+			   unsigned combined_limit, unsigned safe_limit)
+{
+   unsigned cur_total = 0;
+   for (unsigned i = first_stage; i <= last_stage; i++) {
+      cur_total += constlens[i];
+   }
+
+   unsigned max_stage = 0;
+   unsigned max_const = 0;
+   uint32_t trimmed = 0;
+
+   while (cur_total > combined_limit) {
+	   for (unsigned i = first_stage; i <= last_stage; i++) {
+		   if (constlens[i] >= max_const) {
+			   max_stage = i;
+			   max_const = constlens[i];
+		   }
+	   }
+
+	   assert(max_const > safe_limit);
+	   trimmed |= 1 << max_stage;
+	   cur_total = cur_total - max_const + safe_limit;
+	   constlens[max_stage] = safe_limit;
+   }
+
+   return trimmed;
+}
+
+/* Figures out which stages in the pipeline to use the "safe" constlen for, in
+ * order to satisfy all shared constlen limits.
+ */
+uint32_t
+ir3_trim_constlen(struct ir3_shader_variant **variants,
+				  const struct ir3_compiler *compiler)
+{
+	unsigned constlens[MESA_SHADER_STAGES] = {};
+
+	for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+		if (variants[i])
+			constlens[i] = variants[i]->constlen;
 	}
 
-	NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
+	uint32_t trimmed = 0;
+	STATIC_ASSERT(MESA_SHADER_STAGES <= 8 * sizeof(trimmed));
 
-	/* do first pass optimization, ignoring the key: */
-	shader->nir = ir3_optimize_nir(shader, nir, NULL);
-	if (ir3_shader_debug & IR3_DBG_DISASM) {
-		printf("dump nir%d: type=%d", shader->id, shader->type);
-		nir_print_shader(shader->nir, stdout);
+	/* There are two shared limits to take into account, the geometry limit on
+	 * a6xx and the total limit. The frag limit on a6xx only matters for a
+	 * single stage, so it's always satisfied with the first variant.
+	 */
+	if (compiler->gpu_id >= 600) {
+		trimmed |=
+			trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_GEOMETRY,
+						   compiler->max_const_geom, compiler->max_const_safe);
 	}
+	trimmed |=
+		trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_FRAGMENT,
+					   compiler->max_const_pipeline, compiler->max_const_safe);
+
+	return trimmed;
+}
+
+struct ir3_shader *
+ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
+		unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
+{
+	struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
+
+	mtx_init(&shader->variants_lock, mtx_plain);
+	shader->compiler = compiler;
+	shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
+	shader->type = nir->info.stage;
+	if (stream_output)
+		memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
+	shader->num_reserved_user_consts = reserved_user_consts;
+	shader->nir = nir;
+
+	ir3_disk_cache_init_shader_key(compiler, shader);
+
+	ir3_setup_used_key(shader);
 
 	return shader;
 }
 
 static void dump_reg(FILE *out, const char *name, uint32_t r)
 {
-	if (r != regid(63,0))
-		fprintf(out, "; %s: r%d.%c\n", name, r >> 2, "xyzw"[r & 0x3]);
+	if (r != regid(63,0)) {
+		const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
+		fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
+				(r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
+	}
 }
 
 static void dump_output(FILE *out, struct ir3_shader_variant *so,
@@ -314,114 +497,137 @@ static void dump_output(FILE *out, struct ir3_shader_variant *so,
 	dump_reg(out, name, regid);
 }
 
+static const char *
+input_name(struct ir3_shader_variant *so, int i)
+{
+	if (so->inputs[i].sysval) {
+		return gl_system_value_name(so->inputs[i].slot);
+	} else if (so->type == MESA_SHADER_VERTEX) {
+		return gl_vert_attrib_name(so->inputs[i].slot);
+	} else {
+		return gl_varying_slot_name(so->inputs[i].slot);
+	}
+}
+
+static const char *
+output_name(struct ir3_shader_variant *so, int i)
+{
+	if (so->type == MESA_SHADER_FRAGMENT) {
+		return gl_frag_result_name(so->outputs[i].slot);
+	} else {
+		switch (so->outputs[i].slot) {
+		case VARYING_SLOT_GS_HEADER_IR3:
+			return "GS_HEADER";
+		case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
+			return "GS_VERTEX_FLAGS";
+		case VARYING_SLOT_TCS_HEADER_IR3:
+			return "TCS_HEADER";
+		default:
+			return gl_varying_slot_name(so->outputs[i].slot);
+		}
+	}
+}
+
 void
 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 {
 	struct ir3 *ir = so->ir;
 	struct ir3_register *reg;
-	const char *type = ir3_shader_stage(so->shader);
+	const char *type = ir3_shader_stage(so);
 	uint8_t regid;
 	unsigned i;
 
-	for (i = 0; i < ir->ninputs; i++) {
-		if (!ir->inputs[i]) {
-			fprintf(out, "; in%d unused\n", i);
-			continue;
-		}
-		reg = ir->inputs[i]->regs[0];
+	foreach_input_n (instr, i, ir) {
+		reg = instr->regs[0];
 		regid = reg->num;
-		fprintf(out, "@in(%sr%d.%c)\tin%d\n",
+		fprintf(out, "@in(%sr%d.%c)\tin%d",
 				(reg->flags & IR3_REG_HALF) ? "h" : "",
 				(regid >> 2), "xyzw"[regid & 0x3], i);
+
+		if (reg->wrmask > 0x1)
+			fprintf(out, " (wrmask=0x%x)", reg->wrmask);
+		fprintf(out, "\n");
 	}
 
-	for (i = 0; i < ir->noutputs; i++) {
-		if (!ir->outputs[i]) {
-			fprintf(out, "; out%d unused\n", i);
-			continue;
-		}
-		/* kill shows up as a virtual output.. skip it! */
-		if (is_kill(ir->outputs[i]))
-			continue;
-		reg = ir->outputs[i]->regs[0];
+	/* print pre-dispatch texture fetches: */
+	for (i = 0; i < so->num_sampler_prefetch; i++) {
+		const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
+		fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
+				fetch->half_precision ? "h" : "",
+				fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
+				fetch->src, fetch->samp_id, fetch->tex_id,
+				fetch->wrmask, fetch->cmd);
+	}
+
+	foreach_output_n (instr, i, ir) {
+		reg = instr->regs[0];
 		regid = reg->num;
-		fprintf(out, "@out(%sr%d.%c)\tout%d\n",
+		fprintf(out, "@out(%sr%d.%c)\tout%d",
 				(reg->flags & IR3_REG_HALF) ? "h" : "",
 				(regid >> 2), "xyzw"[regid & 0x3], i);
+		if (reg->wrmask > 0x1)
+			fprintf(out, " (wrmask=0x%x)", reg->wrmask);
+		fprintf(out, "\n");
 	}
 
-	for (i = 0; i < so->immediates_count; i++) {
-		fprintf(out, "@const(c%d.x)\t", so->constbase.immediate + i);
+	const struct ir3_const_state *const_state = ir3_const_state(so);
+	for (i = 0; i < const_state->immediates_count; i++) {
+		fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 		fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
-				so->immediates[i].val[0],
-				so->immediates[i].val[1],
-				so->immediates[i].val[2],
-				so->immediates[i].val[3]);
+				const_state->immediates[i].val[0],
+				const_state->immediates[i].val[1],
+				const_state->immediates[i].val[2],
+				const_state->immediates[i].val[3]);
 	}
 
 	disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 
-	switch (so->type) {
-	case MESA_SHADER_VERTEX:
-		fprintf(out, "; %s: outputs:", type);
-		for (i = 0; i < so->outputs_count; i++) {
-			uint8_t regid = so->outputs[i].regid;
-			fprintf(out, " r%d.%c (%s)",
-					(regid >> 2), "xyzw"[regid & 0x3],
-					gl_varying_slot_name(so->outputs[i].slot));
-		}
-		fprintf(out, "\n");
-		fprintf(out, "; %s: inputs:", type);
-		for (i = 0; i < so->inputs_count; i++) {
-			uint8_t regid = so->inputs[i].regid;
-			fprintf(out, " r%d.%c (cm=%x,il=%u,b=%u)",
-					(regid >> 2), "xyzw"[regid & 0x3],
-					so->inputs[i].compmask,
-					so->inputs[i].inloc,
-					so->inputs[i].bary);
-		}
-		fprintf(out, "\n");
-		break;
-	case MESA_SHADER_FRAGMENT:
-		fprintf(out, "; %s: outputs:", type);
-		for (i = 0; i < so->outputs_count; i++) {
-			uint8_t regid = so->outputs[i].regid;
-			fprintf(out, " r%d.%c (%s)",
-					(regid >> 2), "xyzw"[regid & 0x3],
-					gl_frag_result_name(so->outputs[i].slot));
-		}
-		fprintf(out, "\n");
-		fprintf(out, "; %s: inputs:", type);
-		for (i = 0; i < so->inputs_count; i++) {
-			uint8_t regid = so->inputs[i].regid;
-			fprintf(out, " r%d.%c (%s,cm=%x,il=%u,b=%u)",
-					(regid >> 2), "xyzw"[regid & 0x3],
-					gl_varying_slot_name(so->inputs[i].slot),
-					so->inputs[i].compmask,
-					so->inputs[i].inloc,
-					so->inputs[i].bary);
-		}
-		fprintf(out, "\n");
-		break;
-	default:
-		/* TODO */
-		break;
+	fprintf(out, "; %s: outputs:", type);
+	for (i = 0; i < so->outputs_count; i++) {
+		uint8_t regid = so->outputs[i].regid;
+		const char *reg_type = so->outputs[i].half ? "hr" : "r";
+		fprintf(out, " %s%d.%c (%s)",
+				reg_type, (regid >> 2), "xyzw"[regid & 0x3],
+				output_name(so, i));
+	}
+	fprintf(out, "\n");
+
+	fprintf(out, "; %s: inputs:", type);
+	for (i = 0; i < so->inputs_count; i++) {
+		uint8_t regid = so->inputs[i].regid;
+		fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
+				(regid >> 2), "xyzw"[regid & 0x3],
+				input_name(so, i),
+				so->inputs[i].slot,
+				so->inputs[i].compmask,
+				so->inputs[i].inloc,
+				so->inputs[i].bary);
 	}
+	fprintf(out, "\n");
 
 	/* print generic shader info: */
-	fprintf(out, "; %s prog %d/%d: %u instructions, %d half, %d full\n",
+	fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 			type, so->shader->id, so->id,
 			so->info.instrs_count,
-			so->info.max_half_reg + 1,
-			so->info.max_reg + 1);
+			so->info.nops_count,
+			so->info.instrs_count - so->info.nops_count,
+			so->info.mov_count, so->info.cov_count,
+			so->info.sizedwords);
 
-	fprintf(out, "; %d const, %u constlen\n",
-			so->info.max_const + 1,
+	fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
+			type, so->shader->id, so->id,
+			so->info.last_baryf,
+			so->info.max_half_reg + 1,
+			so->info.max_reg + 1,
 			so->constlen);
 
-	fprintf(out, "; %u (ss), %u (sy)\n", so->info.ss, so->info.sy);
-
-	fprintf(out, "; max_sun=%u\n", ir->max_sun);
+	fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
+			type, so->shader->id, so->id,
+			so->info.sstall,
+			so->info.ss,
+			so->info.sy,
+			so->max_sun,
+			so->loops);
 
 	/* print shader type specific info: */
 	switch (so->type) {
@@ -431,11 +637,11 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 		break;
 	case MESA_SHADER_FRAGMENT:
 		dump_reg(out, "pos (ij_pixel)",
-			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PIXEL));
+			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 		dump_reg(out, "pos (ij_centroid)",
-			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_CENTROID));
+			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 		dump_reg(out, "pos (ij_size)",
-			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_SIZE));
+			ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 		dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 		if (so->color0_mrt) {
 			dump_output(out, so, FRAG_RESULT_COLOR, "color");
@@ -449,13 +655,10 @@ ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 			dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 			dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 		}
-		/* these two are hard-coded since we don't know how to
-		 * program them to anything but all 0's...
-		 */
-		if (so->frag_coord)
-			fprintf(out, "; fragcoord: r0.x\n");
-		if (so->frag_face)
-			fprintf(out, "; fragface: hr0.x\n");
+		dump_reg(out, "fragcoord",
+			ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
+		dump_reg(out, "fragface",
+			ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 		break;
 	default:
 		/* TODO */