X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Ffreedreno%2Fir3%2Fregmask.h;h=4dded900b4dd70035b9d09ba09a0105711275a3c;hb=66d8bbd822914f27814d05d2d21196072f41284b;hp=6eade8daf01b94c5ca61921c40f8ca48f08dde26;hpb=bb98b71893f9f0f8dc277f3e55f652e0cd398666;p=mesa.git

diff --git a/src/freedreno/ir3/regmask.h b/src/freedreno/ir3/regmask.h
index 6eade8daf01..4dded900b4d 100644
--- a/src/freedreno/ir3/regmask.h
+++ b/src/freedreno/ir3/regmask.h
@@ -86,6 +86,31 @@ __regmask_set(regmask_t *regmask, bool half, unsigned n)
 	}
 }
 
+static inline void
+__regmask_clear(regmask_t *regmask, bool half, unsigned n)
+{
+	if (regmask->mergedregs) {
+		/* a6xx+ case, with merged register file, we track things in terms
+		 * of half-precision registers, with a full precisions register
+		 * using two half-precision slots:
+		 */
+		if (half) {
+			BITSET_CLEAR(regmask->mask, n);
+		} else {
+			n *= 2;
+			BITSET_CLEAR(regmask->mask, n);
+			BITSET_CLEAR(regmask->mask, n+1);
+		}
+	} else {
+		/* pre a6xx case, with separate register file for half and full
+		 * precision:
+		 */
+		if (half)
+			n += MAX_REG;
+		BITSET_CLEAR(regmask->mask, n);
+	}
+}
+
 static inline void
 regmask_init(regmask_t *regmask, bool mergedregs)
 {