X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Ffreedreno%2Fvulkan%2Ftu_pipeline.c;h=54d011b002ad2644b205221f30e41b8b467edb72;hb=2fbc12a0ac0472b85922c406ce14931091d74eb6;hp=ef1422fa708bb0871239be0f663b71c28b34d947;hpb=8f11cc4cad7feb8d78f37709baac36c6a22034c6;p=mesa.git diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c index ef1422fa708..54d011b002a 100644 --- a/src/freedreno/vulkan/tu_pipeline.c +++ b/src/freedreno/vulkan/tu_pipeline.c @@ -243,9 +243,8 @@ struct tu_pipeline_builder struct tu_shader *shaders[MESA_SHADER_STAGES]; struct ir3_shader_variant *variants[MESA_SHADER_STAGES]; struct ir3_shader_variant *binning_variant; - uint32_t shader_offsets[MESA_SHADER_STAGES]; - uint32_t binning_vs_offset; - uint32_t shader_total_size; + uint64_t shader_iova[MESA_SHADER_STAGES]; + uint64_t binning_vs_iova; bool rasterizer_discard; /* these states are affectd by rasterizer_discard */ @@ -413,7 +412,7 @@ tu6_emit_xs_config(struct tu_cs *cs, tu_cs_emit(cs, xs->instrlen); tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1); - tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(xs->constlen, 4)) | + tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) | A6XX_HLSQ_VS_CNTL_ENABLED); /* emit program binary @@ -494,6 +493,8 @@ tu6_emit_cs_config(struct tu_cs *cs, const struct tu_shader *shader, static void tu6_emit_vs_system_values(struct tu_cs *cs, const struct ir3_shader_variant *vs, + const struct ir3_shader_variant *hs, + const struct ir3_shader_variant *ds, const struct ir3_shader_variant *gs, bool primid_passthru) { @@ -501,6 +502,21 @@ tu6_emit_vs_system_values(struct tu_cs *cs, ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID); const uint32_t instanceid_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID); + const uint32_t tess_coord_x_regid = hs ? + ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD) : + regid(63, 0); + const uint32_t tess_coord_y_regid = VALIDREG(tess_coord_x_regid) ? + tess_coord_x_regid + 1 : + regid(63, 0); + const uint32_t hs_patch_regid = hs ? + ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID) : + regid(63, 0); + const uint32_t ds_patch_regid = hs ? + ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID) : + regid(63, 0); + const uint32_t hs_invocation_regid = hs ? + ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3) : + regid(63, 0); const uint32_t primitiveid_regid = gs ? ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID) : regid(63, 0); @@ -513,8 +529,12 @@ tu6_emit_vs_system_values(struct tu_cs *cs, A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) | A6XX_VFD_CONTROL_1_REGID4PRIMID(primitiveid_regid) | 0xfc000000); - tu_cs_emit(cs, 0x0000fcfc); /* VFD_CONTROL_2 */ - tu_cs_emit(cs, 0xfcfcfcfc); /* VFD_CONTROL_3 */ + tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) | + A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid)); + tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) | + A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) | + A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) | + 0xfc); tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */ tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) | 0xfc00); /* VFD_CONTROL_5 */ @@ -570,20 +590,28 @@ tu6_link_streamout(struct ir3_shader_linkage *l, } static void -tu6_setup_streamout(const struct ir3_shader_variant *v, - struct ir3_shader_linkage *l, struct tu_streamout_state *tf) +tu6_setup_streamout(struct tu_cs *cs, + const struct ir3_shader_variant *v, + struct ir3_shader_linkage *l) { const struct ir3_stream_output_info *info = &v->shader->stream_output; + uint32_t prog[IR3_MAX_SO_OUTPUTS * 2] = {}; + uint32_t ncomp[IR3_MAX_SO_BUFFERS] = {}; + uint32_t prog_count = align(l->max_loc, 2) / 2; - memset(tf, 0, sizeof(*tf)); - - tf->prog_count = align(l->max_loc, 2) / 2; + /* TODO: streamout state should be in a non-GMEM draw state */ - debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog)); + /* no streamout: */ + if (info->num_outputs == 0) { + tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 4); + tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL); + tu_cs_emit(cs, 0); + tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL); + tu_cs_emit(cs, 0); + return; + } - /* set stride info to the streamout state */ - for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) - tf->stride[i] = info->stride[i]; + /* is there something to do with info->stride[i]? */ for (unsigned i = 0; i < info->num_outputs; i++) { const struct ir3_stream_output *out = &info->output[i]; @@ -594,7 +622,7 @@ tu6_setup_streamout(const struct ir3_shader_variant *v, if (v->outputs[k].regid == INVALID_REG) continue; - tf->ncomp[out->output_buffer] += out->num_components; + ncomp[out->output_buffer] += out->num_components; /* linkage map sorted by order frag shader wants things, so * a bit less ideal here.. @@ -611,22 +639,35 @@ tu6_setup_streamout(const struct ir3_shader_variant *v, unsigned off = j + out->dst_offset; /* in dwords */ if (loc & 1) { - tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN | - A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) | - A6XX_VPC_SO_PROG_B_OFF(off * 4); + prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN | + A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) | + A6XX_VPC_SO_PROG_B_OFF(off * 4); } else { - tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN | - A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) | - A6XX_VPC_SO_PROG_A_OFF(off * 4); + prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN | + A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) | + A6XX_VPC_SO_PROG_A_OFF(off * 4); } } } - tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE | - COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) | - COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) | - COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) | - COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3); + tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 12 + 2 * prog_count); + tu_cs_emit(cs, REG_A6XX_VPC_SO_BUF_CNTL); + tu_cs_emit(cs, A6XX_VPC_SO_BUF_CNTL_ENABLE | + COND(ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) | + COND(ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) | + COND(ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) | + COND(ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3)); + for (uint32_t i = 0; i < 4; i++) { + tu_cs_emit(cs, REG_A6XX_VPC_SO_NCOMP(i)); + tu_cs_emit(cs, ncomp[i]); + } + /* note: "VPC_SO_CNTL" write seems to be responsible for resetting the SO_PROG */ + tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL); + tu_cs_emit(cs, A6XX_VPC_SO_CNTL_ENABLE); + for (uint32_t i = 0; i < prog_count; i++) { + tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG); + tu_cs_emit(cs, prog[i]); + } } static void @@ -652,7 +693,9 @@ tu6_emit_const(struct tu_cs *cs, uint32_t opcode, uint32_t base, static void tu6_emit_link_map(struct tu_cs *cs, const struct ir3_shader_variant *producer, - const struct ir3_shader_variant *consumer) { + const struct ir3_shader_variant *consumer, + enum a6xx_state_block sb) +{ const struct ir3_const_state *const_state = ir3_const_state(consumer); uint32_t base = const_state->offsets.primitive_map; uint32_t patch_locs[MAX_VARYING] = { }, num_loc; @@ -663,8 +706,8 @@ tu6_emit_link_map(struct tu_cs *cs, if (size <= 0) return; - tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, SB6_GS_SHADER, 0, size, - patch_locs); + tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, base, sb, 0, size, + patch_locs); } static uint16_t @@ -684,11 +727,19 @@ gl_primitive_to_tess(uint16_t primitive) { void tu6_emit_vpc(struct tu_cs *cs, const struct ir3_shader_variant *vs, + const struct ir3_shader_variant *hs, + const struct ir3_shader_variant *ds, const struct ir3_shader_variant *gs, - const struct ir3_shader_variant *fs, - struct tu_streamout_state *tf) + const struct ir3_shader_variant *fs) { - const struct ir3_shader_variant *last_shader = gs ?: vs; + const struct ir3_shader_variant *last_shader; + if (gs) { + last_shader = gs; + } else if (hs) { + last_shader = ds; + } else { + last_shader = vs; + } struct ir3_shader_linkage linkage = { .primid_loc = 0xff }; if (fs) ir3_link_shaders(&linkage, last_shader, fs, true); @@ -700,7 +751,7 @@ tu6_emit_vpc(struct tu_cs *cs, * passthrough needs to be enabled. */ bool primid_passthru = linkage.primid_loc != 0xff; - tu6_emit_vs_system_values(cs, vs, gs, primid_passthru); + tu6_emit_vs_system_values(cs, vs, hs, ds, gs, primid_passthru); tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4); tu_cs_emit(cs, ~linkage.varmask[0]); @@ -730,8 +781,7 @@ tu6_emit_vpc(struct tu_cs *cs, ir3_link_add(&linkage, pointsize_regid, 0x1, linkage.max_loc); } - if (last_shader->shader->stream_output.num_outputs) - tu6_setup_streamout(last_shader, &linkage, tf); + tu6_setup_streamout(cs, last_shader, &linkage); /* map outputs of the last shader to VPC */ assert(linkage.cnt <= 32); @@ -749,12 +799,16 @@ tu6_emit_vpc(struct tu_cs *cs, if (gs) tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_OUT_REG(0), sp_out_count); + else if (hs) + tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_OUT_REG(0), sp_out_count); else tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_OUT_REG(0), sp_out_count); tu_cs_emit_array(cs, sp_out, sp_out_count); if (gs) tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_VPC_DST_REG(0), sp_vpc_dst_count); + else if (hs) + tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_VPC_DST_REG(0), sp_vpc_dst_count); else tu_cs_emit_pkt4(cs, REG_A6XX_SP_VS_VPC_DST_REG(0), sp_vpc_dst_count); tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count); @@ -770,14 +824,100 @@ tu6_emit_vpc(struct tu_cs *cs, tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1); tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) | - A6XX_VPC_PACK_PSIZELOC(pointsize_loc) | - A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc)); + A6XX_VPC_PACK_PSIZELOC(pointsize_loc) | + A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc)); + + if (hs) { + shader_info *hs_info = &hs->shader->nir->info; + tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1); + tu_cs_emit(cs, hs_info->tess.tcs_vertices_out); + + /* Total attribute slots in HS incoming patch. */ + tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1); + tu_cs_emit(cs, + hs_info->tess.tcs_vertices_out * vs->output_size / 4); + + tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1); + tu_cs_emit(cs, vs->output_size); + /* In SPIR-V generated from GLSL, the tessellation primitive params are + * are specified in the tess eval shader, but in SPIR-V generated from + * HLSL, they are specified in the tess control shader. */ + shader_info *tess_info = + ds->shader->nir->info.tess.spacing == TESS_SPACING_UNSPECIFIED ? + &hs->shader->nir->info : &ds->shader->nir->info; + tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_CNTL, 1); + uint32_t output; + if (tess_info->tess.point_mode) + output = TESS_POINTS; + else if (tess_info->tess.primitive_mode == GL_ISOLINES) + output = TESS_LINES; + else if (tess_info->tess.ccw) + output = TESS_CCW_TRIS; + else + output = TESS_CW_TRIS; + + enum a6xx_tess_spacing spacing; + switch (tess_info->tess.spacing) { + case TESS_SPACING_EQUAL: + spacing = TESS_EQUAL; + break; + case TESS_SPACING_FRACTIONAL_ODD: + spacing = TESS_FRACTIONAL_ODD; + break; + case TESS_SPACING_FRACTIONAL_EVEN: + spacing = TESS_FRACTIONAL_EVEN; + break; + case TESS_SPACING_UNSPECIFIED: + default: + unreachable("invalid tess spacing"); + } + tu_cs_emit(cs, A6XX_PC_TESS_CNTL_SPACING(spacing) | + A6XX_PC_TESS_CNTL_OUTPUT(output)); + + /* xxx: Misc tess unknowns: */ + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9103, 1); + tu_cs_emit(cs, 0x00ffff00); + + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_UNKNOWN_9106, 1); + tu_cs_emit(cs, 0x0000ffff); + + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_809D, 1); + tu_cs_emit(cs, 0x0); + + tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_UNKNOWN_8002, 1); + tu_cs_emit(cs, 0x0); + + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK, 1); + tu_cs_emit(cs, A6XX_VPC_PACK_POSITIONLOC(position_loc) | + A6XX_VPC_PACK_PSIZELOC(255) | + A6XX_VPC_PACK_STRIDE_IN_VPC(linkage.max_loc)); + + tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PACK_3, 1); + tu_cs_emit(cs, A6XX_VPC_PACK_3_POSITIONLOC(position_loc) | + A6XX_VPC_PACK_3_PSIZELOC(pointsize_loc) | + A6XX_VPC_PACK_3_STRIDE_IN_VPC(linkage.max_loc)); + + tu_cs_emit_pkt4(cs, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1); + tu_cs_emit(cs, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(linkage.cnt)); + + tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1); + tu_cs_emit(cs, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(linkage.max_loc) | + CONDREG(pointsize_regid, 0x100)); + + tu6_emit_link_map(cs, vs, hs, SB6_HS_SHADER); + tu6_emit_link_map(cs, hs, ds, SB6_DS_SHADER); + } + if (gs) { uint32_t vertices_out, invocations, output, vec4_size; /* this detects the tu_clear_blit path, which doesn't set ->nir */ if (gs->shader->nir) { - tu6_emit_link_map(cs, vs, gs); + if (hs) { + tu6_emit_link_map(cs, ds, gs, SB6_GS_SHADER); + } else { + tu6_emit_link_map(cs, vs, gs, SB6_GS_SHADER); + } vertices_out = gs->shader->nir->info.gs.vertices_out - 1; output = gl_primitive_to_tess(gs->shader->nir->info.gs.output_primitive); invocations = gs->shader->nir->info.gs.invocations - 1; @@ -1069,7 +1209,8 @@ static void tu6_emit_fs_outputs(struct tu_cs *cs, const struct ir3_shader_variant *fs, uint32_t mrt_count, bool dual_src_blend, - uint32_t render_components) + uint32_t render_components, + bool is_s8_uint) { uint32_t smask_regid, posz_regid; @@ -1115,7 +1256,7 @@ tu6_emit_fs_outputs(struct tu_cs *cs, enum a6xx_ztest_mode zmode; - if (fs->no_earlyz || fs->has_kill || fs->writes_pos) { + if (fs->no_earlyz || fs->has_kill || fs->writes_pos || is_s8_uint) { zmode = A6XX_LATE_Z; } else { zmode = A6XX_EARLY_Z; @@ -1129,35 +1270,76 @@ tu6_emit_fs_outputs(struct tu_cs *cs, } static void -tu6_emit_geometry_consts(struct tu_cs *cs, - const struct ir3_shader_variant *vs, - const struct ir3_shader_variant *gs) { - unsigned num_vertices = gs->shader->nir->info.gs.vertices_in; - - uint32_t params[4] = { - vs->output_size * num_vertices * 4, /* primitive stride */ - vs->output_size * 4, /* vertex stride */ +tu6_emit_geom_tess_consts(struct tu_cs *cs, + const struct ir3_shader_variant *vs, + const struct ir3_shader_variant *hs, + const struct ir3_shader_variant *ds, + const struct ir3_shader_variant *gs, + uint32_t cps_per_patch) +{ + uint32_t num_vertices = + hs ? cps_per_patch : gs->shader->nir->info.gs.vertices_in; + + uint32_t vs_params[4] = { + vs->output_size * num_vertices * 4, /* vs primitive stride */ + vs->output_size * 4, /* vs vertex stride */ 0, 0, }; uint32_t vs_base = ir3_const_state(vs)->offsets.primitive_param; tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, vs_base, SB6_VS_SHADER, 0, - ARRAY_SIZE(params), params); + ARRAY_SIZE(vs_params), vs_params); + + if (hs) { + assert(ds->type != MESA_SHADER_NONE); + uint32_t hs_params[4] = { + vs->output_size * num_vertices * 4, /* hs primitive stride */ + vs->output_size * 4, /* hs vertex stride */ + hs->output_size, + cps_per_patch, + }; + + uint32_t hs_base = hs->const_state->offsets.primitive_param; + tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, hs_base, SB6_HS_SHADER, 0, + ARRAY_SIZE(hs_params), hs_params); + if (gs) + num_vertices = gs->shader->nir->info.gs.vertices_in; + + uint32_t ds_params[4] = { + ds->output_size * num_vertices * 4, /* ds primitive stride */ + ds->output_size * 4, /* ds vertex stride */ + hs->output_size, /* hs vertex stride (dwords) */ + hs->shader->nir->info.tess.tcs_vertices_out + }; + + uint32_t ds_base = ds->const_state->offsets.primitive_param; + tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, ds_base, SB6_DS_SHADER, 0, + ARRAY_SIZE(ds_params), ds_params); + } - uint32_t gs_base = ir3_const_state(gs)->offsets.primitive_param; - tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0, - ARRAY_SIZE(params), params); + if (gs) { + const struct ir3_shader_variant *prev = ds ? ds : vs; + uint32_t gs_params[4] = { + prev->output_size * num_vertices * 4, /* gs primitive stride */ + prev->output_size * 4, /* gs vertex stride */ + 0, + 0, + }; + uint32_t gs_base = gs->const_state->offsets.primitive_param; + tu6_emit_const(cs, CP_LOAD_STATE6_GEOM, gs_base, SB6_GS_SHADER, 0, + ARRAY_SIZE(gs_params), gs_params); + } } static void tu6_emit_program(struct tu_cs *cs, struct tu_pipeline_builder *builder, - const struct tu_bo *binary_bo, - bool binning_pass, - struct tu_streamout_state *tf) + bool binning_pass) { const struct ir3_shader_variant *vs = builder->variants[MESA_SHADER_VERTEX]; const struct ir3_shader_variant *bs = builder->binning_variant; + const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL]; + const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL]; const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY]; const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT]; gl_shader_stage stage = MESA_SHADER_VERTEX; @@ -1172,8 +1354,7 @@ tu6_emit_program(struct tu_cs *cs, */ if (binning_pass && !gs) { vs = bs; - tu6_emit_xs_config(cs, stage, bs, - binary_bo->iova + builder->binning_vs_offset); + tu6_emit_xs_config(cs, stage, bs, builder->binning_vs_iova); stage++; } @@ -1183,32 +1364,36 @@ tu6_emit_program(struct tu_cs *cs, if (stage == MESA_SHADER_FRAGMENT && binning_pass) fs = xs = NULL; - tu6_emit_xs_config(cs, stage, xs, - binary_bo->iova + builder->shader_offsets[stage]); + tu6_emit_xs_config(cs, stage, xs, builder->shader_iova[stage]); } tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1); tu_cs_emit(cs, 0); - tu6_emit_vpc(cs, vs, gs, fs, tf); + tu6_emit_vpc(cs, vs, hs, ds, gs, fs); tu6_emit_vpc_varying_modes(cs, fs); if (fs) { tu6_emit_fs_inputs(cs, fs); tu6_emit_fs_outputs(cs, fs, builder->color_attachment_count, builder->use_dual_src_blend, - builder->render_components); + builder->render_components, + builder->depth_attachment_format == VK_FORMAT_S8_UINT); } else { /* TODO: check if these can be skipped if fs is disabled */ struct ir3_shader_variant dummy_variant = {}; tu6_emit_fs_inputs(cs, &dummy_variant); tu6_emit_fs_outputs(cs, &dummy_variant, builder->color_attachment_count, builder->use_dual_src_blend, - builder->render_components); + builder->render_components, + builder->depth_attachment_format == VK_FORMAT_S8_UINT); } - if (gs) - tu6_emit_geometry_consts(cs, vs, gs); + if (gs || hs) { + uint32_t cps_per_patch = builder->create_info->pTessellationState ? + builder->create_info->pTessellationState->patchControlPoints : 0; + tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch); + } } static void @@ -1219,6 +1404,7 @@ tu6_emit_vertex_input(struct tu_cs *cs, { uint32_t vfd_decode_idx = 0; uint32_t binding_instanced = 0; /* bitmask of instanced bindings */ + uint32_t step_rate[MAX_VBS]; for (uint32_t i = 0; i < info->vertexBindingDescriptionCount; i++) { const VkVertexInputBindingDescription *binding = @@ -1231,6 +1417,17 @@ tu6_emit_vertex_input(struct tu_cs *cs, binding_instanced |= 1 << binding->binding; *bindings_used |= 1 << binding->binding; + step_rate[binding->binding] = 1; + } + + const VkPipelineVertexInputDivisorStateCreateInfoEXT *div_state = + vk_find_struct_const(info->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT); + if (div_state) { + for (uint32_t i = 0; i < div_state->vertexBindingDivisorCount; i++) { + const VkVertexInputBindingDivisorDescriptionEXT *desc = + &div_state->pVertexBindingDivisors[i]; + step_rate[desc->binding] = desc->divisor; + } } /* TODO: emit all VFD_DECODE/VFD_DEST_CNTL in same (two) pkt4 */ @@ -1240,6 +1437,8 @@ tu6_emit_vertex_input(struct tu_cs *cs, &info->pVertexAttributeDescriptions[i]; uint32_t input_idx; + assert(*bindings_used & BIT(attr->binding)); + for (input_idx = 0; input_idx < vs->inputs_count; input_idx++) { if ((vs->inputs[input_idx].slot - VERT_ATTRIB_GENERIC0) == attr->location) break; @@ -1259,7 +1458,7 @@ tu6_emit_vertex_input(struct tu_cs *cs, .swap = format.swap, .unk30 = 1, ._float = !vk_format_is_int(attr->format)), - A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, 1)); + A6XX_VFD_DECODE_STEP_RATE(vfd_decode_idx, step_rate[attr->binding])); tu_cs_emit_regs(cs, A6XX_VFD_DEST_CNTL_INSTR(vfd_decode_idx, @@ -1351,17 +1550,30 @@ tu6_emit_viewport(struct tu_cs *cs, const VkViewport *viewport) void tu6_emit_scissor(struct tu_cs *cs, const VkRect2D *scissor) { - const VkOffset2D min = scissor->offset; - const VkOffset2D max = { + VkOffset2D min = scissor->offset; + VkOffset2D max = { scissor->offset.x + scissor->extent.width, scissor->offset.y + scissor->extent.height, }; - tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2); - tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(min.x) | - A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(min.y)); - tu_cs_emit(cs, A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(max.x - 1) | - A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(max.y - 1)); + /* special case for empty scissor with max == 0 to avoid overflow */ + if (max.x == 0) + min.x = max.x = 1; + if (max.y == 0) + min.y = max.y = 1; + + /* avoid overflow with large scissor + * note the max will be limited to min - 1, so that empty scissor works + */ + uint32_t scissor_max = BITFIELD_MASK(15); + min.x = MIN2(scissor_max, min.x); + min.y = MIN2(scissor_max, min.y); + max.x = MIN2(scissor_max, max.x); + max.y = MIN2(scissor_max, max.y); + + tu_cs_emit_regs(cs, + A6XX_GRAS_SC_SCREEN_SCISSOR_TL_0(.x = min.x, .y = min.y), + A6XX_GRAS_SC_SCREEN_SCISSOR_BR_0(.x = max.x - 1, .y = max.y - 1)); } void @@ -1447,14 +1659,12 @@ tu6_emit_depth_control(struct tu_cs *cs, const VkPipelineDepthStencilStateCreateInfo *ds_info, const VkPipelineRasterizationStateCreateInfo *rast_info) { - assert(!ds_info->depthBoundsTestEnable); - uint32_t rb_depth_cntl = 0; if (ds_info->depthTestEnable) { rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_ENABLE | A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) | - A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; + A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; /* TODO: don't set for ALWAYS/NEVER */ if (rast_info->depthClampEnable) rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE; @@ -1463,6 +1673,9 @@ tu6_emit_depth_control(struct tu_cs *cs, rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE; } + if (ds_info->depthBoundsTestEnable) + rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE | A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE; + tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_CNTL, 1); tu_cs_emit(cs, rb_depth_cntl); } @@ -1614,34 +1827,32 @@ tu6_emit_blend_control(struct tu_cs *cs, } static VkResult -tu_pipeline_create(struct tu_device *dev, - struct tu_pipeline_layout *layout, - bool compute, - const VkAllocationCallbacks *pAllocator, - struct tu_pipeline **out_pipeline) +tu_pipeline_allocate_cs(struct tu_device *dev, + struct tu_pipeline *pipeline, + struct tu_pipeline_builder *builder, + struct ir3_shader_variant *compute) { - struct tu_pipeline *pipeline = - vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8, - VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); - if (!pipeline) - return VK_ERROR_OUT_OF_HOST_MEMORY; + uint32_t size = 2048 + tu6_load_state_size(pipeline->layout, compute); + + /* graphics case: */ + if (builder) { + for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) { + if (builder->variants[i]) + size += builder->variants[i]->info.sizedwords; + } - tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, 2048); + size += builder->binning_variant->info.sizedwords; + } else { + size += compute->info.sizedwords; + } + + tu_cs_init(&pipeline->cs, dev, TU_CS_MODE_SUB_STREAM, size); /* Reserve the space now such that tu_cs_begin_sub_stream never fails. Note * that LOAD_STATE can potentially take up a large amount of space so we * calculate its size explicitly. */ - unsigned load_state_size = tu6_load_state_size(layout, compute); - VkResult result = tu_cs_reserve_space(&pipeline->cs, 2048 + load_state_size); - if (result != VK_SUCCESS) { - vk_free2(&dev->alloc, pAllocator, pipeline); - return result; - } - - *out_pipeline = pipeline; - - return VK_SUCCESS; + return tu_cs_reserve_space(&pipeline->cs, size); } static void @@ -1672,12 +1883,52 @@ tu_pipeline_shader_key_init(struct ir3_shader_key *key, if (msaa_info->sampleShadingEnable) key->sample_shading = true; - /* TODO: Populate the remaining fields of ir3_shader_key. */ + /* We set this after we compile to NIR because we need the prim mode */ + key->tessellation = IR3_TESS_NONE; +} + +static uint32_t +tu6_get_tessmode(struct tu_shader* shader) +{ + uint32_t primitive_mode = shader->ir3_shader->nir->info.tess.primitive_mode; + switch (primitive_mode) { + case GL_ISOLINES: + return IR3_TESS_ISOLINES; + case GL_TRIANGLES: + return IR3_TESS_TRIANGLES; + case GL_QUADS: + return IR3_TESS_QUADS; + case GL_NONE: + return IR3_TESS_NONE; + default: + unreachable("bad tessmode"); + } +} + +static uint64_t +tu_upload_variant(struct tu_pipeline *pipeline, + const struct ir3_shader_variant *variant) +{ + struct tu_cs_memory memory; + + if (!variant) + return 0; + + /* this expects to get enough alignment because shaders are allocated first + * and sizedwords is always aligned correctly + * note: an assert in tu6_emit_xs_config validates the alignment + */ + tu_cs_alloc(&pipeline->cs, variant->info.sizedwords, 1, &memory); + + memcpy(memory.map, variant->bin, sizeof(uint32_t) * variant->info.sizedwords); + return memory.iova; } static VkResult -tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder) +tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder, + struct tu_pipeline *pipeline) { + const struct ir3_compiler *compiler = builder->device->compiler; const VkPipelineShaderStageCreateInfo *stage_infos[MESA_SHADER_STAGES] = { NULL }; @@ -1702,11 +1953,21 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder) if (!shader) return VK_ERROR_OUT_OF_HOST_MEMORY; + /* In SPIR-V generated from GLSL, the primitive mode is specified in the + * tessellation evaluation shader, but in SPIR-V generated from HLSL, + * the mode is specified in the tessellation control shader. */ + if ((stage == MESA_SHADER_TESS_EVAL || stage == MESA_SHADER_TESS_CTRL) && + key.tessellation == IR3_TESS_NONE) { + key.tessellation = tu6_get_tessmode(shader); + } + builder->shaders[stage] = shader; } - for (gl_shader_stage stage = MESA_SHADER_STAGES - 1; - stage > MESA_SHADER_NONE; stage--) { + pipeline->tess.patch_type = key.tessellation; + + for (gl_shader_stage stage = MESA_SHADER_VERTEX; + stage < MESA_SHADER_STAGES; stage++) { if (!builder->shaders[stage]) continue; @@ -1716,10 +1977,25 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder) &key, false, &created); if (!builder->variants[stage]) return VK_ERROR_OUT_OF_HOST_MEMORY; + } - builder->shader_offsets[stage] = builder->shader_total_size; - builder->shader_total_size += - sizeof(uint32_t) * builder->variants[stage]->info.sizedwords; + uint32_t safe_constlens = ir3_trim_constlen(builder->variants, compiler); + + key.safe_constlen = true; + + for (gl_shader_stage stage = MESA_SHADER_VERTEX; + stage < MESA_SHADER_STAGES; stage++) { + if (!builder->shaders[stage]) + continue; + + if (safe_constlens & (1 << stage)) { + bool created; + builder->variants[stage] = + ir3_shader_get_variant(builder->shaders[stage]->ir3_shader, + &key, false, &created); + if (!builder->variants[stage]) + return VK_ERROR_OUT_OF_HOST_MEMORY; + } } const struct tu_shader *vs = builder->shaders[MESA_SHADER_VERTEX]; @@ -1729,48 +2005,37 @@ tu_pipeline_builder_compile_shaders(struct tu_pipeline_builder *builder) variant = builder->variants[MESA_SHADER_VERTEX]; } else { bool created; + key.safe_constlen = !!(safe_constlens & (1 << MESA_SHADER_VERTEX)); variant = ir3_shader_get_variant(vs->ir3_shader, &key, true, &created); if (!variant) return VK_ERROR_OUT_OF_HOST_MEMORY; } - builder->binning_vs_offset = builder->shader_total_size; - builder->shader_total_size += - sizeof(uint32_t) * variant->info.sizedwords; builder->binning_variant = variant; - return VK_SUCCESS; -} - -static VkResult -tu_pipeline_builder_upload_shaders(struct tu_pipeline_builder *builder, - struct tu_pipeline *pipeline) -{ - struct tu_bo *bo = &pipeline->program.binary_bo; - - VkResult result = - tu_bo_init_new(builder->device, bo, builder->shader_total_size); - if (result != VK_SUCCESS) - return result; - - result = tu_bo_map(builder->device, bo); - if (result != VK_SUCCESS) - return result; - - for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) { - const struct ir3_shader_variant *variant = builder->variants[i]; - if (!variant) - continue; - - memcpy(bo->map + builder->shader_offsets[i], variant->bin, - sizeof(uint32_t) * variant->info.sizedwords); - } - - if (builder->binning_variant) { - const struct ir3_shader_variant *variant = builder->binning_variant; - memcpy(bo->map + builder->binning_vs_offset, variant->bin, - sizeof(uint32_t) * variant->info.sizedwords); + if (builder->shaders[MESA_SHADER_TESS_CTRL]) { + struct ir3_shader *hs = + builder->shaders[MESA_SHADER_TESS_CTRL]->ir3_shader; + assert(hs->type != MESA_SHADER_NONE); + + /* Calculate and store the per-vertex and per-patch HS-output sizes. */ + uint32_t per_vertex_output_size = 0; + uint32_t per_patch_output_size = 0; + nir_foreach_variable (output, &hs->nir->outputs) { + switch (output->data.location) { + case VARYING_SLOT_TESS_LEVEL_OUTER: + case VARYING_SLOT_TESS_LEVEL_INNER: + continue; + } + uint32_t size = glsl_count_attribute_slots(output->type, false) * 4; + if (output->data.patch) + per_patch_output_size += size; + else + per_vertex_output_size += size; + } + pipeline->tess.per_vertex_output_size = per_vertex_output_size; + pipeline->tess.per_patch_output_size = per_patch_output_size; } return VK_SUCCESS; @@ -1818,11 +2083,11 @@ tu_pipeline_builder_parse_shader_stages(struct tu_pipeline_builder *builder, { struct tu_cs prog_cs; tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs); - tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, false, &pipeline->streamout); + tu6_emit_program(&prog_cs, builder, false); pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs); tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs); - tu6_emit_program(&prog_cs, builder, &pipeline->program.binary_bo, true, &pipeline->streamout); + tu6_emit_program(&prog_cs, builder, true); pipeline->program.binning_state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs); VkShaderStageFlags stages = 0; @@ -1885,7 +2150,7 @@ static bool tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs, uint32_t id, uint32_t size) { - struct ts_cs_memory memory; + struct tu_cs_memory memory; if (pipeline->dynamic_state_mask & BIT(id)) return false; @@ -1902,6 +2167,29 @@ tu_pipeline_static_state(struct tu_pipeline *pipeline, struct tu_cs *cs, return true; } +static void +tu_pipeline_builder_parse_tessellation(struct tu_pipeline_builder *builder, + struct tu_pipeline *pipeline) +{ + const VkPipelineTessellationStateCreateInfo *tess_info = + builder->create_info->pTessellationState; + + if (!tess_info) + return; + + assert(pipeline->ia.primtype == DI_PT_PATCHES0); + assert(tess_info->patchControlPoints <= 32); + pipeline->ia.primtype += tess_info->patchControlPoints; + const VkPipelineTessellationDomainOriginStateCreateInfo *domain_info = + vk_find_struct_const(tess_info->pNext, PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO); + pipeline->tess.upper_left_domain_origin = !domain_info || + domain_info->domainOrigin == VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT; + const struct ir3_shader_variant *hs = builder->variants[MESA_SHADER_TESS_CTRL]; + const struct ir3_shader_variant *ds = builder->variants[MESA_SHADER_TESS_EVAL]; + pipeline->tess.hs_bo_regid = hs->const_state->offsets.primitive_param + 1; + pipeline->tess.ds_bo_regid = ds->const_state->offsets.primitive_param + 1; +} + static void tu_pipeline_builder_parse_viewport(struct tu_pipeline_builder *builder, struct tu_pipeline *pipeline) @@ -1936,10 +2224,10 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, const VkPipelineRasterizationStateCreateInfo *rast_info = builder->create_info->pRasterizationState; - assert(rast_info->polygonMode == VK_POLYGON_MODE_FILL); + enum a6xx_polygon_mode mode = tu6_polygon_mode(rast_info->polygonMode); struct tu_cs cs; - tu_cs_begin_sub_stream(&pipeline->cs, 7, &cs); + tu_cs_begin_sub_stream(&pipeline->cs, 11, &cs); tu_cs_emit_regs(&cs, A6XX_GRAS_CL_CNTL( @@ -1948,6 +2236,13 @@ tu_pipeline_builder_parse_rasterization(struct tu_pipeline_builder *builder, .unk5 = rast_info->depthClampEnable, .zero_gb_scale_z = 1, .vp_clip_code_ignore = 1)); + + tu_cs_emit_regs(&cs, + A6XX_VPC_POLYGON_MODE(.mode = mode)); + + tu_cs_emit_regs(&cs, + A6XX_PC_POLYGON_MODE(.mode = mode)); + /* move to hw ctx init? */ tu_cs_emit_regs(&cs, A6XX_GRAS_UNKNOWN_8001()); tu_cs_emit_regs(&cs, @@ -2009,6 +2304,12 @@ tu_pipeline_builder_parse_depth_stencil(struct tu_pipeline_builder *builder, pipeline->ds.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &cs); + if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_DEPTH_BOUNDS, 3)) { + tu_cs_emit_regs(&cs, + A6XX_RB_Z_BOUNDS_MIN(ds_info->minDepthBounds), + A6XX_RB_Z_BOUNDS_MAX(ds_info->maxDepthBounds)); + } + if (tu_pipeline_static_state(pipeline, &cs, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK, 2)) { tu_cs_emit_regs(&cs, A6XX_RB_STENCILMASK(.mask = ds_info->front.compareMask & 0xff, .bfmask = ds_info->back.compareMask & 0xff)); @@ -2092,38 +2393,46 @@ tu_pipeline_finish(struct tu_pipeline *pipeline, const VkAllocationCallbacks *alloc) { tu_cs_finish(&pipeline->cs); - - if (pipeline->program.binary_bo.gem_handle) - tu_bo_finish(dev, &pipeline->program.binary_bo); } static VkResult tu_pipeline_builder_build(struct tu_pipeline_builder *builder, struct tu_pipeline **pipeline) { - VkResult result = tu_pipeline_create(builder->device, builder->layout, - false, builder->alloc, pipeline); - if (result != VK_SUCCESS) - return result; + VkResult result; + + *pipeline = + vk_zalloc2(&builder->device->alloc, builder->alloc, sizeof(**pipeline), + 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); + if (!*pipeline) + return VK_ERROR_OUT_OF_HOST_MEMORY; (*pipeline)->layout = builder->layout; /* compile and upload shaders */ - result = tu_pipeline_builder_compile_shaders(builder); - if (result == VK_SUCCESS) - result = tu_pipeline_builder_upload_shaders(builder, *pipeline); + result = tu_pipeline_builder_compile_shaders(builder, *pipeline); if (result != VK_SUCCESS) { - tu_pipeline_finish(*pipeline, builder->device, builder->alloc); vk_free2(&builder->device->alloc, builder->alloc, *pipeline); - *pipeline = VK_NULL_HANDLE; + return result; + } + result = tu_pipeline_allocate_cs(builder->device, *pipeline, builder, NULL); + if (result != VK_SUCCESS) { + vk_free2(&builder->device->alloc, builder->alloc, *pipeline); return result; } + for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) + builder->shader_iova[i] = tu_upload_variant(*pipeline, builder->variants[i]); + + builder->binning_vs_iova = + tu_upload_variant(*pipeline, builder->binning_variant); + tu_pipeline_builder_parse_dynamic(builder, *pipeline); tu_pipeline_builder_parse_shader_stages(builder, *pipeline); tu_pipeline_builder_parse_vertex_input(builder, *pipeline); tu_pipeline_builder_parse_input_assembly(builder, *pipeline); + tu_pipeline_builder_parse_tessellation(builder, *pipeline); tu_pipeline_builder_parse_viewport(builder, *pipeline); tu_pipeline_builder_parse_rasterization(builder, *pipeline); tu_pipeline_builder_parse_depth_stencil(builder, *pipeline); @@ -2255,30 +2564,6 @@ tu_CreateGraphicsPipelines(VkDevice device, return final_result; } -static VkResult -tu_compute_upload_shader(VkDevice device, - struct tu_pipeline *pipeline, - struct ir3_shader_variant *v) -{ - TU_FROM_HANDLE(tu_device, dev, device); - struct tu_bo *bo = &pipeline->program.binary_bo; - - uint32_t shader_size = sizeof(uint32_t) * v->info.sizedwords; - VkResult result = - tu_bo_init_new(dev, bo, shader_size); - if (result != VK_SUCCESS) - return result; - - result = tu_bo_map(dev, bo); - if (result != VK_SUCCESS) - return result; - - memcpy(bo->map, v->bin, shader_size); - - return VK_SUCCESS; -} - - static VkResult tu_compute_pipeline_create(VkDevice device, VkPipelineCache _cache, @@ -2295,9 +2580,11 @@ tu_compute_pipeline_create(VkDevice device, *pPipeline = VK_NULL_HANDLE; - result = tu_pipeline_create(dev, layout, true, pAllocator, &pipeline); - if (result != VK_SUCCESS) - return result; + pipeline = + vk_zalloc2(&dev->alloc, pAllocator, sizeof(*pipeline), 8, + VK_SYSTEM_ALLOCATION_SCOPE_OBJECT); + if (!pipeline) + return VK_ERROR_OUT_OF_HOST_MEMORY; pipeline->layout = layout; @@ -2313,22 +2600,26 @@ tu_compute_pipeline_create(VkDevice device, bool created; struct ir3_shader_variant *v = ir3_shader_get_variant(shader->ir3_shader, &key, false, &created); - if (!v) + if (!v) { + result = VK_ERROR_OUT_OF_HOST_MEMORY; goto fail; + } tu_pipeline_set_linkage(&pipeline->program.link[MESA_SHADER_COMPUTE], shader, v); - result = tu_compute_upload_shader(device, pipeline, v); + result = tu_pipeline_allocate_cs(dev, pipeline, NULL, v); if (result != VK_SUCCESS) goto fail; + uint64_t shader_iova = tu_upload_variant(pipeline, v); + for (int i = 0; i < 3; i++) pipeline->compute.local_size[i] = v->shader->nir->info.cs.local_size[i]; struct tu_cs prog_cs; tu_cs_begin_sub_stream(&pipeline->cs, 512, &prog_cs); - tu6_emit_cs_config(&prog_cs, shader, v, pipeline->program.binary_bo.iova); + tu6_emit_cs_config(&prog_cs, shader, v, shader_iova); pipeline->program.state_ib = tu_cs_end_sub_stream(&pipeline->cs, &prog_cs); tu6_emit_load_state(pipeline, true); @@ -2340,7 +2631,6 @@ fail: if (shader) tu_shader_destroy(dev, shader, pAllocator); - tu_pipeline_finish(pipeline, dev, pAllocator); vk_free2(&dev->alloc, pAllocator, pipeline); return result;