X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Ffreedreno%2Fvulkan%2Ftu_private.h;h=40c2fb092a3f1cd9e36742c2565a920c4446d026;hb=59e5f95bdccf70219dd67adabd8b7f09b62710bf;hp=ab7cdc65491ee87ffd681542c1306c529e1a2949;hpb=8cb226b2588edbe67488d23a3425a78e78152004;p=mesa.git diff --git a/src/freedreno/vulkan/tu_private.h b/src/freedreno/vulkan/tu_private.h index ab7cdc65491..40c2fb092a3 100644 --- a/src/freedreno/vulkan/tu_private.h +++ b/src/freedreno/vulkan/tu_private.h @@ -47,7 +47,9 @@ #include "main/macros.h" #include "util/list.h" #include "util/macros.h" +#include "util/u_atomic.h" #include "vk_alloc.h" +#include "vk_object.h" #include "vk_debug_report.h" #include "wsi_common.h" @@ -188,7 +190,7 @@ tu_lookup_entrypoint_checked( struct tu_physical_device { - VK_LOADER_DATA _loader_data; + struct vk_object_base base; struct tu_instance *instance; @@ -220,6 +222,11 @@ struct tu_physical_device uint32_t SP_UNKNOWN_A0F8; } magic; + int msm_major_version; + int msm_minor_version; + + bool limited_z24s8; + /* This is the drivers on-disk cache used as a fallback as opposed to * the pipeline cache defined by apps. */ @@ -241,7 +248,7 @@ enum tu_debug_flags struct tu_instance { - VK_LOADER_DATA _loader_data; + struct vk_object_base base; VkAllocationCallbacks alloc; @@ -273,6 +280,8 @@ struct cache_entry; struct tu_pipeline_cache { + struct vk_object_base base; + struct tu_device *device; pthread_mutex_t mutex; @@ -297,6 +306,7 @@ struct tu_pipeline_key struct tu_fence { + struct vk_object_base base; struct wsi_fence *fence_wsi; bool signaled; int fd; @@ -317,7 +327,8 @@ tu_fence_wait_idle(struct tu_fence *fence); struct tu_queue { - VK_LOADER_DATA _loader_data; + struct vk_object_base base; + struct tu_device *device; uint32_t queue_family_index; int queue_idx; @@ -335,29 +346,61 @@ struct tu_bo void *map; }; -struct tu_device +enum global_shader { + GLOBAL_SH_VS, + GLOBAL_SH_FS_BLIT, + GLOBAL_SH_FS_CLEAR0, + GLOBAL_SH_FS_CLEAR_MAX = GLOBAL_SH_FS_CLEAR0 + MAX_RTS, + GLOBAL_SH_COUNT, +}; + +/* This struct defines the layout of the global_bo */ +struct tu6_global { - VK_LOADER_DATA _loader_data; + /* 6 bcolor_entry entries, one for each VK_BORDER_COLOR */ + uint8_t border_color[128 * 6]; - VkAllocationCallbacks alloc; + /* clear/blit shaders, all <= 16 instrs (16 instr = 1 instrlen unit) */ + instr_t shaders[GLOBAL_SH_COUNT][16]; + + uint32_t seqno_dummy; /* dummy seqno for CP_EVENT_WRITE */ + uint32_t _pad0; + volatile uint32_t vsc_draw_overflow; + uint32_t _pad1; + volatile uint32_t vsc_prim_overflow; + uint32_t _pad2; + uint64_t predicate; + + /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */ + struct { + uint32_t offset; + uint32_t pad[7]; + } flush_base[4]; +}; +#define gb_offset(member) offsetof(struct tu6_global, member) +#define global_iova(cmd, member) ((cmd)->device->global_bo.iova + gb_offset(member)) +void tu_init_clear_blit_shaders(struct tu6_global *global); + +/* extra space in vsc draw/prim streams */ +#define VSC_PAD 0x40 + +struct tu_device +{ + struct vk_device vk; struct tu_instance *instance; struct tu_queue *queues[TU_MAX_QUEUE_FAMILIES]; int queue_count[TU_MAX_QUEUE_FAMILIES]; struct tu_physical_device *physical_device; + int _lost; struct ir3_compiler *compiler; /* Backup in-memory cache to be used if the app doesn't provide one */ struct tu_pipeline_cache *mem_cache; - struct tu_bo vsc_draw_strm; - struct tu_bo vsc_prim_strm; - uint32_t vsc_draw_strm_pitch; - uint32_t vsc_prim_strm_pitch; - #define MIN_SCRATCH_BO_SIZE_LOG2 12 /* A page */ /* Currently the kernel driver uses a 32-bit GPU address space, but it @@ -369,11 +412,27 @@ struct tu_device bool initialized; } scratch_bos[48 - MIN_SCRATCH_BO_SIZE_LOG2]; - struct tu_bo border_color; + struct tu_bo global_bo; struct tu_device_extension_table enabled_extensions; + + uint32_t vsc_draw_strm_pitch; + uint32_t vsc_prim_strm_pitch; + mtx_t vsc_pitch_mtx; }; +VkResult _tu_device_set_lost(struct tu_device *device, + const char *file, int line, + const char *msg, ...) PRINTFLIKE(4, 5); +#define tu_device_set_lost(dev, ...) \ + _tu_device_set_lost(dev, __FILE__, __LINE__, __VA_ARGS__) + +static inline bool +tu_device_is_lost(struct tu_device *device) +{ + return unlikely(p_atomic_read(&device->_lost)); +} + VkResult tu_bo_init_new(struct tu_device *dev, struct tu_bo *bo, uint64_t size); VkResult @@ -406,7 +465,7 @@ struct tu_cs_entry uint32_t offset; }; -struct ts_cs_memory { +struct tu_cs_memory { uint32_t *map; uint64_t iova; }; @@ -435,6 +494,8 @@ enum tu_draw_state_group_id TU_DRAW_STATE_DS, TU_DRAW_STATE_BLEND, TU_DRAW_STATE_VS_CONST, + TU_DRAW_STATE_HS_CONST, + TU_DRAW_STATE_DS_CONST, TU_DRAW_STATE_GS_CONST, TU_DRAW_STATE_FS_CONST, TU_DRAW_STATE_DESC_SETS, @@ -507,6 +568,8 @@ struct tu_cs struct tu_device_memory { + struct vk_object_base base; + struct tu_bo bo; VkDeviceSize size; @@ -527,6 +590,8 @@ struct tu_descriptor_range struct tu_descriptor_set { + struct vk_object_base base; + const struct tu_descriptor_set_layout *layout; struct tu_descriptor_pool *pool; uint32_t size; @@ -554,6 +619,8 @@ struct tu_descriptor_pool_entry struct tu_descriptor_pool { + struct vk_object_base base; + struct tu_bo bo; uint64_t current_offset; uint64_t size; @@ -596,12 +663,16 @@ struct tu_descriptor_update_template_entry struct tu_descriptor_update_template { + struct vk_object_base base; + uint32_t entry_count; struct tu_descriptor_update_template_entry entry[0]; }; struct tu_buffer { + struct vk_object_base base; + VkDeviceSize size; VkBufferUsageFlags usage; @@ -635,56 +706,16 @@ struct tu_descriptor_state uint32_t dynamic_descriptors[MAX_DYNAMIC_BUFFERS * A6XX_TEX_CONST_DWORDS]; }; -struct tu_tile -{ - uint8_t pipe; - uint8_t slot; - VkOffset2D begin; - VkOffset2D end; -}; - -struct tu_tiling_config -{ - VkRect2D render_area; - - /* position and size of the first tile */ - VkRect2D tile0; - /* number of tiles */ - VkExtent2D tile_count; - - /* size of the first VSC pipe */ - VkExtent2D pipe0; - /* number of VSC pipes */ - VkExtent2D pipe_count; - - /* pipe register values */ - uint32_t pipe_config[MAX_VSC_PIPES]; - uint32_t pipe_sizes[MAX_VSC_PIPES]; - - /* Whether sysmem rendering must be used */ - bool force_sysmem; -}; - enum tu_cmd_dirty_bits { - TU_CMD_DIRTY_COMPUTE_PIPELINE = 1 << 1, TU_CMD_DIRTY_VERTEX_BUFFERS = 1 << 2, - TU_CMD_DIRTY_DESCRIPTOR_SETS = 1 << 3, - TU_CMD_DIRTY_COMPUTE_DESCRIPTOR_SETS = 1 << 4, + TU_CMD_DIRTY_DESC_SETS_LOAD = 1 << 3, + TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD = 1 << 4, TU_CMD_DIRTY_SHADER_CONSTS = 1 << 5, - TU_CMD_DIRTY_STREAMOUT_BUFFERS = 1 << 6, /* all draw states were disabled and need to be re-enabled: */ TU_CMD_DIRTY_DRAW_STATE = 1 << 7, }; -struct tu_streamout_state { - uint16_t stride[IR3_MAX_SO_BUFFERS]; - uint32_t ncomp[IR3_MAX_SO_BUFFERS]; - uint32_t prog[IR3_MAX_SO_OUTPUTS * 2]; - uint32_t prog_count; - uint32_t vpc_so_buf_cntl; -}; - /* There are only three cache domains we have to care about: the CCU, or * color cache unit, which is used for color and depth/stencil attachments * and copy/blit destinations, and is split conceptually into color and depth, @@ -724,13 +755,34 @@ enum tu_cmd_access_mask { TU_ACCESS_CCU_DEPTH_INCOHERENT_READ = 1 << 8, TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE = 1 << 9, - TU_ACCESS_SYSMEM_READ = 1 << 10, - TU_ACCESS_SYSMEM_WRITE = 1 << 11, + /* Accesses by the host */ + TU_ACCESS_HOST_READ = 1 << 10, + TU_ACCESS_HOST_WRITE = 1 << 11, + + /* Accesses by a GPU engine which bypasses any cache. e.g. writes via + * CP_EVENT_WRITE::BLIT and the CP are SYSMEM_WRITE. + */ + TU_ACCESS_SYSMEM_READ = 1 << 12, + TU_ACCESS_SYSMEM_WRITE = 1 << 13, + + /* Set if a WFI is required. This can be required for: + * - 2D engine which (on some models) doesn't wait for flushes to complete + * before starting + * - CP draw indirect opcodes, where we need to wait for any flushes to + * complete but the CP implicitly waits for WFI's to complete and + * therefore we only need a WFI after the flushes. + */ + TU_ACCESS_WFI_READ = 1 << 14, + + /* Set if a CP_WAIT_FOR_ME is required due to the data being read by the CP + * without it waiting for any WFI. + */ + TU_ACCESS_WFM_READ = 1 << 15, - /* Set if a WFI is required due to data being read by the CP or the 2D - * engine. + /* Memory writes from the CP start in-order with draws and event writes, + * but execute asynchronously and hence need a CP_WAIT_MEM_WRITES if read. */ - TU_ACCESS_WFI_READ = 1 << 12, + TU_ACCESS_CP_WRITE = 1 << 16, TU_ACCESS_READ = TU_ACCESS_UCHE_READ | @@ -738,7 +790,10 @@ enum tu_cmd_access_mask { TU_ACCESS_CCU_DEPTH_READ | TU_ACCESS_CCU_COLOR_INCOHERENT_READ | TU_ACCESS_CCU_DEPTH_INCOHERENT_READ | - TU_ACCESS_SYSMEM_READ, + TU_ACCESS_HOST_READ | + TU_ACCESS_SYSMEM_READ | + TU_ACCESS_WFI_READ | + TU_ACCESS_WFM_READ, TU_ACCESS_WRITE = TU_ACCESS_UCHE_WRITE | @@ -746,7 +801,9 @@ enum tu_cmd_access_mask { TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE | TU_ACCESS_CCU_DEPTH_WRITE | TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE | - TU_ACCESS_SYSMEM_WRITE, + TU_ACCESS_HOST_WRITE | + TU_ACCESS_SYSMEM_WRITE | + TU_ACCESS_CP_WRITE, TU_ACCESS_ALL = TU_ACCESS_READ | @@ -760,18 +817,31 @@ enum tu_cmd_flush_bits { TU_CMD_FLAG_CCU_INVALIDATE_COLOR = 1 << 3, TU_CMD_FLAG_CACHE_FLUSH = 1 << 4, TU_CMD_FLAG_CACHE_INVALIDATE = 1 << 5, + TU_CMD_FLAG_WAIT_MEM_WRITES = 1 << 6, + TU_CMD_FLAG_WAIT_FOR_IDLE = 1 << 7, + TU_CMD_FLAG_WAIT_FOR_ME = 1 << 8, TU_CMD_FLAG_ALL_FLUSH = TU_CMD_FLAG_CCU_FLUSH_DEPTH | TU_CMD_FLAG_CCU_FLUSH_COLOR | - TU_CMD_FLAG_CACHE_FLUSH, + TU_CMD_FLAG_CACHE_FLUSH | + /* Treat the CP as a sort of "cache" which may need to be "flushed" via + * waiting for writes to land with WAIT_FOR_MEM_WRITES. + */ + TU_CMD_FLAG_WAIT_MEM_WRITES, - TU_CMD_FLAG_ALL_INVALIDATE = + TU_CMD_FLAG_GPU_INVALIDATE = TU_CMD_FLAG_CCU_INVALIDATE_DEPTH | TU_CMD_FLAG_CCU_INVALIDATE_COLOR | TU_CMD_FLAG_CACHE_INVALIDATE, - TU_CMD_FLAG_WFI = 1 << 6, + TU_CMD_FLAG_ALL_INVALIDATE = + TU_CMD_FLAG_GPU_INVALIDATE | + /* Treat the CP as a sort of "cache" which may need to be "invalidated" + * via waiting for UCHE/CCU flushes to land with WFI/WFM. + */ + TU_CMD_FLAG_WAIT_FOR_IDLE | + TU_CMD_FLAG_WAIT_FOR_ME, }; /* Changing the CCU from sysmem mode to gmem mode or vice-versa is pretty @@ -817,28 +887,22 @@ struct tu_cmd_state /* saved states to re-emit in TU_CMD_DIRTY_DRAW_STATE case */ struct tu_draw_state dynamic_state[TU_DYNAMIC_STATE_COUNT]; - struct tu_cs_entry vertex_buffers_ib; - struct tu_cs_entry shader_const_ib[MESA_SHADER_STAGES]; - struct tu_cs_entry desc_sets_ib, desc_sets_load_ib; - struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib; + struct tu_draw_state vertex_buffers; + struct tu_draw_state shader_const[MESA_SHADER_STAGES]; + struct tu_draw_state desc_sets; - /* Stream output buffers */ - struct - { - struct tu_buffer *buffers[IR3_MAX_SO_BUFFERS]; - VkDeviceSize offsets[IR3_MAX_SO_BUFFERS]; - VkDeviceSize sizes[IR3_MAX_SO_BUFFERS]; - } streamout_buf; - - uint8_t streamout_reset; - uint8_t streamout_enabled; + struct tu_draw_state vs_params; /* Index buffer */ - struct tu_buffer *index_buffer; - uint64_t index_offset; - uint32_t index_type; - uint32_t max_index_count; uint64_t index_va; + uint32_t max_index_count; + uint8_t index_size; + + /* because streamout base has to be 32-byte aligned + * there is an extra offset to deal with when it is + * unaligned + */ + uint8_t streamout_offset[IR3_MAX_SO_BUFFERS]; /* Renderpasses are tricky, because we may need to flush differently if * using sysmem vs. gmem and therefore we have to delay any flushing that @@ -854,14 +918,20 @@ struct tu_cmd_state const struct tu_render_pass *pass; const struct tu_subpass *subpass; const struct tu_framebuffer *framebuffer; - - struct tu_tiling_config tiling_config; + VkRect2D render_area; struct tu_cs_entry tile_store_ib; + + bool xfb_used; + bool has_tess; + bool has_subpass_predication; + bool predication_active; }; struct tu_cmd_pool { + struct vk_object_base base; + VkAllocationCallbacks alloc; struct list_head cmd_buffers; struct list_head free_cmd_buffers; @@ -907,31 +977,9 @@ tu_bo_list_add(struct tu_bo_list *list, VkResult tu_bo_list_merge(struct tu_bo_list *list, const struct tu_bo_list *other); -/* This struct defines the layout of the scratch_bo */ -struct tu6_control -{ - uint32_t seqno_dummy; /* dummy seqno for CP_EVENT_WRITE */ - uint32_t _pad0; - volatile uint32_t vsc_overflow; - uint32_t _pad1; - /* flag set from cmdstream when VSC overflow detected: */ - uint32_t vsc_scratch; - uint32_t _pad2; - uint32_t _pad3; - uint32_t _pad4; - - /* scratch space for VPC_SO[i].FLUSH_BASE_LO/HI, start on 32 byte boundary. */ - struct { - uint32_t offset; - uint32_t pad[7]; - } flush_base[4]; -}; - -#define ctrl_offset(member) offsetof(struct tu6_control, member) - struct tu_cmd_buffer { - VK_LOADER_DATA _loader_data; + struct vk_object_base base; struct tu_device *device; @@ -963,13 +1011,8 @@ struct tu_cmd_buffer struct tu_cs draw_epilogue_cs; struct tu_cs sub_cs; - struct tu_bo scratch_bo; - - struct tu_bo vsc_draw_strm; - struct tu_bo vsc_prim_strm; uint32_t vsc_draw_strm_pitch; uint32_t vsc_prim_strm_pitch; - bool use_vsc_data; }; /* Temporary struct for tracking a register state to be written, used by @@ -1007,11 +1050,14 @@ tu_get_descriptors_state(struct tu_cmd_buffer *cmd_buffer, struct tu_event { + struct vk_object_base base; struct tu_bo bo; }; struct tu_shader_module { + struct vk_object_base base; + unsigned char sha1[20]; uint32_t code_size; @@ -1055,6 +1101,8 @@ struct tu_program_descriptor_linkage struct tu_pipeline { + struct vk_object_base base; + struct tu_cs cs; struct tu_pipeline_layout *layout; @@ -1063,8 +1111,6 @@ struct tu_pipeline VkShaderStageFlags active_stages; uint32_t active_desc_sets; - struct tu_streamout_state streamout; - /* mask of enabled dynamic states * if BIT(i) is set, pipeline->dynamic_state[i] is *NOT* used */ @@ -1074,24 +1120,21 @@ struct tu_pipeline /* gras_su_cntl without line width, used for dynamic line width state */ uint32_t gras_su_cntl; + /* draw states for the pipeline */ + struct tu_draw_state load_state, rast_state, ds_state, blend_state; + struct { - struct tu_bo binary_bo; - struct tu_cs_entry state_ib; - struct tu_cs_entry binning_state_ib; + struct tu_draw_state state; + struct tu_draw_state binning_state; struct tu_program_descriptor_linkage link[MESA_SHADER_STAGES]; } program; struct { - struct tu_cs_entry state_ib; - } load_state; - - struct - { - struct tu_cs_entry state_ib; - struct tu_cs_entry binning_state_ib; + struct tu_draw_state state; + struct tu_draw_state binning_state; uint32_t bindings_used; } vi; @@ -1104,27 +1147,12 @@ struct tu_pipeline struct { uint32_t patch_type; - uint32_t per_vertex_output_size; - uint32_t per_patch_output_size; + uint32_t param_stride; uint32_t hs_bo_regid; uint32_t ds_bo_regid; + bool upper_left_domain_origin; } tess; - struct - { - struct tu_cs_entry state_ib; - } rast; - - struct - { - struct tu_cs_entry state_ib; - } ds; - - struct - { - struct tu_cs_entry state_ib; - } blend; - struct { uint32_t local_size[3]; @@ -1165,7 +1193,8 @@ tu6_emit_vpc(struct tu_cs *cs, const struct ir3_shader_variant *ds, const struct ir3_shader_variant *gs, const struct ir3_shader_variant *fs, - struct tu_streamout_state *tf); + uint32_t patch_control_points, + bool vshs_workgroup); void tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs); @@ -1236,6 +1265,8 @@ tu6_base_format(VkFormat format) struct tu_image { + struct vk_object_base base; + VkImageType type; /* The original VkFormat provided by the client. This may not match any * of the actual surface formats. @@ -1250,7 +1281,8 @@ struct tu_image uint32_t layer_count; VkSampleCountFlagBits samples; - struct fdl_layout layout; + struct fdl_layout layout[3]; + uint32_t total_size; unsigned queue_family_mask; bool exclusive; @@ -1284,6 +1316,8 @@ tu_get_levelCount(const struct tu_image *image, struct tu_image_view { + struct vk_object_base base; + struct tu_image *image; /**< VkImageViewCreateInfo::image */ uint64_t base_addr; @@ -1317,9 +1351,16 @@ struct tu_image_view uint32_t RB_2D_DST_INFO; uint32_t RB_BLIT_DST_INFO; + + /* for d32s8 separate stencil */ + uint64_t stencil_base_addr; + uint32_t stencil_layer_size; + uint32_t stencil_PITCH; }; struct tu_sampler_ycbcr_conversion { + struct vk_object_base base; + VkFormat format; VkSamplerYcbcrModelConversion ycbcr_model; VkSamplerYcbcrRange ycbcr_range; @@ -1329,6 +1370,8 @@ struct tu_sampler_ycbcr_conversion { }; struct tu_sampler { + struct vk_object_base base; + uint32_t descriptor[A6XX_TEX_SAMP_DWORDS]; struct tu_sampler_ycbcr_conversion *ycbcr_sampler; }; @@ -1342,6 +1385,12 @@ tu_cs_image_ref_2d(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t void tu_cs_image_flag_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer); +void +tu_cs_image_stencil_ref(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer); + +#define tu_image_view_stencil(iview, x) \ + ((iview->x & ~A6XX_##x##_COLOR_FORMAT__MASK) | A6XX_##x##_COLOR_FORMAT(FMT6_8_UINT)) + VkResult tu_image_create(VkDevice _device, const VkImageCreateInfo *pCreateInfo, @@ -1358,11 +1407,14 @@ tu_image_from_gralloc(VkDevice device_h, VkImage *out_image_h); void -tu_image_view_init(struct tu_image_view *view, - const VkImageViewCreateInfo *pCreateInfo); +tu_image_view_init(struct tu_image_view *iview, + const VkImageViewCreateInfo *pCreateInfo, + bool limited_z24s8); struct tu_buffer_view { + struct vk_object_base base; + uint32_t descriptor[A6XX_TEX_CONST_DWORDS]; struct tu_buffer *buffer; @@ -1379,14 +1431,35 @@ struct tu_attachment_info struct tu_framebuffer { + struct vk_object_base base; + uint32_t width; uint32_t height; uint32_t layers; + /* size of the first tile */ + VkExtent2D tile0; + /* number of tiles */ + VkExtent2D tile_count; + + /* size of the first VSC pipe */ + VkExtent2D pipe0; + /* number of VSC pipes */ + VkExtent2D pipe_count; + + /* pipe register values */ + uint32_t pipe_config[MAX_VSC_PIPES]; + uint32_t pipe_sizes[MAX_VSC_PIPES]; + uint32_t attachment_count; struct tu_attachment_info attachments[0]; }; +void +tu_framebuffer_tiling_config(struct tu_framebuffer *fb, + const struct tu_device *device, + const struct tu_render_pass *pass); + struct tu_subpass_barrier { VkPipelineStageFlags src_stage_mask; VkAccessFlags src_access_mask; @@ -1397,7 +1470,6 @@ struct tu_subpass_barrier { struct tu_subpass_attachment { uint32_t attachment; - VkImageLayout layout; }; struct tu_subpass @@ -1410,7 +1482,6 @@ struct tu_subpass struct tu_subpass_attachment depth_stencil_attachment; VkSampleCountFlagBits samples; - bool has_external_src, has_external_dst; uint32_t srgb_cntl; @@ -1425,12 +1496,17 @@ struct tu_render_pass_attachment VkImageAspectFlags clear_mask; bool load; bool store; - VkImageLayout initial_layout, final_layout; int32_t gmem_offset; + /* for D32S8 separate stencil: */ + bool load_stencil; + bool store_stencil; + int32_t gmem_offset_stencil; }; struct tu_render_pass { + struct vk_object_base base; + uint32_t attachment_count; uint32_t subpass_count; uint32_t gmem_pixels; @@ -1443,6 +1519,8 @@ struct tu_render_pass struct tu_query_pool { + struct vk_object_base base; + VkQueryType type; uint32_t stride; uint64_t size; @@ -1450,10 +1528,26 @@ struct tu_query_pool struct tu_bo bo; }; +enum tu_semaphore_kind +{ + TU_SEMAPHORE_NONE, + TU_SEMAPHORE_SYNCOBJ, +}; + +struct tu_semaphore_part +{ + enum tu_semaphore_kind kind; + union { + uint32_t syncobj; + }; +}; + struct tu_semaphore { - uint32_t syncobj; - uint32_t temp_syncobj; + struct vk_object_base base; + + struct tu_semaphore_part permanent; + struct tu_semaphore_part temporary; }; void @@ -1479,14 +1573,11 @@ tu_update_descriptor_set_with_template( VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void *pData); -int -tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id); - -int -tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size); - -int -tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base); +VkResult +tu_physical_device_init(struct tu_physical_device *device, + struct tu_instance *instance); +VkResult +tu_enumerate_devices(struct tu_instance *instance); int tu_drm_submitqueue_new(const struct tu_device *dev, @@ -1496,21 +1587,6 @@ tu_drm_submitqueue_new(const struct tu_device *dev, void tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id); -uint32_t -tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags); -uint32_t -tu_gem_import_dmabuf(const struct tu_device *dev, - int prime_fd, - uint64_t size); -int -tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle); -void -tu_gem_close(const struct tu_device *dev, uint32_t gem_handle); -uint64_t -tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle); -uint64_t -tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle); - #define TU_DEFINE_HANDLE_CASTS(__tu_type, __VkType) \ \ static inline struct __tu_type *__tu_type##_from_handle(__VkType _handle) \