X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fauxiliary%2Fgallivm%2Ftgsitollvm.cpp;h=8f7d3b71004b1793f9d06d3fc07b3d43aab88844;hb=74d23546c79fe8c8d87588fa423040e3b19a8fc6;hp=71f79ef5f58f1629863f4668f6340c439192b2f2;hpb=78379abcbf853b2cff8d832b45ecf0eeb54b2c58;p=mesa.git

diff --git a/src/gallium/auxiliary/gallivm/tgsitollvm.cpp b/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
index 71f79ef5f58..8f7d3b71004 100644
--- a/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
+++ b/src/gallium/auxiliary/gallivm/tgsitollvm.cpp
@@ -94,8 +94,8 @@ translate_declaration(struct gallivm_ir *prog,
       unsigned first, last, mask;
       uint interp_method;
 
-      first = decl->DeclarationRange.First;
-      last = decl->DeclarationRange.Last;
+      first = decl->Range.First;
+      last = decl->Range.Last;
       mask = decl->Declaration.UsageMask;
 
       /* Do not touch WPOS.xy */
@@ -149,7 +149,7 @@ translate_declarationir(struct gallivm_ir *,
                       struct tgsi_full_declaration *)
 {
    if (decl->Declaration.File == TGSI_FILE_ADDRESS) {
-      int idx = decl->DeclarationRange.First;
+      int idx = decl->Range.First;
       storage->addAddress(idx);
    }
 }
@@ -234,26 +234,26 @@ translate_instruction(llvm::Module *module,
    inputs[3] = 0;
 
    for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
-      struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+      struct tgsi_full_src_register *src = &inst->Src[i];
       llvm::Value *val = 0;
       llvm::Value *indIdx = 0;
 
-      if (src->SrcRegister.Indirect) {
-         indIdx = storage->addrElement(src->SrcRegisterInd.Index);
+      if (src->Register.Indirect) {
+         indIdx = storage->addrElement(src->Indirect.Index);
          indIdx = storage->extractIndex(indIdx);
       }
-      if (src->SrcRegister.File == TGSI_FILE_CONSTANT) {
-         val = storage->constElement(src->SrcRegister.Index, indIdx);
-      } else if (src->SrcRegister.File == TGSI_FILE_INPUT) {
-         val = storage->inputElement(src->SrcRegister.Index, indIdx);
-      } else if (src->SrcRegister.File == TGSI_FILE_TEMPORARY) {
-         val = storage->tempElement(src->SrcRegister.Index);
-      } else if (src->SrcRegister.File == TGSI_FILE_OUTPUT) {
-         val = storage->outputElement(src->SrcRegister.Index, indIdx);
-      } else if (src->SrcRegister.File == TGSI_FILE_IMMEDIATE) {
-         val = storage->immediateElement(src->SrcRegister.Index);
+      if (src->Register.File == TGSI_FILE_CONSTANT) {
+         val = storage->constElement(src->Register.Index, indIdx);
+      } else if (src->Register.File == TGSI_FILE_INPUT) {
+         val = storage->inputElement(src->Register.Index, indIdx);
+      } else if (src->Register.File == TGSI_FILE_TEMPORARY) {
+         val = storage->tempElement(src->Register.Index);
+      } else if (src->Register.File == TGSI_FILE_OUTPUT) {
+         val = storage->outputElement(src->Register.Index, indIdx);
+      } else if (src->Register.File == TGSI_FILE_IMMEDIATE) {
+         val = storage->immediateElement(src->Register.Index);
       } else {
-         fprintf(stderr, "ERROR: not supported llvm source %d\n", src->SrcRegister.File);
+         fprintf(stderr, "ERROR: not supported llvm source %d\n", src->Register.File);
          return;
       }
 
@@ -338,7 +338,7 @@ translate_instruction(llvm::Module *module,
       out = instr->sub(inputs[0], inputs[1]);
    }
       break;
-   case TGSI_OPCODE_LERP: {
+   case TGSI_OPCODE_LRP: {
       out = instr->lerp(inputs[0], inputs[1], inputs[2]);
    }
       break;
@@ -350,11 +350,11 @@ translate_instruction(llvm::Module *module,
       out = instr->cnd0(inputs[0], inputs[1], inputs[2]);
    }
       break;
-   case TGSI_OPCODE_DOT2ADD: {
+   case TGSI_OPCODE_DP2A: {
       out = instr->dot2add(inputs[0], inputs[1], inputs[2]);
    }
       break;
-   case TGSI_OPCODE_FRAC: {
+   case TGSI_OPCODE_FRC: {
       out = instr->frc(inputs[0]);
    }
       break;
@@ -362,25 +362,25 @@ translate_instruction(llvm::Module *module,
       out = instr->clamp(inputs[0]);
    }
       break;
-   case TGSI_OPCODE_FLOOR: {
+   case TGSI_OPCODE_FLR: {
       out = instr->floor(inputs[0]);
    }
       break;
    case TGSI_OPCODE_ROUND:
       break;
-   case TGSI_OPCODE_EXPBASE2: {
+   case TGSI_OPCODE_EX2: {
       out = instr->ex2(inputs[0]);
    }
       break;
-   case TGSI_OPCODE_LOGBASE2: {
+   case TGSI_OPCODE_LG2: {
       out = instr->lg2(inputs[0]);
    }
       break;
-   case TGSI_OPCODE_POWER: {
+   case TGSI_OPCODE_POW: {
       out = instr->pow(inputs[0], inputs[1]);
    }
       break;
-   case TGSI_OPCODE_CROSSPRODUCT: {
+   case TGSI_OPCODE_XPD: {
       out = instr->cross(inputs[0], inputs[1]);
    }
       break;
@@ -516,7 +516,7 @@ translate_instruction(llvm::Module *module,
       return;  //just update the state
    }
       break;
-   case TGSI_OPCODE_LOOP:
+   case TGSI_OPCODE_BGNFOR:
       break;
    case TGSI_OPCODE_REP:
       break;
@@ -532,7 +532,7 @@ translate_instruction(llvm::Module *module,
       return; //just update the state
    }
       break;
-   case TGSI_OPCODE_ENDLOOP:
+   case TGSI_OPCODE_ENDFOR:
       break;
    case TGSI_OPCODE_ENDREP:
       break;
@@ -552,7 +552,7 @@ translate_instruction(llvm::Module *module,
       break;
    case TGSI_OPCODE_SHL:
       break;
-   case TGSI_OPCODE_SHR:
+   case TGSI_OPCODE_ISHR:
       break;
    case TGSI_OPCODE_AND:
       break;
@@ -574,7 +574,7 @@ translate_instruction(llvm::Module *module,
       break;
    case TGSI_OPCODE_ENDPRIM:
       break;
-   case TGSI_OPCODE_BGNLOOP2: {
+   case TGSI_OPCODE_BGNLOOP: {
       instr->beginLoop();
       storage->setCurrentBlock(instr->currentBlock());
       return;
@@ -587,7 +587,7 @@ translate_instruction(llvm::Module *module,
       return;
    }
       break;
-   case TGSI_OPCODE_ENDLOOP2: {
+   case TGSI_OPCODE_ENDLOOP: {
       instr->endLoop();
       storage->setCurrentBlock(instr->currentBlock());
       return;
@@ -656,14 +656,14 @@ translate_instruction(llvm::Module *module,
 
    /* store results  */
    for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
-      struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
-
-      if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
-         storage->setOutputElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
-      } else if (dst->DstRegister.File == TGSI_FILE_TEMPORARY) {
-         storage->setTempElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
-      } else if (dst->DstRegister.File == TGSI_FILE_ADDRESS) {
-         storage->setAddrElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
+      struct tgsi_full_dst_register *dst = &inst->Dst[i];
+
+      if (dst->Register.File == TGSI_FILE_OUTPUT) {
+         storage->setOutputElement(dst->Register.Index, out, dst->Register.WriteMask);
+      } else if (dst->Register.File == TGSI_FILE_TEMPORARY) {
+         storage->setTempElement(dst->Register.Index, out, dst->Register.WriteMask);
+      } else if (dst->Register.File == TGSI_FILE_ADDRESS) {
+         storage->setAddrElement(dst->Register.Index, out, dst->Register.WriteMask);
       } else {
          fprintf(stderr, "ERROR: unsupported LLVM destination!");
          assert(!"wrong destination");
@@ -683,16 +683,16 @@ translate_instructionir(llvm::Module *module,
    std::vector< std::vector<llvm::Value*> > inputs(inst->Instruction.NumSrcRegs);
 
    for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
-      struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+      struct tgsi_full_src_register *src = &inst->Src[i];
       std::vector<llvm::Value*> val;
       llvm::Value *indIdx = 0;
       int swizzle = swizzleInt(src);
 
-      if (src->SrcRegister.Indirect) {
-         indIdx = storage->addrElement(src->SrcRegisterInd.Index);
+      if (src->Register.Indirect) {
+         indIdx = storage->addrElement(src->Indirect.Index);
       }
-      val = storage->load((enum tgsi_file_type)src->SrcRegister.File,
-                          src->SrcRegister.Index, swizzle, instr->getIRBuilder(), indIdx);
+      val = storage->load((enum tgsi_file_type)src->Register.File,
+                          src->Register.Index, swizzle, instr->getIRBuilder(), indIdx);
 
       inputs[i] = val;
    }
@@ -764,40 +764,36 @@ translate_instructionir(llvm::Module *module,
       out = instr->sub(inputs[0], inputs[1]);
    }
       break;
-   case TGSI_OPCODE_LERP: {
+   case TGSI_OPCODE_LRP: {
    }
       break;
    case TGSI_OPCODE_CND:
       break;
    case TGSI_OPCODE_CND0:
       break;
-   case TGSI_OPCODE_DOT2ADD:
+   case TGSI_OPCODE_DP2A:
       break;
-   case TGSI_OPCODE_INDEX:
-      break;
-   case TGSI_OPCODE_NEGATE:
-      break;
-   case TGSI_OPCODE_FRAC: {
+   case TGSI_OPCODE_FRC: {
    }
       break;
    case TGSI_OPCODE_CLAMP:
       break;
-   case TGSI_OPCODE_FLOOR: {
+   case TGSI_OPCODE_FLR: {
    }
       break;
    case TGSI_OPCODE_ROUND:
       break;
-   case TGSI_OPCODE_EXPBASE2: {
+   case TGSI_OPCODE_EX2: {
    }
       break;
-   case TGSI_OPCODE_LOGBASE2: {
+   case TGSI_OPCODE_LG2: {
    }
       break;
-   case TGSI_OPCODE_POWER: {
+   case TGSI_OPCODE_POW: {
       out = instr->pow(inputs[0], inputs[1]);
    }
       break;
-   case TGSI_OPCODE_CROSSPRODUCT: {
+   case TGSI_OPCODE_XPD: {
    }
       break;
    case TGSI_OPCODE_ABS: {
@@ -894,7 +890,7 @@ translate_instructionir(llvm::Module *module,
    case TGSI_OPCODE_IF: {
    }
       break;
-   case TGSI_OPCODE_LOOP:
+   case TGSI_OPCODE_BGNFOR:
       break;
    case TGSI_OPCODE_REP:
       break;
@@ -904,7 +900,7 @@ translate_instructionir(llvm::Module *module,
    case TGSI_OPCODE_ENDIF: {
    }
       break;
-   case TGSI_OPCODE_ENDLOOP:
+   case TGSI_OPCODE_ENDFOR:
       break;
    case TGSI_OPCODE_ENDREP:
       break;
@@ -923,7 +919,7 @@ translate_instructionir(llvm::Module *module,
       break;
    case TGSI_OPCODE_SHL:
       break;
-   case TGSI_OPCODE_SHR:
+   case TGSI_OPCODE_ISHR:
       break;
    case TGSI_OPCODE_AND:
       break;
@@ -945,13 +941,13 @@ translate_instructionir(llvm::Module *module,
       break;
    case TGSI_OPCODE_ENDPRIM:
       break;
-   case TGSI_OPCODE_BGNLOOP2: {
+   case TGSI_OPCODE_BGNLOOP: {
    }
       break;
    case TGSI_OPCODE_BGNSUB: {
    }
       break;
-   case TGSI_OPCODE_ENDLOOP2: {
+   case TGSI_OPCODE_ENDLOOP: {
    }
       break;
    case TGSI_OPCODE_ENDSUB: {
@@ -997,9 +993,9 @@ translate_instructionir(llvm::Module *module,
 
    /* store results  */
    for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
-      struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
-      storage->store((enum tgsi_file_type)dst->DstRegister.File,
-                     dst->DstRegister.Index, out, dst->DstRegister.WriteMask,
+      struct tgsi_full_dst_register *dst = &inst->Dst[i];
+      storage->store((enum tgsi_file_type)dst->Register.File,
+                     dst->Register.Index, out, dst->Register.WriteMask,
 		     instr->getIRBuilder() );
    }
 }