X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdocs%2Fsource%2Ftgsi.rst;h=287f4b7272977625e8905876c42403ff851c21b2;hb=5167ca27fa3ad9534d24fef76a13c6513b00ebdb;hp=be1f411b91a4959edd040efb08076d7132432dea;hpb=068c3ad2cbef748783837ebbaa6cdca325d0475e;p=mesa.git diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index be1f411b91a..287f4b72729 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -285,19 +285,6 @@ Perform a * b + c with no intermediate rounding step. dst.w = src0.w \times src1.w + src2.w -.. opcode:: DP2A - 2-component Dot Product And Add - -.. math:: - - dst.x = src0.x \times src1.x + src0.y \times src1.y + src2.x - - dst.y = src0.x \times src1.x + src0.y \times src1.y + src2.x - - dst.z = src0.x \times src1.x + src0.y \times src1.y + src2.x - - dst.w = src0.x \times src1.x + src0.y \times src1.y + src2.x - - .. opcode:: FRC - Fraction .. math:: @@ -363,26 +350,17 @@ This instruction replicates its result. dst = src0.x^{src1.x} -.. opcode:: XPD - Cross Product -.. math:: +.. opcode:: LDEXP - Multiply Number by Integral Power of 2 - dst.x = src0.y \times src1.z - src1.y \times src0.z - - dst.y = src0.z \times src1.x - src1.z \times src0.x - - dst.z = src0.x \times src1.y - src1.x \times src0.y - - dst.w = 1 - - -.. opcode:: DPH - Homogeneous Dot Product - -This instruction replicates its result. +src1 is an integer. .. math:: - dst = src0.x \times src1.x + src0.y \times src1.y + src0.z \times src1.z + src1.w + dst.x = src0.x * 2^{src1.x} + dst.y = src0.y * 2^{src1.y} + dst.z = src0.z * 2^{src1.z} + dst.w = src0.w * 2^{src1.w} .. opcode:: COS - Cosine @@ -439,17 +417,35 @@ This instruction replicates its result. .. opcode:: PK2US - Pack Two Unsigned 16-bit Scalars - TBD +This instruction replicates its result. + +.. math:: + + dst = f32\_to\_unorm16(src.x) | f32\_to\_unorm16(src.y) << 16 .. opcode:: PK4B - Pack Four Signed 8-bit Scalars - TBD +This instruction replicates its result. + +.. math:: + + dst = f32\_to\_snorm8(src.x) | + (f32\_to\_snorm8(src.y) << 8) | + (f32\_to\_snorm8(src.z) << 16) | + (f32\_to\_snorm8(src.w) << 24) .. opcode:: PK4UB - Pack Four Unsigned 8-bit Scalars - TBD +This instruction replicates its result. + +.. math:: + + dst = f32\_to\_unorm8(src.x) | + (f32\_to\_unorm8(src.y) << 8) | + (f32\_to\_unorm8(src.z) << 16) | + (f32\_to\_unorm8(src.w) << 24) .. opcode:: SEQ - Set On Equal @@ -685,19 +681,6 @@ This instruction replicates its result. Unconditional discard. Allowed in fragment shaders only. -.. opcode:: SCS - Sine Cosine - -.. math:: - - dst.x = \cos{src.x} - - dst.y = \sin{src.x} - - dst.z = 0 - - dst.w = 1 - - .. opcode:: TXB - Texture Lookup With Bias for cube map array textures and shadow cube maps, the bias value @@ -835,19 +818,6 @@ This instruction replicates its result. dst = texture\_sample(unit, coord, lod) -.. opcode:: CALLNZ - Subroutine Call If Not Zero - - TBD - -.. note:: - - Considered for cleanup. - -.. note:: - - Considered for removal. - - Compute ISA ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -1643,7 +1613,7 @@ GLSL ISA These opcodes are part of :term:`GLSL`'s opcode set. Support for these opcodes is determined by a special capability bit, ``GLSL``. -Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH). +Some require glsl version 1.30 (UIF/SWITCH/CASE/DEFAULT/ENDSWITCH). .. opcode:: CAL - Subroutine Call @@ -1699,20 +1669,6 @@ Some require glsl version 1.30 (UIF/BREAKC/SWITCH/CASE/DEFAULT/ENDSWITCH). or switch/endswitch. -.. opcode:: BREAKC - Break Conditional - - Conditionally moves the point of execution to the instruction after the - next endloop or endswitch. The instruction must appear within a loop/endloop - or switch/endswitch. - Condition evaluates to true if src0.x != 0 where src0.x is interpreted - as an integer register. - -.. note:: - - Considered for removal as it's quite inconsistent wrt other opcodes - (could emulate with UIF/BRK/ENDIF). - - .. opcode:: IF - Float If Start an IF ... ELSE .. ENDIF block. Condition evaluates to true if @@ -1836,7 +1792,7 @@ two-component vectors with doubled precision in each component. dst.z = src0.zw == src1.zw ? \sim 0 : 0 -.. opcode:: DSNE - Set on Equal +.. opcode:: DSNE - Set on Not Equal .. math:: @@ -1912,17 +1868,15 @@ two-component vectors with doubled precision in each component. Like the ``frexp()`` routine in many math libraries, this opcode stores the exponent of its source to ``dst0``, and the significand to ``dst1``, such that -:math:`dst1 \times 2^{dst0} = src` . +:math:`dst1 \times 2^{dst0} = src` . The results are replicated across +channels. .. math:: - dst0.xy = exp(src.xy) - - dst1.xy = frac(src.xy) + dst0.xy = dst.zw = frac(src.xy) - dst0.zw = exp(src.zw) + dst1 = frac(src.xy) - dst1.zw = frac(src.zw) .. opcode:: DLDEXP - Multiply Number by Integral Power of 2 @@ -1933,7 +1887,7 @@ source is an integer. dst.xy = src0.xy \times 2^{src1.x} - dst.zw = src0.zw \times 2^{src1.y} + dst.zw = src0.zw \times 2^{src1.z} .. opcode:: DMIN - Minimum @@ -2273,9 +2227,9 @@ two-component vectors with 64-bits in each component. .. math:: - dst.xy = (uint64_t) src0.x + dst.xy = (int64_t) src0.x - dst.zw = (uint64_t) src0.y + dst.zw = (int64_t) src0.y .. opcode:: I2I64 - Signed Integer to 64-bit Integer @@ -2543,6 +2497,18 @@ after lookup. NOTE: no driver has implemented this opcode yet (and no state tracker emits it). This information is subject to change. +.. opcode:: LOD - level of detail + + Same syntax as the SAMPLE opcode but instead of performing an actual + texture lookup/filter, return the computed LOD information that the + texture pipe would use to access the texture. The Y component contains + the computed LOD lambda_prime. The X component contains the LOD that will + be accessed, based on min/max lod's and mipmap filters. + The Z and W components are set to 0. + + Syntax: ``LOD dst, address, sampler_view, sampler`` + + .. _resourceopcodes: Resource Access Opcodes @@ -2626,6 +2592,31 @@ For these opcodes, the resource can be a BUFFER, IMAGE, or MEMORY. barrier in between. +.. _bindlessopcodes: + +Bindless Opcodes +^^^^^^^^^^^^^^^^ + +These opcodes are for working with bindless sampler or image handles and +require PIPE_CAP_BINDLESS_TEXTURE. + +.. opcode:: IMG2HND - Get a bindless handle for a image + + Syntax: ``IMG2HND dst, image`` + + Example: ``IMG2HND TEMP[0], IMAGE[0]`` + + Sets 'dst' to a bindless handle for 'image'. + +.. opcode:: SAMP2HND - Get a bindless handle for a sampler + + Syntax: ``SAMP2HND dst, sampler`` + + Example: ``SAMP2HND TEMP[0], SAMP[0]`` + + Sets 'dst' to a bindless handle for 'sampler'. + + .. _threadsyncopcodes: Inter-thread synchronization opcodes @@ -2672,9 +2663,11 @@ logical operations. In this context atomicity means that another concurrent memory access operation that affects the same memory location is guaranteed to be performed strictly before or after the entire execution of the atomic operation. The resource may be a BUFFER, -IMAGE, or MEMORY. In the case of an image, the offset works the same as for -``LOAD`` and ``STORE``, specified above. These atomic operations may -only be used with 32-bit integer image formats. +IMAGE, HWATOMIC, or MEMORY. In the case of an image, the offset works +the same as for ``LOAD`` and ``STORE``, specified above. For atomic +counters, the offset is an immediate index to the base hw atomic +counter for this operation. +These atomic operations may only be used with 32-bit integer image formats. .. opcode:: ATOMUADD - Atomic integer addition @@ -2691,6 +2684,21 @@ only be used with 32-bit integer image formats. resource[offset] = dst_x + src_x +.. opcode:: ATOMFADD - Atomic floating point addition + + Syntax: ``ATOMFADD dst, resource, offset, src`` + + Example: ``ATOMFADD TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` + + The following operation is performed atomically: + +.. math:: + + dst_x = resource[offset] + + resource[offset] = dst_x + src_x + + .. opcode:: ATOMXCHG - Atomic exchange Syntax: ``ATOMXCHG dst, resource, offset, src`` @@ -2826,6 +2834,36 @@ only be used with 32-bit integer image formats. resource[offset] = (dst_x > src_x ? dst_x : src_x) +.. opcode:: ATOMINC_WRAP - Atomic increment + wrap around + + Syntax: ``ATOMINC_WRAP dst, resource, offset, src`` + + Example: ``ATOMINC_WRAP TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` + + The following operation is performed atomically: + +.. math:: + + dst_x = resource[offset] + 1 + + resource[offset] = dst_x <= src_x ? dst_x : 0 + + +.. opcode:: ATOMDEC_WRAP - Atomic decrement + wrap around + + Syntax: ``ATOMDEC_WRAP dst, resource, offset, src`` + + Example: ``ATOMDEC_WRAP TEMP[0], BUFFER[0], TEMP[1], TEMP[2]`` + + The following operation is performed atomically: + +.. math:: + + dst_x = resource[offset] + + resource[offset] = (dst_x > 0 && dst_x < src_x) ? dst_x - 1 : 0 + + .. _interlaneopcodes: Inter-lane opcodes @@ -3197,24 +3235,6 @@ tessellation evaluation shaders, respectively. Only the value written in the last vertex processing stage is used. -TGSI_SEMANTIC_CULLDIST -"""""""""""""""""""""" - -Used as distance to plane for performing application-defined culling -of individual primitives against a plane. When components of vertex -elements are given this label, these values are assumed to be a -float32 signed distance to a plane. Primitives will be completely -discarded if the plane distance for all of the vertices in the -primitive are < 0. If a vertex has a cull distance of NaN, that -vertex counts as "out" (as if its < 0); -The limits on both clip and cull distances are bound -by the PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT define which defines -the maximum number of components that can be used to hold the -distances and by the PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT -which specifies the maximum number of registers which can be -annotated with those semantics. - - TGSI_SEMANTIC_CLIPDIST """""""""""""""""""""" @@ -3471,10 +3491,22 @@ A bit mask of ``bit index <= TGSI_SEMANTIC_SUBGROUP_INVOCATION``, i.e. TGSI_SEMANTIC_SUBGROUP_LT_MASK """""""""""""""""""""""""""""" -A bit mask of ``bit index > TGSI_SEMANTIC_SUBGROUP_INVOCATION``, i.e. +A bit mask of ``bit index < TGSI_SEMANTIC_SUBGROUP_INVOCATION``, i.e. ``(1 << subgroup_invocation) - 1`` in arbitrary precision arithmetic. +TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL +"""""""""""""""""""""""""""""""""""""" + +A system value equal to the default_outer_level array set via set_tess_level. + + +TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL +"""""""""""""""""""""""""""""""""""""" + +A system value equal to the default_inner_level array set via set_tess_level. + + Declaration Interpolate ^^^^^^^^^^^^^^^^^^^^^^^ @@ -3551,6 +3583,31 @@ accessing a misaligned address is undefined. Usage of the STORE opcode is only allowed if the WR (writable) flag is set. +Hardware Atomic Register File +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Hardware atomics are declared as a 2D array with an optional array id. + +The first member of the dimension is the buffer resource the atomic +is located in. +The second member is a range into the buffer resource, either for +one or multiple counters. If this is an array, the declaration will have +an unique array id. + +Each counter is 4 bytes in size, and index and ranges are in counters not bytes. +DCL HWATOMIC[0][0] +DCL HWATOMIC[0][1] + +This declares two atomics, one at the start of the buffer and one in the +second 4 bytes. + +DCL HWATOMIC[0][0] +DCL HWATOMIC[1][0] +DCL HWATOMIC[1][1..3], ARRAY(1) + +This declares 5 atomics, one in buffer 0 at 0, +one in buffer 1 at 0, and an array of 3 atomics in +the buffer 1, starting at 1. Properties ^^^^^^^^^^^^^^^^^^^^^^^^ @@ -3698,7 +3755,7 @@ of the operands are equal to 0. That means that 0 * Inf = 0. This should be set the same way for an entire pipeline. Note that this applies not only to the literal MUL TGSI opcode, but all FP32 multiplications implied by other operations, such as MAD, FMA, DP2, -DP3, DP4, DPH, DST, LOG, LRP, XPD, and possibly others. If there is a +DP3, DP4, DST, LOG, LRP, and possibly others. If there is a mismatch between shaders, then it is unspecified whether this behavior will be enabled.