X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fetnaviv%2Fetnaviv_screen.c;h=8fd118438bd14d877ad9ebd8764f3ae1e87c0300;hb=0f888ad4be32d1c66e2749feacb8b88def03fac9;hp=57634201131759d67a090c4b8b80732347d819a4;hpb=fe3bb8cdb519a01e6315ce6f142827aece3d4a41;p=mesa.git diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 57634201131..8fd118438bd 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -45,6 +45,9 @@ #include "state_tracker/drm_driver.h" +#define ETNA_DRM_VERSION(major, minor) ((major) << 16 | (minor)) +#define ETNA_DRM_VERSION_FENCE_FD ETNA_DRM_VERSION(1, 1) + static const struct debug_named_value debug_options[] = { {"dbg_msgs", ETNA_DBG_MSGS, "Print debug messages"}, {"frame_msgs", ETNA_DBG_FRAME_MSGS, "Print frame messages"}, @@ -62,6 +65,7 @@ static const struct debug_named_value debug_options[] = { {"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered primitive"}, {"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"}, {"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered primitive"}, + {"shaderdb", ETNA_DBG_SHADERDB, "Enable shaderdb output"}, DEBUG_NAMED_VALUE_END }; @@ -136,6 +140,8 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: return 1; + case PIPE_CAP_NATIVE_FENCE_FD: + return screen->drm_version >= ETNA_DRM_VERSION_FENCE_FD; /* Memory */ case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: @@ -179,7 +185,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: @@ -237,11 +242,21 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: - case PIPE_CAP_NATIVE_FENCE_FD: case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: case PIPE_CAP_TGSI_FS_FBFETCH: case PIPE_CAP_TGSI_MUL_ZERO_WINS: + case PIPE_CAP_DOUBLES: case PIPE_CAP_INT64: + case PIPE_CAP_INT64_DIVMOD: + case PIPE_CAP_TGSI_TEX_TXF_LZ: + case PIPE_CAP_TGSI_CLOCK: + case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: + case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: + case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: + case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: + case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: + case PIPE_CAP_POST_DEPTH_COVERAGE: return 0; /* Stream output. */ @@ -351,7 +366,8 @@ etna_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) } static int -etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, +etna_screen_get_shader_param(struct pipe_screen *pscreen, + enum pipe_shader_type shader, enum pipe_shader_cap param) { struct etna_screen *screen = etna_screen(pscreen); @@ -391,8 +407,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return 64; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return 1; - case PIPE_SHADER_CAP_MAX_PREDS: - return 0; /* nothing uses this */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: @@ -415,7 +429,6 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return 4096; - case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: @@ -428,6 +441,7 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: + case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: return 0; } @@ -471,11 +485,8 @@ etna_screen_is_format_supported(struct pipe_screen *pscreen, return FALSE; if (usage & PIPE_BIND_RENDER_TARGET) { - /* If render target, must be RS-supported format that is not rb swapped. - * Exposing rb swapped (or other swizzled) formats for rendering would - * involve swizzing in the pixel shader. - */ - if (translate_rs_format(format) != ETNA_NO_MATCH && !translate_rs_format_rb_swap(format)) { + /* if render target, must be RS-supported format */ + if (translate_rs_format(format) != ETNA_NO_MATCH) { /* Validate MSAA; number of samples must be allowed, and render target * must have MSAA'able format. */ if (sample_count > 1) { @@ -578,16 +589,6 @@ etna_get_specs(struct etna_screen *screen) DBG("could not get ETNA_GPU_PIXEL_PIPES"); goto fail; } - if (val < 1 && val > ETNA_MAX_PIXELPIPES) { - if (val == 0) { - fprintf(stderr, "Warning: zero pixel pipes (update kernel?)\n"); - val = 1; - } else { - fprintf(stderr, "Error: bad pixel pipes value %u\n", - (unsigned int)val); - goto fail; - } - } screen->specs.pixel_pipes = val; if (etna_gpu_get_param(screen->gpu, ETNA_GPU_NUM_CONSTANTS, &val)) { @@ -625,14 +626,30 @@ etna_get_specs(struct etna_screen *screen) screen->specs.has_new_sin_cos = VIV_FEATURE(screen, chipMinorFeatures3, HAS_FAST_TRANSCENDENTALS); - if (instruction_count > 256) { /* unified instruction memory? */ + if (VIV_FEATURE(screen, chipMinorFeatures3, INSTRUCTION_CACHE)) { + /* GC3000 - this core is capable of loading shaders from + * memory. It can also run shaders from registers, as a fallback, but + * "max_instructions" does not have the correct value. It has place for + * 2*256 instructions just like GC2000, but the offsets are slightly + * different. + */ screen->specs.vs_offset = 0xC000; - screen->specs.ps_offset = 0xD000; /* like vivante driver */ + /* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses + * this mirror for writing PS instructions, probably safest to do the + * same. + */ + screen->specs.ps_offset = 0x8000 + 0x1000; screen->specs.max_instructions = 256; } else { - screen->specs.vs_offset = 0x4000; - screen->specs.ps_offset = 0x6000; - screen->specs.max_instructions = instruction_count / 2; + if (instruction_count > 256) { /* unified instruction memory? */ + screen->specs.vs_offset = 0xC000; + screen->specs.ps_offset = 0xD000; /* like vivante driver */ + screen->specs.max_instructions = 256; + } else { + screen->specs.vs_offset = 0x4000; + screen->specs.ps_offset = 0x6000; + screen->specs.max_instructions = instruction_count / 2; + } } if (VIV_FEATURE(screen, chipMinorFeatures1, HALTI0)) { @@ -666,6 +683,10 @@ etna_get_specs(struct etna_screen *screen) screen->specs.max_rendertarget_size = VIV_FEATURE(screen, chipMinorFeatures0, RENDERTARGET_8K) ? 8192 : 2048; + screen->specs.single_buffer = VIV_FEATURE(screen, chipMinorFeatures4, SINGLE_BUFFER); + if (screen->specs.single_buffer) + DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes); + return true; fail: @@ -723,6 +744,7 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, { struct etna_screen *screen = CALLOC_STRUCT(etna_screen); struct pipe_screen *pscreen; + drmVersionPtr version; uint64_t val; if (!screen) @@ -738,10 +760,15 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, goto fail; } + version = drmGetVersion(screen->ro->gpu_fd); + screen->drm_version = ETNA_DRM_VERSION(version->version_major, + version->version_minor); + drmFreeVersion(version); + etna_mesa_debug = debug_get_option_etna_mesa_debug(); - /* FIXME: Disable tile status for stability at the moment */ - etna_mesa_debug |= ETNA_DBG_NO_TS; + /* Disable autodisable for correct rendering with TS */ + etna_mesa_debug |= ETNA_DBG_NO_AUTODISABLE; screen->pipe = etna_pipe_new(gpu, ETNA_PIPE_3D); if (!screen->pipe) { @@ -791,9 +818,31 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, } screen->features[4] = val; + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { + DBG("could not get ETNA_GPU_FEATURES_5"); + goto fail; + } + screen->features[5] = val; + + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { + DBG("could not get ETNA_GPU_FEATURES_6"); + goto fail; + } + screen->features[6] = val; + if (!etna_get_specs(screen)) goto fail; + /* apply debug options that disable individual features */ + if (DBG_ENABLED(ETNA_DBG_NO_EARLY_Z)) + screen->features[viv_chipFeatures] |= chipFeatures_NO_EARLY_Z; + if (DBG_ENABLED(ETNA_DBG_NO_TS)) + screen->features[viv_chipFeatures] &= ~chipFeatures_FAST_CLEAR; + if (DBG_ENABLED(ETNA_DBG_NO_AUTODISABLE)) + screen->features[viv_chipMinorFeatures1] &= ~chipMinorFeatures1_AUTO_DISABLE; + if (DBG_ENABLED(ETNA_DBG_NO_SUPERTILE)) + screen->specs.can_supertile = 0; + pscreen->destroy = etna_screen_destroy; pscreen->get_param = etna_screen_get_param; pscreen->get_paramf = etna_screen_get_paramf;