X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fetnaviv%2Fetnaviv_state.c;h=cd9f974112d9bb8d37e516d5937ee6eb00033894;hb=0f888ad4be32d1c66e2749feacb8b88def03fac9;hp=141a34a4c673ede399506d173bc645f8b5fb64d3;hpb=56314f5bafdfeb514adf8401c52f216bd430bbb2;p=mesa.git

diff --git a/src/gallium/drivers/etnaviv/etnaviv_state.c b/src/gallium/drivers/etnaviv/etnaviv_state.c
index 141a34a4c67..cd9f974112d 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_state.c
@@ -86,7 +86,8 @@ etna_set_sample_mask(struct pipe_context *pctx, unsigned sample_mask)
 }
 
 static void
-etna_set_constant_buffer(struct pipe_context *pctx, uint shader, uint index,
+etna_set_constant_buffer(struct pipe_context *pctx,
+      enum pipe_shader_type shader, uint index,
       const struct pipe_constant_buffer *cb)
 {
    struct etna_context *ctx = etna_context(pctx);
@@ -167,8 +168,8 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
          cs->PE_COLOR_ADDR = cbuf->reloc[0];
          cs->PE_COLOR_ADDR.flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
       } else {
-         /* Rendered textures must always be multi-tiled */
-         assert(res->layout & ETNA_LAYOUT_BIT_MULTI);
+         /* Rendered textures must always be multi-tiled, or single-buffer mode must be supported */
+         assert((res->layout & ETNA_LAYOUT_BIT_MULTI) || ctx->specs.single_buffer);
          for (int i = 0; i < ctx->specs.pixel_pipes; i++) {
             cs->PE_PIPE_COLOR_ADDR[i] = cbuf->reloc[i];
             cs->PE_PIPE_COLOR_ADDR[i].flags = ETNA_RELOC_READ | ETNA_RELOC_WRITE;
@@ -330,6 +331,12 @@ etna_set_framebuffer_state(struct pipe_context *pctx,
 
    cs->TS_MEM_CONFIG = ts_mem_config;
 
+   /* Single buffer setup. There is only one switch for this, not a separate
+    * one per color buffer / depth buffer. To keep the logic simple always use
+    * single buffer when this feature is available.
+    */
+   cs->PE_LOGIC_OP = VIVS_PE_LOGIC_OP_SINGLE_BUFFER(ctx->specs.single_buffer ? 2 : 0);
+
    ctx->framebuffer_s = *sv; /* keep copy of original structure */
    ctx->dirty |= ETNA_DIRTY_FRAMEBUFFER;
 }
@@ -421,11 +428,11 @@ etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
       struct compiled_set_vertex_buffer *cs = &so->cvb[idx];
       struct pipe_vertex_buffer *vbi = &so->vb[idx];
 
-      assert(!vbi->user_buffer); /* XXX support user_buffer using
-                                    etna_usermem_map */
+      assert(!vbi->is_user_buffer); /* XXX support user_buffer using
+                                       etna_usermem_map */
 
-      if (vbi->buffer) { /* GPU buffer */
-         cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer)->bo;
+      if (vbi->buffer.resource) { /* GPU buffer */
+         cs->FE_VERTEX_STREAM_BASE_ADDR.bo = etna_resource(vbi->buffer.resource)->bo;
          cs->FE_VERTEX_STREAM_BASE_ADDR.offset = vbi->buffer_offset;
          cs->FE_VERTEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
          cs->FE_VERTEX_STREAM_CONTROL =
@@ -439,34 +446,6 @@ etna_set_vertex_buffers(struct pipe_context *pctx, unsigned start_slot,
    ctx->dirty |= ETNA_DIRTY_VERTEX_BUFFERS;
 }
 
-static void
-etna_set_index_buffer(struct pipe_context *pctx, const struct pipe_index_buffer *ib)
-{
-   struct etna_context *ctx = etna_context(pctx);
-   uint32_t ctrl;
-
-   if (ib) {
-      pipe_resource_reference(&ctx->index_buffer.ib.buffer, ib->buffer);
-      memcpy(&ctx->index_buffer.ib, ib, sizeof(ctx->index_buffer.ib));
-      ctrl = translate_index_size(ctx->index_buffer.ib.index_size);
-   } else {
-      pipe_resource_reference(&ctx->index_buffer.ib.buffer, NULL);
-      ctrl = 0;
-   }
-
-   if (ctx->index_buffer.ib.buffer && ctrl != ETNA_NO_MATCH) {
-      ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = etna_resource(ctx->index_buffer.ib.buffer)->bo;
-      ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.offset = ctx->index_buffer.ib.offset;
-      ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.flags = ETNA_RELOC_READ;
-      ctx->index_buffer.FE_INDEX_STREAM_CONTROL = ctrl;
-   } else {
-      ctx->index_buffer.FE_INDEX_STREAM_BASE_ADDR.bo = NULL;
-      ctx->index_buffer.FE_INDEX_STREAM_CONTROL = 0;
-   }
-
-   ctx->dirty |= ETNA_DIRTY_INDEX_BUFFER;
-}
-
 static void
 etna_blend_state_bind(struct pipe_context *pctx, void *bs)
 {
@@ -645,7 +624,6 @@ etna_state_init(struct pipe_context *pctx)
    pctx->set_viewport_states = etna_set_viewport_states;
 
    pctx->set_vertex_buffers = etna_set_vertex_buffers;
-   pctx->set_index_buffer = etna_set_index_buffer;
 
    pctx->bind_blend_state = etna_blend_state_bind;
    pctx->delete_blend_state = etna_blend_state_delete;