X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Fa4xx%2Ffd4_draw.c;h=a76f9e8c4347d1570f2cca5d98028c19b51d093a;hb=fd6ed7b5628678ada0db3bf6ae1bcf80628c6947;hp=af02d31fb913cbbb61b9d2eaf4bd49d42fe22dd7;hpb=291ac872a445f3edebd668b27e910a79e1de5a00;p=mesa.git

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
index af02d31fb91..a76f9e8c434 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
@@ -49,9 +49,6 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 	const struct pipe_draw_info *info = emit->info;
 	enum pc_di_primtype primtype = ctx->primtypes[info->mode];
 
-	if (!(fd4_emit_get_vp(emit) && fd4_emit_get_fp(emit)))
-		return;
-
 	fd4_emit_state(ctx, ring, emit);
 
 	if (emit->dirty & (FD_DIRTY_VTXBUF | FD_DIRTY_VTXSTATE))
@@ -71,8 +68,7 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring,
 			(info->mode == PIPE_PRIM_POINTS))
 		primtype = DI_PT_POINTLIST_PSIZE;
 
-	fd4_draw_emit(ctx, ring,
-			primtype,
+	fd4_draw_emit(ctx->batch, ring, primtype,
 			emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY,
 			info);
 }
@@ -88,40 +84,21 @@ fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key)
 	struct ir3_shader_key *last_key = &fd4_ctx->last_key;
 
 	if (!ir3_shader_key_equal(last_key, key)) {
-		if (last_key->has_per_samp || key->has_per_samp) {
-			if ((last_key->vsaturate_s != key->vsaturate_s) ||
-					(last_key->vsaturate_t != key->vsaturate_t) ||
-					(last_key->vsaturate_r != key->vsaturate_r) ||
-					(last_key->vastc_srgb != key->vastc_srgb))
-				ctx->dirty |= FD_SHADER_DIRTY_VP;
-
-			if ((last_key->fsaturate_s != key->fsaturate_s) ||
-					(last_key->fsaturate_t != key->fsaturate_t) ||
-					(last_key->fsaturate_r != key->fsaturate_r) ||
-					(last_key->fastc_srgb != key->fastc_srgb))
-				ctx->dirty |= FD_SHADER_DIRTY_FP;
+		if (ir3_shader_key_changes_fs(last_key, key)) {
+			ctx->dirty_shader[PIPE_SHADER_FRAGMENT] |= FD_DIRTY_SHADER_PROG;
+			ctx->dirty |= FD_DIRTY_PROG;
 		}
 
-		if (last_key->vclamp_color != key->vclamp_color)
-			ctx->dirty |= FD_SHADER_DIRTY_VP;
-
-		if (last_key->fclamp_color != key->fclamp_color)
-			ctx->dirty |= FD_SHADER_DIRTY_FP;
-
-		if (last_key->color_two_side != key->color_two_side)
-			ctx->dirty |= FD_SHADER_DIRTY_FP;
-
-		if (last_key->half_precision != key->half_precision)
-			ctx->dirty |= FD_SHADER_DIRTY_FP;
-
-		if (last_key->rasterflat != key->rasterflat)
-			ctx->dirty |= FD_SHADER_DIRTY_FP;
+		if (ir3_shader_key_changes_vs(last_key, key)) {
+			ctx->dirty_shader[PIPE_SHADER_VERTEX] |= FD_DIRTY_SHADER_PROG;
+			ctx->dirty |= FD_DIRTY_PROG;
+		}
 
 		fd4_ctx->last_key = *key;
 	}
 }
 
-static void
+static bool
 fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 {
 	struct fd4_context *fd4_ctx = fd4_context(ctx);
@@ -131,15 +108,12 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 		.prog = &ctx->prog,
 		.info = info,
 		.key = {
-			/* do binning pass first: */
-			.binning_pass = true,
 			.color_two_side = ctx->rasterizer->light_twoside,
 			.vclamp_color = ctx->rasterizer->clamp_vertex_color,
 			.fclamp_color = ctx->rasterizer->clamp_fragment_color,
 			.rasterflat = ctx->rasterizer->flatshade,
-			// TODO set .half_precision based on render target format,
-			// ie. float16 and smaller use half, float32 use full..
-			.half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF),
+			.half_precision = ctx->in_blit &&
+					fd_half_precision(&ctx->batch->framebuffer),
 			.ucp_enables = ctx->rasterizer->clip_plane_enable,
 			.has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
 					fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb),
@@ -156,249 +130,49 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info)
 		.sprite_coord_enable = ctx->rasterizer->sprite_coord_enable,
 		.sprite_coord_mode = ctx->rasterizer->sprite_coord_mode,
 	};
-	unsigned dirty;
 
 	fixup_shader_state(ctx, &emit.key);
 
-	dirty = ctx->dirty;
-	emit.dirty = dirty & ~(FD_DIRTY_BLEND);
-	draw_impl(ctx, ctx->binning_ring, &emit);
-
-	/* and now regular (non-binning) pass: */
-	emit.key.binning_pass = false;
-	emit.dirty = dirty;
-	emit.vp = NULL;   /* we changed key so need to refetch vp */
-	emit.fp = NULL;
-
-	if (ctx->rasterizer->rasterizer_discard) {
-		fd_wfi(ctx, ctx->ring);
-		OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
-		OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
-		OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
-		OUT_RING(ctx->ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
-	}
-
-	draw_impl(ctx, ctx->ring, &emit);
-
-	if (ctx->rasterizer->rasterizer_discard) {
-		fd_wfi(ctx, ctx->ring);
-		OUT_PKT3(ctx->ring, CP_REG_RMW, 3);
-		OUT_RING(ctx->ring, REG_A4XX_RB_RENDER_CONTROL);
-		OUT_RING(ctx->ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
-		OUT_RING(ctx->ring, 0);
-	}
-}
-
-/* clear operations ignore viewport state, so we need to reset it
- * based on framebuffer state:
- */
-static void
-reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
-{
-	float half_width = pfb->width * 0.5f;
-	float half_height = pfb->height * 0.5f;
-
-	OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 4);
-	OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0(half_width));
-	OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0(half_width));
-	OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0(half_height));
-	OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-half_height));
-}
-
-/* TODO maybe we should just migrate u_blitter for clear and do it in
- * core (so we get normal draw pass state mgmt and binning).. That should
- * work well enough for a3xx/a4xx (but maybe not a2xx?)
- */
-
-static void
-fd4_clear_binning(struct fd_context *ctx, unsigned dirty)
-{
-	struct fd4_context *fd4_ctx = fd4_context(ctx);
-	struct fd_ringbuffer *ring = ctx->binning_ring;
-	struct fd4_emit emit = {
-		.debug = &ctx->debug,
-		.vtx  = &fd4_ctx->solid_vbuf_state,
-		.prog = &ctx->solid_prog,
-		.key = {
-			.binning_pass = true,
-			.half_precision = true,
-		},
-		.dirty = dirty,
-	};
-
-	fd4_emit_state(ctx, ring, &emit);
-	fd4_emit_vertex_bufs(ring, &emit);
-	reset_viewport(ring, &ctx->framebuffer);
-
-	OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 2);
-	OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_VAROUT(0) |
-			A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
-	OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(PC_DRAW_TRIANGLES) |
-			A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(PC_DRAW_TRIANGLES));
+	enum fd_dirty_3d_state dirty = ctx->dirty;
 
-	OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
-	OUT_RING(ring, 0x00000002);
+	/* do regular pass first, since that is more likely to fail compiling: */
 
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
-			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
-}
-
-static void
-fd4_clear(struct fd_context *ctx, unsigned buffers,
-		const union pipe_color_union *color, double depth, unsigned stencil)
-{
-	struct fd4_context *fd4_ctx = fd4_context(ctx);
-	struct fd_ringbuffer *ring = ctx->ring;
-	struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
-	unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
-	unsigned dirty = ctx->dirty;
-	unsigned i;
-	struct fd4_emit emit = {
-		.debug = &ctx->debug,
-		.vtx  = &fd4_ctx->solid_vbuf_state,
-		.prog = &ctx->solid_prog,
-		.key = {
-			.half_precision = fd_half_precision(pfb),
-		},
-	};
+	if (!(fd4_emit_get_vp(&emit) && fd4_emit_get_fp(&emit)))
+		return false;
 
-	dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
-	dirty |= FD_DIRTY_PROG;
+	emit.key.binning_pass = false;
 	emit.dirty = dirty;
 
-	fd4_clear_binning(ctx, dirty);
-
-	OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
-	OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
-
-	/* emit generic state now: */
-	fd4_emit_state(ctx, ring, &emit);
-	reset_viewport(ring, pfb);
-
-	if (buffers & PIPE_CLEAR_DEPTH) {
-		OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
-		OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
-				A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
-				A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS));
-
-		fd_wfi(ctx, ring);
-		OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0, 2);
-		OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
-		OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(depth));
-		ctx->dirty |= FD_DIRTY_VIEWPORT;
-	} else {
-		OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
-		OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
-	}
-
-	if (buffers & PIPE_CLEAR_STENCIL) {
-		OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
-		OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(stencil) |
-				A4XX_RB_STENCILREFMASK_STENCILMASK(stencil) |
-				A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
-		OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
-				A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
-				0xff000000 | // XXX ???
-				A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
-
-		OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
-		OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
-				A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
-				A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_REPLACE) |
-				A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
-				A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
-		OUT_RING(ring, A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER);
-	} else {
-		OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
-		OUT_RING(ring, A4XX_RB_STENCILREFMASK_STENCILREF(0) |
-				A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
-				A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0));
-		OUT_RING(ring, A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
-				A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
-				A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0));
+	struct fd_ringbuffer *ring = ctx->batch->draw;
 
-		OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
-		OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
-				A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
-				A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
-				A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
-		OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
-	}
-
-	if (buffers & PIPE_CLEAR_COLOR) {
-		OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1);
-		OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER));
+	if (ctx->rasterizer->rasterizer_discard) {
+		fd_wfi(ctx->batch, ring);
+		OUT_PKT3(ring, CP_REG_RMW, 3);
+		OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
+		OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
+		OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
 	}
 
-	for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
-		mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0;
+	draw_impl(ctx, ctx->batch->draw, &emit);
 
-		OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
-		OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
-				A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
-
-		OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
-		OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
-				A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
-				A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
-				A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
-				A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
-				A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
+	if (ctx->rasterizer->rasterizer_discard) {
+		fd_wfi(ctx->batch, ring);
+		OUT_PKT3(ring, CP_REG_RMW, 3);
+		OUT_RING(ring, REG_A4XX_RB_RENDER_CONTROL);
+		OUT_RING(ring, ~A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
+		OUT_RING(ring, 0);
 	}
 
-	OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
-	OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
-			A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
-			A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
-			A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
-			A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
-			A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
-			A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
-			A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
-
-	fd4_emit_vertex_bufs(ring, &emit);
-
-	OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
-	OUT_RING(ring, 0x0);          /* XXX GRAS_ALPHA_CONTROL */
-
-	OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
-	OUT_RING(ring, 0x00000000);
-
-	/* until fastclear works: */
-	fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL);
-
-	OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
-	OUT_RING(ring, 0);            /* VFD_INDEX_OFFSET */
-	OUT_RING(ring, 0);            /* ??? UNKNOWN_2209 */
-
-	OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1);
-	OUT_RING(ring, 0xffffffff);   /* PC_RESTART_INDEX */
-
-	OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
-	OUT_RING(ring, 0x00000001);
-
-	fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY,
-			DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL);
-
-	OUT_PKT3(ring, CP_UNKNOWN_1A, 1);
-	OUT_RING(ring, 0x00000000);
+	/* and now binning pass: */
+	emit.key.binning_pass = true;
+	emit.dirty = dirty & ~(FD_DIRTY_BLEND);
+	emit.vp = NULL;   /* we changed key so need to refetch vp */
+	emit.fp = NULL;
+	draw_impl(ctx, ctx->batch->binning, &emit);
 
-	OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1);
-	OUT_RING(ring, A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR);
+	fd_context_all_clean(ctx);
 
-	OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
-	OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
-			A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
-			A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
-			A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
+	return true;
 }
 
 void
@@ -406,5 +180,4 @@ fd4_draw_init(struct pipe_context *pctx)
 {
 	struct fd_context *ctx = fd_context(pctx);
 	ctx->draw_vbo = fd4_draw_vbo;
-	ctx->clear = fd4_clear;
 }