X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Fa4xx%2Ffd4_draw.c;h=bc9cfae9aa07a6bf3de62fd417f626c9a22d1673;hb=b3fe196e21dbbb51e62ed42dce890ada2bfd6db8;hp=9a586c8806b70bff0bdd223cbe4b92159682d038;hpb=66f694b16c2279e9fac9d6970611e812742f6dc9;p=mesa.git diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c index 9a586c8806b..bc9cfae9aa0 100644 --- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c +++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c @@ -38,7 +38,7 @@ #include "fd4_context.h" #include "fd4_emit.h" #include "fd4_program.h" -#include "fd4_util.h" +#include "fd4_format.h" #include "fd4_zsa.h" @@ -47,6 +47,10 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring, struct fd4_emit *emit) { const struct pipe_draw_info *info = emit->info; + enum pc_di_primtype primtype = ctx->primtypes[info->mode]; + + if (!(fd4_emit_get_vp(emit) && fd4_emit_get_fp(emit))) + return; fd4_emit_state(ctx, ring, emit); @@ -54,14 +58,21 @@ draw_impl(struct fd_context *ctx, struct fd_ringbuffer *ring, fd4_emit_vertex_bufs(ring, emit); OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2); - OUT_RING(ring, info->start); /* VFD_INDEX_OFFSET */ + OUT_RING(ring, info->indexed ? info->index_bias : info->start); /* VFD_INDEX_OFFSET */ OUT_RING(ring, info->start_instance); /* ??? UNKNOWN_2209 */ OUT_PKT0(ring, REG_A4XX_PC_RESTART_INDEX, 1); OUT_RING(ring, info->primitive_restart ? /* PC_RESTART_INDEX */ info->restart_index : 0xffffffff); + /* points + psize -> spritelist: */ + if (ctx->rasterizer->point_size_per_vertex && + fd4_emit_get_vp(emit)->writes_psize && + (info->mode == PIPE_PRIM_POINTS)) + primtype = DI_PT_POINTLIST_PSIZE; + fd4_draw_emit(ctx, ring, + primtype, emit->key.binning_pass ? IGNORE_VISIBILITY : USE_VISIBILITY, info); } @@ -97,7 +108,7 @@ fixup_shader_state(struct fd_context *ctx, struct ir3_shader_key *key) if (last_key->half_precision != key->half_precision) ctx->prog.dirty |= FD_SHADER_DIRTY_FP; - if (last_key->alpha != key->alpha) + if (last_key->rasterflat != key->rasterflat) ctx->prog.dirty |= FD_SHADER_DIRTY_FP; fd4_ctx->last_key = *key; @@ -108,7 +119,6 @@ static void fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) { struct fd4_context *fd4_ctx = fd4_context(ctx); - struct pipe_framebuffer_state *pfb = &ctx->framebuffer; struct fd4_emit emit = { .vtx = &ctx->vtx, .prog = &ctx->prog, @@ -116,12 +126,13 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) .key = { /* do binning pass first: */ .binning_pass = true, - .color_two_side = ctx->rasterizer ? ctx->rasterizer->light_twoside : false, - .alpha = util_format_is_alpha(pipe_surface_format(pfb->cbufs[0])), + .color_two_side = ctx->rasterizer->light_twoside, + .rasterflat = ctx->rasterizer->flatshade, // TODO set .half_precision based on render target format, // ie. float16 and smaller use half, float32 use full.. .half_precision = !!(fd_mesa_debug & FD_DBG_FRAGHALF), - .has_per_samp = fd4_ctx->fsaturate || fd4_ctx->vsaturate, + .ucp_enables = ctx->rasterizer->clip_plane_enable, + .has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate), .vsaturate_s = fd4_ctx->vsaturate_s, .vsaturate_t = fd4_ctx->vsaturate_t, .vsaturate_r = fd4_ctx->vsaturate_r, @@ -129,8 +140,9 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) .fsaturate_t = fd4_ctx->fsaturate_t, .fsaturate_r = fd4_ctx->fsaturate_r, }, - .format = fd4_emit_format(pfb->cbufs[0]), - .rasterflat = ctx->rasterizer && ctx->rasterizer->flatshade, + .rasterflat = ctx->rasterizer->flatshade, + .sprite_coord_enable = ctx->rasterizer->sprite_coord_enable, + .sprite_coord_mode = ctx->rasterizer->sprite_coord_mode, }; unsigned dirty; @@ -144,6 +156,7 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info) emit.key.binning_pass = false; emit.dirty = dirty; emit.vp = NULL; /* we changed key so need to refetch vp */ + emit.fp = NULL; draw_impl(ctx, ctx->ring, &emit); } @@ -170,20 +183,16 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, struct fd4_context *fd4_ctx = fd4_context(ctx); struct fd_ringbuffer *ring = ctx->ring; struct pipe_framebuffer_state *pfb = &ctx->framebuffer; + unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0}; unsigned dirty = ctx->dirty; - unsigned ce, i; + unsigned i; struct fd4_emit emit = { .vtx = &fd4_ctx->solid_vbuf_state, .prog = &ctx->solid_prog, .key = { - .half_precision = true, + .half_precision = fd_half_precision(pfb), }, - .format = fd4_emit_format(pfb->cbufs[0]), }; - uint32_t colr = 0; - - if ((buffers & PIPE_CLEAR_COLOR) && pfb->nr_cbufs) - colr = pack_rgba(pfb->cbufs[0]->format, color->f); dirty &= FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR; dirty |= FD_DIRTY_PROG; @@ -257,16 +266,14 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, if (buffers & PIPE_CLEAR_COLOR) { OUT_PKT0(ring, REG_A4XX_RB_ALPHA_CONTROL, 1); OUT_RING(ring, A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER)); - ce = 0xf; - } else { - ce = 0x0; } - for (i = 0; i < 8; i++) { + for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) { + mrt_comp[i] = (buffers & (PIPE_CLEAR_COLOR0 << i)) ? 0xf : 0x0; + OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1); - OUT_RING(ring, A4XX_RB_MRT_CONTROL_FASTCLEAR | - A4XX_RB_MRT_CONTROL_B11 | - A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(ce)); + OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) | + A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf)); OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1); OUT_RING(ring, A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) | @@ -277,6 +284,16 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO)); } + OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1); + OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) | + A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) | + A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) | + A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) | + A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) | + A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) | + A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) | + A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7])); + fd4_emit_vertex_bufs(ring, &emit); OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1); @@ -285,14 +302,8 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, OUT_PKT0(ring, REG_A4XX_GRAS_CLEAR_CNTL, 1); OUT_RING(ring, 0x00000000); - OUT_PKT0(ring, REG_A4XX_RB_CLEAR_COLOR_DW0, 4); - OUT_RING(ring, colr); /* RB_CLEAR_COLOR_DW0 */ - OUT_RING(ring, colr); /* RB_CLEAR_COLOR_DW1 */ - OUT_RING(ring, colr); /* RB_CLEAR_COLOR_DW2 */ - OUT_RING(ring, colr); /* RB_CLEAR_COLOR_DW3 */ - /* until fastclear works: */ - fd4_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color->ui, NULL); + fd4_emit_const(ring, SHADER_FRAGMENT, 0, 0, 4, color->ui, NULL); OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2); OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */ @@ -305,7 +316,7 @@ fd4_clear(struct fd_context *ctx, unsigned buffers, OUT_RING(ring, 0x00000001); fd4_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX_SIZE_IGN, 0, 0, NULL); OUT_PKT3(ring, CP_UNKNOWN_1A, 1); OUT_RING(ring, 0x00000000);