X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Fa6xx%2Ffd6_resource.c;h=430044aebbb243ab4243314088092696c85c16b1;hb=8d9f5a28e3879523fbdd018a2b87223313333379;hp=ff869d7d87bb3473a0bc8fe037dfa6c27e06ad54;hpb=031e94dc72bda818e440bb66a8caf52e3d669748;p=mesa.git diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c index ff869d7d87b..430044aebbb 100644 --- a/src/gallium/drivers/freedreno/a6xx/fd6_resource.c +++ b/src/gallium/drivers/freedreno/a6xx/fd6_resource.c @@ -26,6 +26,9 @@ */ #include "fd6_resource.h" +#include "fd6_format.h" + +#include "a6xx.xml.h" /* indexed by cpp, including msaa 2x and 4x: */ static const struct { @@ -70,23 +73,23 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma /* in layer_first layout, the level (slice) contains just one * layer (since in fact the layer contains the slices) */ - uint32_t layers_in_level = rsc->layer_first ? 1 : prsc->array_size; - int ta = rsc->cpp; + uint32_t layers_in_level = rsc->layout.layer_first ? 1 : prsc->array_size; + int ta = rsc->layout.cpp; /* The z16/r16 formats seem to not play by the normal tiling rules: */ - if ((rsc->cpp == 2) && (util_format_get_nr_components(format) == 1)) + if ((rsc->layout.cpp == 2) && (util_format_get_nr_components(format) == 1)) ta = 0; debug_assert(ta < ARRAY_SIZE(tile_alignment)); debug_assert(tile_alignment[ta].pitchalign); for (level = 0; level <= prsc->last_level; level++) { - struct fd_resource_slice *slice = fd_resource_slice(rsc, level); - bool linear_level = fd_resource_level_linear(prsc, level); + struct fdl_slice *slice = fd_resource_slice(rsc, level); + uint32_t tile_mode = fd_resource_tile_mode(prsc, level); uint32_t width, height; /* tiled levels of 3D textures are rounded up to PoT dimensions: */ - if ((prsc->target == PIPE_TEXTURE_3D) && rsc->tile_mode && !linear_level) { + if ((prsc->target == PIPE_TEXTURE_3D) && tile_mode) { width = twidth; height = theight; } else { @@ -96,7 +99,7 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma uint32_t aligned_height = height; uint32_t blocks; - if (rsc->tile_mode && !linear_level) { + if (tile_mode) { pitchalign = tile_alignment[ta].pitchalign; aligned_height = align(aligned_height, tile_alignment[ta].heightalign); @@ -130,23 +133,24 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma * range gets into range, we stop reducing it. */ if (prsc->target == PIPE_TEXTURE_3D) { - if (level <= 1 || (rsc->slices[level - 1].size0 > 0xf000)) { - slice->size0 = align(blocks * rsc->cpp, alignment); + if (level < 1 || fd_resource_slice(rsc, level - 1)->size0 > 0xf000) { + slice->size0 = align(blocks * rsc->layout.cpp, alignment); } else { - slice->size0 = rsc->slices[level - 1].size0; + slice->size0 = fd_resource_slice(rsc, level - 1)->size0; } } else { - slice->size0 = align(blocks * rsc->cpp, alignment); + slice->size0 = align(blocks * rsc->layout.cpp, alignment); } size += slice->size0 * depth * layers_in_level; #if 0 - debug_printf("%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u\n", + fprintf(stderr, "%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x tiling=%d\n", util_format_name(prsc->format), - width, height, depth, rsc->cpp, - level, slice->pitch * rsc->cpp, - slice->size0, size, aligned_height, blocks); + width, height, depth, rsc->layout.cpp, + level, slice->pitch * rsc->layout.cpp, + slice->size0, size, aligned_height, blocks, + slice->offset, fd_resource_tile_mode(prsc, level)); #endif depth = u_minify(depth, 1); @@ -159,6 +163,132 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment, enum pipe_format forma return size; } +/* A subset of the valid tiled formats can be compressed. We do + * already require tiled in order to be compressed, but just because + * it can be tiled doesn't mean it can be compressed. + */ +static bool +ok_ubwc_format(enum pipe_format pfmt) +{ + /* NOTE: both x24s8 and z24s8 map to RB6_X8Z24_UNORM, but UBWC + * does not seem to work properly when sampling x24s8.. possibly + * because we sample it as TFMT6_8_8_8_8_UINT. + * + * This could possibly be a hw limitation, or maybe something + * else wrong somewhere (although z24s8 blits and sampling with + * UBWC seem fine). Recheck on a later revision of a6xx + */ + if (pfmt == PIPE_FORMAT_X24S8_UINT) + return false; + + switch (fd6_pipe2color(pfmt)) { + case RB6_R10G10B10A2_UINT: + case RB6_R10G10B10A2_UNORM: + case RB6_R11G11B10_FLOAT: + case RB6_R16_FLOAT: + case RB6_R16G16B16A16_FLOAT: + case RB6_R16G16B16A16_SINT: + case RB6_R16G16B16A16_UINT: + case RB6_R16G16_FLOAT: + case RB6_R16G16_SINT: + case RB6_R16G16_UINT: + case RB6_R16_SINT: + case RB6_R16_UINT: + case RB6_R32G32B32A32_SINT: + case RB6_R32G32B32A32_UINT: + case RB6_R32G32_SINT: + case RB6_R32G32_UINT: + case RB6_R5G6B5_UNORM: + case RB6_R8G8B8A8_SINT: + case RB6_R8G8B8A8_UINT: + case RB6_R8G8B8A8_UNORM: + case RB6_R8G8B8_UNORM: + case RB6_R8G8_SINT: + case RB6_R8G8_UINT: + case RB6_R8G8_UNORM: + case RB6_Z24_UNORM_S8_UINT: + case RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8: + return true; + default: + return false; + } +} + +uint32_t +fd6_fill_ubwc_buffer_sizes(struct fd_resource *rsc) +{ +#define RBG_TILE_WIDTH_ALIGNMENT 64 +#define RGB_TILE_HEIGHT_ALIGNMENT 16 +#define UBWC_PLANE_SIZE_ALIGNMENT 4096 + + struct pipe_resource *prsc = &rsc->base; + uint32_t width = prsc->width0; + uint32_t height = prsc->height0; + + if (!ok_ubwc_format(prsc->format)) + return 0; + + /* limit things to simple single level 2d for now: */ + if ((prsc->depth0 != 1) || (prsc->array_size != 1) || (prsc->last_level != 0)) + return 0; + + uint32_t block_width, block_height; + switch (rsc->layout.cpp) { + case 2: + case 4: + block_width = 16; + block_height = 4; + break; + case 8: + block_width = 8; + block_height = 4; + break; + case 16: + block_width = 4; + block_height = 4; + break; + default: + return 0; + } + + uint32_t meta_stride = + ALIGN_POT(DIV_ROUND_UP(width, block_width), RBG_TILE_WIDTH_ALIGNMENT); + uint32_t meta_height = + ALIGN_POT(DIV_ROUND_UP(height, block_height), RGB_TILE_HEIGHT_ALIGNMENT); + uint32_t meta_size = + ALIGN_POT(meta_stride * meta_height, UBWC_PLANE_SIZE_ALIGNMENT); + + /* UBWC goes first, then color data.. this constraint is mainly only + * because it is what the kernel expects for scanout. For non-2D we + * could just use a separate UBWC buffer.. + */ + rsc->layout.ubwc_offset = 0; + rsc->layout.offset = meta_size; + rsc->layout.ubwc_pitch = meta_stride; + rsc->layout.ubwc_size = meta_size >> 2; /* in dwords??? */ + rsc->layout.tile_mode = TILE6_3; + + return meta_size; +} + +/** + * Ensure the rsc is in an ok state to be used with the specified format. + * This handles the case of UBWC buffers used with non-UBWC compatible + * formats, by triggering an uncompress. + */ +void +fd6_validate_format(struct fd_context *ctx, struct fd_resource *rsc, + enum pipe_format format) +{ + if (!rsc->layout.ubwc_size) + return; + + if (ok_ubwc_format(format)) + return; + + fd_resource_uncompress(ctx, rsc); +} + uint32_t fd6_setup_slices(struct fd_resource *rsc) { @@ -166,11 +296,11 @@ fd6_setup_slices(struct fd_resource *rsc) switch (rsc->base.target) { case PIPE_TEXTURE_3D: - rsc->layer_first = false; + rsc->layout.layer_first = false; alignment = 4096; break; default: - rsc->layer_first = true; + rsc->layout.layer_first = true; alignment = 1; break; }