X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_screen.c;h=531644c85e8423ded131c8b52ffd793403ea776f;hb=33af91dc07efcc2ca52200570a297de33c18a5f7;hp=6a44d7543d1800a757f1b722e01aefd608a68ed7;hpb=62981bbe656db1de5311ac5c23a69122748e681b;p=mesa.git diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 6a44d7543d1..531644c85e8 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -40,9 +40,10 @@ #include "util/os_time.h" -#include #include +#include #include +#include #include "freedreno_screen.h" #include "freedreno_resource.h" @@ -79,6 +80,10 @@ static const struct debug_named_value debug_options[] = { {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, {"lrz", FD_DBG_LRZ, "Enable experimental LRZ support (a5xx+)"}, + {"noindirect",FD_DBG_NOINDR, "Disable hw indirect draws (emulate on CPU)"}, + {"noblit", FD_DBG_NOBLIT, "Disable blitter (fallback to generic blit path)"}, + {"hiprio", FD_DBG_HIPRIO, "Force high-priority context"}, + {"ttile", FD_DBG_TTILE, "Enable texture tiling (a5xx)"}, DEBUG_NAMED_VALUE_END }; @@ -88,6 +93,17 @@ int fd_mesa_debug = 0; bool fd_binning_enabled = true; static bool glsl120 = false; +static const struct debug_named_value shader_debug_options[] = { + {"vs", FD_DBG_SHADER_VS, "Print shader disasm for vertex shaders"}, + {"fs", FD_DBG_SHADER_FS, "Print shader disasm for fragment shaders"}, + {"cs", FD_DBG_SHADER_CS, "Print shader disasm for compute shaders"}, + DEBUG_NAMED_VALUE_END +}; + +DEBUG_GET_ONCE_FLAGS_OPTION(fd_shader_debug, "FD_SHADER_DEBUG", shader_debug_options, 0) + +enum fd_shader_debug fd_shader_debug = 0; + static const char * fd_screen_get_name(struct pipe_screen *pscreen) { @@ -146,6 +162,7 @@ fd_screen_destroy(struct pipe_screen *pscreen) ralloc_free(screen->compiler); + free(screen->perfcntr_queries); free(screen); } @@ -163,10 +180,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Supported features (boolean caps). */ case PIPE_CAP_NPOT_TEXTURES: case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: - case PIPE_CAP_TWO_SIDED_STENCIL: case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: - case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: @@ -188,16 +203,12 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEXID_NOBASE: return is_a3xx(screen) || is_a4xx(screen); - case PIPE_CAP_USER_CONSTANT_BUFFERS: - return is_a4xx(screen) ? 0 : 1; - case PIPE_CAP_COMPUTE: return has_compute(screen); case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: - case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_TEXTURE_MIRROR_CLAMP: case PIPE_CAP_QUERY_MEMORY_INFO: case PIPE_CAP_PCI_GROUP: @@ -216,11 +227,16 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: case PIPE_CAP_CONDITIONAL_RENDER: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: - case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_CLIP_HALFZ: return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen); + case PIPE_CAP_FAKE_SW_MSAA: + return !fd_screen_get_param(pscreen, PIPE_CAP_TEXTURE_MULTISAMPLE); + + case PIPE_CAP_TEXTURE_MULTISAMPLE: + return is_a5xx(screen); + case PIPE_CAP_DEPTH_CLIP_DISABLE: return is_a3xx(screen) || is_a4xx(screen); @@ -245,15 +261,23 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_FLOAT_LINEAR: case PIPE_CAP_CUBE_MAP_ARRAY: - case PIPE_CAP_START_INSTANCE: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_TEXTURE_QUERY_LOD: return is_a4xx(screen) || is_a5xx(screen); + case PIPE_CAP_START_INSTANCE: + /* Note that a5xx can do this, it just can't (at least with + * current firmware) do draw_indirect with base_instance. + * Since draw_indirect is needed sooner (gles31 and gl40 vs + * gl42), hide base_instance on a5xx. :-/ + */ + return is_a4xx(screen); + case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 64; case PIPE_CAP_GLSL_FEATURE_LEVEL: + case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: if (glsl120) return 120; return is_ir3(screen) ? 140 : 120; @@ -263,6 +287,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 4; return 0; + case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: + if (is_a4xx(screen) || is_a5xx(screen)) + return 4; + return 0; + /* Unsupported features. */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: @@ -271,12 +300,10 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: - case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: - case PIPE_CAP_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: @@ -296,7 +323,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: case PIPE_CAP_GENERATE_MIPMAP: case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: - case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: case PIPE_CAP_CULL_DISTANCE: case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: @@ -328,6 +354,29 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: + case PIPE_CAP_FENCE_SIGNAL: + case PIPE_CAP_CONSTBUF0_FLAGS: + case PIPE_CAP_PACKED_UNIFORMS: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: + case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: + case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: + return 0; + + case PIPE_CAP_CONTEXT_PRIORITY_MASK: + return screen->priority_mask; + + case PIPE_CAP_DRAW_INDIRECT: + if (is_a4xx(screen) || is_a5xx(screen)) + return 1; + return 0; + + case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: + if (is_a4xx(screen) || is_a5xx(screen)) + return 1; return 0; case PIPE_CAP_LOAD_CONSTBUF: @@ -454,10 +503,9 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) return 16.0f; case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: return 15.0f; - case PIPE_CAPF_GUARD_BAND_LEFT: - case PIPE_CAPF_GUARD_BAND_TOP: - case PIPE_CAPF_GUARD_BAND_RIGHT: - case PIPE_CAPF_GUARD_BAND_BOTTOM: + case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE: + case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY: return 0.0f; } debug_printf("unknown paramf %d\n", param); @@ -530,6 +578,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: + case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; @@ -559,9 +608,9 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, return 32; case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS: case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS: - return 0; + case PIPE_SHADER_CAP_SCALAR_ISA: + return 1; case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: if (is_a5xx(screen)) { @@ -615,16 +664,20 @@ fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type, if (!has_compute(screen)) return 0; +#define RET(x) do { \ + if (ret) \ + memcpy(ret, x, sizeof(x)); \ + return sizeof(x); \ +} while (0) + switch (param) { case PIPE_COMPUTE_CAP_ADDRESS_BITS: - if (ret) { - uint32_t *address_bits = ret; - address_bits[0] = 32; - - if (is_a5xx(screen)) - address_bits[0] = 64; - } - return 1 * sizeof(uint32_t); +// don't expose 64b pointer support yet, until ir3 supports 64b +// math, otherwise spir64 target is used and we get 64b pointer +// calculations that we can't do yet +// if (is_a5xx(screen)) +// RET((uint32_t []){ 64 }); + RET((uint32_t []){ 32 }); case PIPE_COMPUTE_CAP_IR_TARGET: if (ret) @@ -632,54 +685,44 @@ fd_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type, return strlen(ir) * sizeof(char); case PIPE_COMPUTE_CAP_GRID_DIMENSION: - if (ret) { - uint64_t *grid_dimension = ret; - grid_dimension[0] = 3; - } - return 1 * sizeof(uint64_t); + RET((uint64_t []) { 3 }); case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: - if (ret) { - uint64_t *grid_size = ret; - grid_size[0] = 65535; - grid_size[1] = 65535; - grid_size[2] = 65535; - } - return 3 * sizeof(uint64_t) ; + RET(((uint64_t []) { 65535, 65535, 65535 })); case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: - if (ret) { - uint64_t *block_size = ret; - block_size[0] = 1024; - block_size[1] = 1024; - block_size[2] = 64; - } - return 3 * sizeof(uint64_t) ; + RET(((uint64_t []) { 1024, 1024, 64 })); case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: - if (ret) { - uint64_t *max_threads_per_block = ret; - *max_threads_per_block = 1024; - } - return sizeof(uint64_t); + RET((uint64_t []) { 1024 }); case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: + RET((uint64_t []) { screen->ram_size }); + case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: + RET((uint64_t []) { 32768 }); + case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: - break; + RET((uint64_t []) { 4096 }); + case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: - if (ret) { - uint64_t *max = ret; - *max = 32768; - } - return sizeof(uint64_t); + RET((uint64_t []) { screen->ram_size }); + case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: + RET((uint32_t []) { screen->max_freq / 1000000 }); + case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: + RET((uint32_t []) { 9999 }); // TODO + case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: + RET((uint32_t []) { 1 }); + case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: + RET((uint32_t []) { 32 }); // TODO + case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: - break; + RET((uint64_t []) { 1024 }); // TODO } return 0; @@ -705,12 +748,12 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen, { whandle->stride = stride; - if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { + if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { return fd_bo_get_name(bo, &whandle->handle) == 0; - } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { + } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) { whandle->handle = fd_bo_handle(bo); return TRUE; - } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { whandle->handle = fd_bo_dmabuf(bo); return TRUE; } else { @@ -725,11 +768,11 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen, struct fd_screen *screen = fd_screen(pscreen); struct fd_bo *bo; - if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { + if (whandle->type == WINSYS_HANDLE_TYPE_SHARED) { bo = fd_bo_from_name(screen->dev, whandle->handle); - } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { + } else if (whandle->type == WINSYS_HANDLE_TYPE_KMS) { bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); - } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + } else if (whandle->type == WINSYS_HANDLE_TYPE_FD) { bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); } else { DBG("Attempt to import unsupported handle type %d", whandle->type); @@ -752,6 +795,7 @@ fd_screen_create(struct fd_device *dev) uint64_t val; fd_mesa_debug = debug_get_option_fd_mesa_debug(); + fd_shader_debug = debug_get_option_fd_shader_debug(); if (fd_mesa_debug & FD_DBG_NOBIN) fd_binning_enabled = false; @@ -815,6 +859,18 @@ fd_screen_create(struct fd_device *dev) } screen->chip_id = val; + if (fd_pipe_get_param(screen->pipe, FD_NR_RINGS, &val)) { + DBG("could not get # of rings"); + screen->priority_mask = 0; + } else { + /* # of rings equates to number of unique priority values: */ + screen->priority_mask = (1 << val) - 1; + } + + struct sysinfo si; + sysinfo(&si); + screen->ram_size = si.totalram; + DBG("Pipe Info:"); DBG(" GPU-id: %d", screen->gpu_id); DBG(" Chip-id: 0x%08x", screen->chip_id); @@ -832,6 +888,7 @@ fd_screen_create(struct fd_device *dev) * send a patch ;-) */ switch (screen->gpu_id) { + case 205: case 220: fd2_screen_init(pscreen); break;