X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_screen.c;h=93b434b0bac564f58fe9caef0ee0bdebd4f1d6d8;hb=3a927e0aa34d2d27583063732eadfddccd1ebdd2;hp=5bbe4016a2aa4997151269b2097e28e4caf6c24b;hpb=190acb34ca165c840f87a25149eab1d1b7dc85c4;p=mesa.git diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 5bbe4016a2a..93b434b0bac 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -53,6 +53,9 @@ #include "a2xx/fd2_screen.h" #include "a3xx/fd3_screen.h" #include "a4xx/fd4_screen.h" +#include "a5xx/fd5_screen.h" + +#include "ir3/ir3_nir.h" /* XXX this should go away */ #include "state_tracker/drm_driver.h" @@ -71,6 +74,11 @@ static const struct debug_named_value debug_options[] = { {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 1.20 (rather than 1.30) on a3xx+"}, {"shaderdb", FD_DBG_SHADERDB, "Enable shaderdb output"}, {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, + {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"}, + {"nir", FD_DBG_NIR, "Prefer NIR as native IR"}, + {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"}, + {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, + {"nogrow", FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, DEBUG_NAMED_VALUE_END }; @@ -105,8 +113,18 @@ fd_screen_get_device_vendor(struct pipe_screen *pscreen) static uint64_t fd_screen_get_timestamp(struct pipe_screen *pscreen) { - int64_t cpu_time = os_time_get() * 1000; - return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta; + struct fd_screen *screen = fd_screen(pscreen); + + if (screen->has_timestamp) { + uint64_t n; + fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &n); + debug_assert(screen->max_freq > 0); + return n * 1000000000 / screen->max_freq; + } else { + int64_t cpu_time = os_time_get() * 1000; + return cpu_time + screen->cpu_gpu_time_delta; + } + } static void @@ -120,6 +138,14 @@ fd_screen_destroy(struct pipe_screen *pscreen) if (screen->dev) fd_device_del(screen->dev); + fd_bc_fini(&screen->batch_cache); + + slab_destroy_parent(&screen->transfer_pool); + + mtx_destroy(&screen->lock); + + ralloc_free(screen->compiler); + free(screen); } @@ -152,11 +178,17 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: - case PIPE_CAP_VERTEXID_NOBASE: + case PIPE_CAP_STRING_MARKER: + case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: return 1; + case PIPE_CAP_VERTEXID_NOBASE: + return is_a3xx(screen) || is_a4xx(screen); + + case PIPE_CAP_USER_CONSTANT_BUFFERS: + return is_a4xx(screen) ? 0 : 1; + case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: @@ -164,6 +196,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BARRIER: case PIPE_CAP_TEXTURE_MIRROR_CLAMP: case PIPE_CAP_COMPUTE: + case PIPE_CAP_QUERY_MEMORY_INFO: + case PIPE_CAP_PCI_GROUP: + case PIPE_CAP_PCI_BUS: + case PIPE_CAP_PCI_DEVICE: + case PIPE_CAP_PCI_FUNCTION: return 0; case PIPE_CAP_SM3: @@ -180,11 +217,14 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_DEPTH_CLIP_DISABLE: case PIPE_CAP_CLIP_HALFZ: - return is_a3xx(screen) || is_a4xx(screen); + return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen); + case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: + return 0; case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: if (is_a3xx(screen)) return 16; if (is_a4xx(screen)) return 32; + if (is_a5xx(screen)) return 32; return 0; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: /* We could possibly emulate more by pretending 2d/rect textures and @@ -192,6 +232,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) */ if (is_a3xx(screen)) return 8192; if (is_a4xx(screen)) return 16384; + if (is_a5xx(screen)) return 16384; return 0; case PIPE_CAP_TEXTURE_FLOAT_LINEAR: @@ -199,10 +240,10 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_START_INSTANCE: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_TEXTURE_QUERY_LOD: - return is_a4xx(screen); + return is_a4xx(screen) || is_a5xx(screen); case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: - return 256; + return 64; case PIPE_CAP_GLSL_FEATURE_LEVEL: if (glsl120) @@ -213,10 +254,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: - case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: - case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: @@ -226,6 +264,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: case PIPE_CAP_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: @@ -234,21 +274,60 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: case PIPE_CAP_DEPTH_BOUNDS_TEST: case PIPE_CAP_TGSI_TXQS: + /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */ case PIPE_CAP_FORCE_PERSAMPLE_INTERP: - case PIPE_CAP_SHAREABLE_SHADERS: case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: case PIPE_CAP_CLEAR_TEXTURE: + case PIPE_CAP_DRAW_PARAMETERS: + case PIPE_CAP_TGSI_PACK_HALF_FLOAT: + case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: + case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: + case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: + case PIPE_CAP_INVALIDATE_BUFFER: + case PIPE_CAP_GENERATE_MIPMAP: + case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: + case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: + case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: + case PIPE_CAP_CULL_DISTANCE: + case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: + case PIPE_CAP_TGSI_VOTE: + case PIPE_CAP_MAX_WINDOW_RECTANGLES: + case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: + case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: + case PIPE_CAP_TGSI_ARRAY_COMPONENTS: + case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: + case PIPE_CAP_TGSI_FS_FBFETCH: + case PIPE_CAP_TGSI_MUL_ZERO_WINS: + case PIPE_CAP_DOUBLES: + case PIPE_CAP_INT64: + case PIPE_CAP_INT64_DIVMOD: + case PIPE_CAP_TGSI_TEX_TXF_LZ: + case PIPE_CAP_TGSI_CLOCK: + case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: + case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: + case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; case PIPE_CAP_MAX_VIEWPORTS: return 1; + case PIPE_CAP_SHAREABLE_SHADERS: + case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: + /* manage the variants for these ourself, to avoid breaking precompile: */ + case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: + case PIPE_CAP_VERTEX_COLOR_CLAMPED: + if (is_ir3(screen)) + return 1; + return 0; + /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: if (is_ir3(screen)) return PIPE_MAX_SO_BUFFERS; return 0; case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: + case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: if (is_ir3(screen)) return 1; return 0; @@ -275,7 +354,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 11; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: - return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0; + return (is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 256 : 0; /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: @@ -284,11 +363,14 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return is_a3xx(screen) ? 1 : 0; /* Queries. */ - case PIPE_CAP_QUERY_TIME_ELAPSED: - case PIPE_CAP_QUERY_TIMESTAMP: + case PIPE_CAP_QUERY_BUFFER_OBJECT: return 0; case PIPE_CAP_OCCLUSION_QUERY: - return is_a3xx(screen) || is_a4xx(screen); + return is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen); + case PIPE_CAP_QUERY_TIMESTAMP: + case PIPE_CAP_QUERY_TIME_ELAPSED: + /* only a4xx, requires new enough kernel so we know max_freq: */ + return (screen->max_freq > 0) && is_a4xx(screen); case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MIN_TEXEL_OFFSET: @@ -315,6 +397,8 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 10; case PIPE_CAP_UMA: return 1; + case PIPE_CAP_NATIVE_FENCE_FD: + return fd_device_version(screen->dev) >= FD_VERSION_FENCE_FD; } debug_printf("unknown param %d\n", param); return 0; @@ -326,6 +410,16 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) switch (param) { case PIPE_CAPF_MAX_LINE_WIDTH: case PIPE_CAPF_MAX_LINE_WIDTH_AA: + /* NOTE: actual value is 127.0f, but this is working around a deqp + * bug.. dEQP-GLES3.functional.rasterization.primitives.lines_wide + * uses too small of a render target size, and gets confused when + * the lines start going offscreen. + * + * See: https://code.google.com/p/android/issues/detail?id=206513 + */ + if (fd_mesa_debug & FD_DBG_DEQP) + return 48.0f; + return 127.0f; case PIPE_CAPF_MAX_POINT_WIDTH: case PIPE_CAPF_MAX_POINT_WIDTH_AA: return 4092.0f; @@ -344,7 +438,8 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) } static int -fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, +fd_screen_get_shader_param(struct pipe_screen *pscreen, + enum pipe_shader_type shader, enum pipe_shader_cap param) { struct fd_screen *screen = fd_screen(pscreen); @@ -382,24 +477,28 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, * split between VS and FS. Use lower limit of 256 to * avoid getting into impossible situations: */ - return ((is_a3xx(screen) || is_a4xx(screen)) ? 4096 : 64) * sizeof(float[4]); + return ((is_a3xx(screen) || is_a4xx(screen) || is_a5xx(screen)) ? 4096 : 64) * sizeof(float[4]); case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return is_ir3(screen) ? 16 : 1; - case PIPE_SHADER_CAP_MAX_PREDS: - return 0; /* nothing uses this */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: + /* Technically this should be the same as for TEMP/CONST, since + * everything is just normal registers. This is just temporary + * hack until load_input/store_output handle arrays in a similar + * way as load_var/store_var.. + */ + return 0; case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - return 1; + /* a2xx compiler doesn't handle indirect: */ + return is_ir3(screen) ? 1 : 0; case PIPE_SHADER_CAP_SUBROUTINES: - case PIPE_SHADER_CAP_DOUBLES: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: + case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; @@ -411,14 +510,35 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return 16; case PIPE_SHADER_CAP_PREFERRED_IR: + if ((fd_mesa_debug & FD_DBG_NIR) && is_ir3(screen)) + return PIPE_SHADER_IR_NIR; return PIPE_SHADER_IR_TGSI; + case PIPE_SHADER_CAP_SUPPORTED_IRS: + return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 32; + case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS: + case PIPE_SHADER_CAP_MAX_SHADER_IMAGES: + case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: + case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: + return 0; } debug_printf("unknown shader param %d\n", param); return 0; } +static const void * +fd_get_compiler_options(struct pipe_screen *pscreen, + enum pipe_shader_ir ir, unsigned shader) +{ + struct fd_screen *screen = fd_screen(pscreen); + + if (is_ir3(screen)) + return ir3_get_compiler_options(); + + return NULL; +} + boolean fd_screen_bo_get_handle(struct pipe_screen *pscreen, struct fd_bo *bo, @@ -442,8 +562,7 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen, struct fd_bo * fd_screen_bo_from_handle(struct pipe_screen *pscreen, - struct winsys_handle *whandle, - unsigned *out_stride) + struct winsys_handle *whandle) { struct fd_screen *screen = fd_screen(pscreen); struct fd_bo *bo; @@ -464,8 +583,6 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen, return NULL; } - *out_stride = whandle->stride; - return bo; } @@ -510,6 +627,18 @@ fd_screen_create(struct fd_device *dev) } screen->device_id = val; + if (fd_pipe_get_param(screen->pipe, FD_MAX_FREQ, &val)) { + DBG("could not get gpu freq"); + /* this limits what performance related queries are + * supported but is not fatal + */ + screen->max_freq = 0; + } else { + screen->max_freq = val; + if (fd_pipe_get_param(screen->pipe, FD_TIMESTAMP, &val) == 0) + screen->has_timestamp = true; + } + if (fd_pipe_get_param(screen->pipe, FD_GPU_ID, &val)) { DBG("could not get gpu-id"); goto fail; @@ -555,17 +684,42 @@ fd_screen_create(struct fd_device *dev) fd3_screen_init(pscreen); break; case 420: + case 430: fd4_screen_init(pscreen); break; + case 530: + fd5_screen_init(pscreen); + break; default: debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); goto fail; } + if (screen->gpu_id >= 500) { + screen->gmem_alignw = 64; + screen->gmem_alignh = 32; + } else { + screen->gmem_alignw = 32; + screen->gmem_alignh = 32; + } + + /* NOTE: don't enable reordering on a2xx, since completely untested. + * Also, don't enable if we have too old of a kernel to support + * growable cmdstream buffers, since memory requirement for cmdstream + * buffers would be too much otherwise. + */ + if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)) + screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER); + + fd_bc_init(&screen->batch_cache); + + (void) mtx_init(&screen->lock, mtx_plain); + pscreen->destroy = fd_screen_destroy; pscreen->get_param = fd_screen_get_param; pscreen->get_paramf = fd_screen_get_paramf; pscreen->get_shader_param = fd_screen_get_shader_param; + pscreen->get_compiler_options = fd_get_compiler_options; fd_resource_screen_init(pscreen); fd_query_screen_init(pscreen); @@ -576,8 +730,11 @@ fd_screen_create(struct fd_device *dev) pscreen->get_timestamp = fd_screen_get_timestamp; - pscreen->fence_reference = fd_screen_fence_ref; - pscreen->fence_finish = fd_screen_fence_finish; + pscreen->fence_reference = fd_fence_ref; + pscreen->fence_finish = fd_fence_finish; + pscreen->fence_get_fd = fd_fence_get_fd; + + slab_create_parent(&screen->transfer_pool, sizeof(struct fd_transfer), 16); util_format_s3tc_init();