X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_screen.c;h=bc6ff78aa734836f74f4d3cbc19f263a3c3352b2;hb=f0ca26725e48e6d85a9e2749caaf122e7bb8d6e6;hp=228ed1868c52e246244074e8f71677132e34634d;hpb=db8886ed09d5806dae6475a76928ea8c354cd404;p=mesa.git diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 228ed1868c5..bc6ff78aa73 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -50,8 +50,8 @@ #include "freedreno_query.h" #include "freedreno_util.h" -#include "fd2_screen.h" -#include "fd3_screen.h" +#include "a2xx/fd2_screen.h" +#include "a3xx/fd3_screen.h" /* XXX this should go away */ #include "state_tracker/drm_driver.h" @@ -60,7 +60,7 @@ static const struct debug_named_value debug_options[] = { {"msgs", FD_DBG_MSGS, "Print debug messages"}, {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"}, {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"}, - {"dgmem", FD_DBG_DGMEM, "Mark all state dirty after GMEM tile pass"}, + {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, {"dscis", FD_DBG_DSCIS, "Disable scissor optimization"}, {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"}, {"dbypass", FD_DBG_DBYPASS,"Disable GMEM bypass"}, @@ -69,6 +69,7 @@ static const struct debug_named_value debug_options[] = { {"noopt", FD_DBG_NOOPT , "Disable optimization passes in compiler"}, {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizater debug messages"}, {"optdump", FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"}, + {"glsl130", FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"}, DEBUG_NAMED_VALUE_END }; @@ -76,6 +77,7 @@ DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0) int fd_mesa_debug = 0; bool fd_binning_enabled = true; +static bool glsl130 = false; static const char * fd_screen_get_name(struct pipe_screen *pscreen) @@ -143,6 +145,8 @@ tables for things that differ if the delta is not too much.. static int fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) { + struct fd_screen *screen = fd_screen(pscreen); + /* this is probably not totally correct.. but it's a start: */ switch (param) { /* Supported features (boolean caps). */ @@ -152,41 +156,48 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_TEXTURE_SHADOW_MAP: - case PIPE_CAP_TEXTURE_MIRROR_CLAMP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - case PIPE_CAP_SM3: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_SEAMLESS_CUBE_MAP: - case PIPE_CAP_PRIMITIVE_RESTART: - case PIPE_CAP_CONDITIONAL_RENDER: - case PIPE_CAP_TEXTURE_BARRIER: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: - case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_COMPUTE: - case PIPE_CAP_START_INSTANCE: - case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: - case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_USER_CONSTANT_BUFFERS: + case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: return 1; case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: + case PIPE_CAP_CONDITIONAL_RENDER: + case PIPE_CAP_TEXTURE_MULTISAMPLE: + case PIPE_CAP_TEXTURE_BARRIER: + case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + case PIPE_CAP_CUBE_MAP_ARRAY: + case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: + case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: + case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: + case PIPE_CAP_TGSI_INSTANCEID: + case PIPE_CAP_START_INSTANCE: + case PIPE_CAP_COMPUTE: return 0; + case PIPE_CAP_SM3: + case PIPE_CAP_PRIMITIVE_RESTART: + return (screen->gpu_id >= 300) ? 1 : 0; + case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; case PIPE_CAP_GLSL_FEATURE_LEVEL: - return 120; + return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120; /* Unsupported features. */ case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -194,7 +205,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DEPTH_CLIP_DISABLE: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: @@ -202,12 +213,23 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: - case PIPE_CAP_TGSI_VS_LAYER: + case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: case PIPE_CAP_TEXTURE_GATHER_SM5: - case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: + case PIPE_CAP_FAKE_SW_MSAA: + case PIPE_CAP_TEXTURE_QUERY_LOD: + case PIPE_CAP_SAMPLE_SHADING: + case PIPE_CAP_TEXTURE_GATHER_OFFSETS: + case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: + case PIPE_CAP_DRAW_INDIRECT: + case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: + case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: + case PIPE_CAP_SAMPLER_VIEW_TARGET: return 0; + case PIPE_CAP_MAX_VIEWPORTS: + return 1; + /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: @@ -218,42 +240,61 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Geometry shader output, unsupported. */ case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: + case PIPE_CAP_MAX_VERTEX_STREAMS: return 0; + case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: + return 2048; + /* Texturing. */ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: - case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return MAX_MIP_LEVELS; + case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + return 11; + case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: - return 9192; + return (screen->gpu_id >= 300) ? 256 : 0; /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: return 1; - /* Timer queries. */ + /* Queries. */ case PIPE_CAP_QUERY_TIME_ELAPSED: - case PIPE_CAP_OCCLUSION_QUERY: case PIPE_CAP_QUERY_TIMESTAMP: return 0; + case PIPE_CAP_OCCLUSION_QUERY: + return (screen->gpu_id >= 300) ? 1 : 0; + case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MIN_TEXEL_OFFSET: return -8; + case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; case PIPE_CAP_ENDIANNESS: return PIPE_ENDIAN_LITTLE; - case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: + case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: return 64; - default: - DBG("unknown param %d", param); - return 0; + case PIPE_CAP_VENDOR_ID: + return 0x5143; + case PIPE_CAP_DEVICE_ID: + return 0xFFFFFFFF; + case PIPE_CAP_ACCELERATED: + return 1; + case PIPE_CAP_VIDEO_MEMORY: + DBG("FINISHME: The value returned is incorrect\n"); + return 10; + case PIPE_CAP_UMA: + return 1; } + debug_printf("unknown param %d\n", param); + return 0; } static float @@ -268,16 +309,15 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: return 16.0f; case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: - return 16.0f; + return 15.0f; case PIPE_CAPF_GUARD_BAND_LEFT: case PIPE_CAPF_GUARD_BAND_TOP: case PIPE_CAPF_GUARD_BAND_RIGHT: case PIPE_CAPF_GUARD_BAND_BOTTOM: return 0.0f; - default: - DBG("unknown paramf %d", param); - return 0; } + debug_printf("unknown paramf %d\n", param); + return 0; } static int @@ -310,13 +350,15 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return 8; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: - return 32; + return 16; case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ - case PIPE_SHADER_CAP_MAX_ADDRS: - return 1; /* Max native address registers */ - case PIPE_SHADER_CAP_MAX_CONSTS: - return (screen->gpu_id >= 300) ? 1024 : 64; + case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: + /* NOTE: seems to be limit for a3xx is actually 512 but + * split between VS and FS. Use lower limit of 256 to + * avoid getting into impossible situations: + */ + return ((screen->gpu_id >= 300) ? 256 : 64) * sizeof(float[4]); case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return 1; case PIPE_SHADER_CAP_MAX_PREDS: @@ -329,6 +371,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: return 1; case PIPE_SHADER_CAP_SUBROUTINES: + case PIPE_SHADER_CAP_DOUBLES: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; @@ -336,16 +379,14 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, /* we should be able to support this on a3xx, but not * implemented yet: */ - return 0; + return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return 16; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; - default: - DBG("unknown shader param %d", param); - return 0; } + debug_printf("unknown shader param %d\n", param); return 0; } @@ -362,6 +403,9 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen, } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { whandle->handle = fd_bo_handle(bo); return TRUE; + } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + whandle->handle = fd_bo_dmabuf(bo); + return TRUE; } else { return FALSE; } @@ -375,12 +419,17 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen, struct fd_screen *screen = fd_screen(pscreen); struct fd_bo *bo; - if (whandle->type != DRM_API_HANDLE_TYPE_SHARED) { + if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { + bo = fd_bo_from_name(screen->dev, whandle->handle); + } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { + bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); + } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); + } else { DBG("Attempt to import unsupported handle type %d", whandle->type); return NULL; } - bo = fd_bo_from_name(screen->dev, whandle->handle); if (!bo) { DBG("ref name 0x%08x failed", whandle->handle); return NULL; @@ -403,6 +452,8 @@ fd_screen_create(struct fd_device *dev) if (fd_mesa_debug & FD_DBG_NOBIN) fd_binning_enabled = false; + glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130); + if (!screen) return NULL; @@ -435,6 +486,23 @@ fd_screen_create(struct fd_device *dev) } screen->gpu_id = val; + if (fd_pipe_get_param(screen->pipe, FD_CHIP_ID, &val)) { + DBG("could not get chip-id"); + /* older kernels may not have this property: */ + unsigned core = screen->gpu_id / 100; + unsigned major = (screen->gpu_id % 100) / 10; + unsigned minor = screen->gpu_id % 10; + unsigned patch = 0; /* assume the worst */ + val = (patch & 0xff) | ((minor & 0xff) << 8) | + ((major & 0xff) << 16) | ((core & 0xff) << 24); + } + screen->chip_id = val; + + DBG("Pipe Info:"); + DBG(" GPU-id: %d", screen->gpu_id); + DBG(" Chip-id: 0x%08x", screen->chip_id); + DBG(" GMEM size: 0x%08x", screen->gmemsize_bytes); + /* explicitly checking for GPU revisions that are known to work. This * may be overly conservative for a3xx, where spoofing the gpu_id with * the blob driver seems to generate identical cmdstream dumps. But