X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_screen.c;h=cdcc0daf2fbd8e4ff5d91660e6e1ab772826b6d9;hb=62cc003b7d2031c2321f4698bd5b97cc97261c07;hp=74cbd9676c49393361c65ebe4a5cfd4830e18352;hpb=720cfb6fe9a3dafadf3bc034008f7c5c15973866;p=mesa.git diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 74cbd9676c4..cdcc0daf2fb 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -52,6 +52,7 @@ #include "a2xx/fd2_screen.h" #include "a3xx/fd3_screen.h" +#include "a4xx/fd4_screen.h" /* XXX this should go away */ #include "state_tracker/drm_driver.h" @@ -60,16 +61,16 @@ static const struct debug_named_value debug_options[] = { {"msgs", FD_DBG_MSGS, "Print debug messages"}, {"disasm", FD_DBG_DISASM, "Dump TGSI and adreno shader disassembly"}, {"dclear", FD_DBG_DCLEAR, "Mark all state dirty after clear"}, - {"dgmem", FD_DBG_DGMEM, "Mark all state dirty after GMEM tile pass"}, - {"dscis", FD_DBG_DSCIS, "Disable scissor optimization"}, + {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, + {"noscis", FD_DBG_NOSCIS, "Disable scissor optimization"}, {"direct", FD_DBG_DIRECT, "Force inline (SS_DIRECT) state loads"}, - {"dbypass", FD_DBG_DBYPASS,"Disable GMEM bypass"}, + {"nobypass", FD_DBG_NOBYPASS, "Disable GMEM bypass"}, {"fraghalf", FD_DBG_FRAGHALF, "Use half-precision in fragment shader"}, {"nobin", FD_DBG_NOBIN, "Disable hw binning"}, - {"noopt", FD_DBG_NOOPT , "Disable optimization passes in compiler"}, - {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizater debug messages"}, + {"optmsgs", FD_DBG_OPTMSGS,"Enable optimizer debug messages"}, {"optdump", FD_DBG_OPTDUMP,"Dump shader DAG to .dot files"}, - {"glsl130", FD_DBG_GLSL130,"Temporary flag to enable GLSL 130 on a3xx+"}, + {"glsl120", FD_DBG_GLSL120,"Temporary flag to force GLSL 120 (rather than 130) on a3xx+"}, + {"nocp", FD_DBG_NOCP, "Disable copy-propagation"}, DEBUG_NAMED_VALUE_END }; @@ -77,7 +78,7 @@ DEBUG_GET_ONCE_FLAGS_OPTION(fd_mesa_debug, "FD_MESA_DEBUG", debug_options, 0) int fd_mesa_debug = 0; bool fd_binning_enabled = true; -static bool glsl130 = false; +static bool glsl120 = false; static const char * fd_screen_get_name(struct pipe_screen *pscreen) @@ -101,29 +102,6 @@ fd_screen_get_timestamp(struct pipe_screen *pscreen) return cpu_time + fd_screen(pscreen)->cpu_gpu_time_delta; } -static void -fd_screen_fence_ref(struct pipe_screen *pscreen, - struct pipe_fence_handle **ptr, - struct pipe_fence_handle *pfence) -{ - fd_fence_ref(fd_fence(pfence), (struct fd_fence **)ptr); -} - -static boolean -fd_screen_fence_signalled(struct pipe_screen *screen, - struct pipe_fence_handle *pfence) -{ - return fd_fence_signalled(fd_fence(pfence)); -} - -static boolean -fd_screen_fence_finish(struct pipe_screen *screen, - struct pipe_fence_handle *pfence, - uint64_t timeout) -{ - return fd_fence_wait(fd_fence(pfence)); -} - static void fd_screen_destroy(struct pipe_screen *pscreen) { @@ -156,25 +134,20 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_TEXTURE_SHADOW_MAP: - case PIPE_CAP_TEXTURE_MIRROR_CLAMP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: - case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: - case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_COMPUTE: - case PIPE_CAP_START_INSTANCE: - case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: + case PIPE_CAP_VERTEXID_NOBASE: return 1; case PIPE_CAP_SHADER_STENCIL_EXPORT: @@ -183,17 +156,29 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CONDITIONAL_RENDER: case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_TEXTURE_BARRIER: - case PIPE_CAP_SM3: + case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + case PIPE_CAP_CUBE_MAP_ARRAY: + case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: + case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: + case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: + case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: + case PIPE_CAP_START_INSTANCE: + case PIPE_CAP_COMPUTE: return 0; + case PIPE_CAP_SM3: case PIPE_CAP_PRIMITIVE_RESTART: - return (screen->gpu_id >= 300) ? 1 : 0; + case PIPE_CAP_TGSI_INSTANCEID: + case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: + return is_a3xx(screen) || is_a4xx(screen); case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: return 256; case PIPE_CAP_GLSL_FEATURE_LEVEL: - return ((screen->gpu_id >= 300) && glsl130) ? 130 : 120; + if (glsl120) + return 120; + return (is_a3xx(screen) || is_a4xx(screen)) ? 130 : 120; /* Unsupported features. */ case PIPE_CAP_INDEP_BLEND_ENABLE: @@ -201,7 +186,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DEPTH_CLIP_DISABLE: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: @@ -220,8 +205,16 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DRAW_INDIRECT: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: + case PIPE_CAP_SAMPLER_VIEW_TARGET: + case PIPE_CAP_CLIP_HALFZ: + case PIPE_CAP_POLYGON_OFFSET_CLAMP: + case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: + case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return 0; + case PIPE_CAP_MAX_VIEWPORTS: + return 1; + /* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: @@ -240,11 +233,13 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Texturing. */ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: - case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: return MAX_MIP_LEVELS; + case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: + return 11; + case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: - return 0; /* TODO: a3xx+ should support (required in gles3) */ + return (is_a3xx(screen) || is_a4xx(screen)) ? 256 : 0; /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: @@ -255,7 +250,10 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_QUERY_TIMESTAMP: return 0; case PIPE_CAP_OCCLUSION_QUERY: - return (screen->gpu_id >= 300) ? 1 : 0; + /* TODO still missing on a4xx, but we lie to get gl2.. + * it's not a feature, it's a bug! + */ + return is_a3xx(screen) || is_a4xx(screen); case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: case PIPE_CAP_MIN_TEXEL_OFFSET: @@ -282,11 +280,9 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 10; case PIPE_CAP_UMA: return 1; - - default: - DBG("unknown param %d", param); - return 0; } + debug_printf("unknown param %d\n", param); + return 0; } static float @@ -301,16 +297,15 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: return 16.0f; case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: - return 16.0f; + return 15.0f; case PIPE_CAPF_GUARD_BAND_LEFT: case PIPE_CAPF_GUARD_BAND_TOP: case PIPE_CAPF_GUARD_BAND_RIGHT: case PIPE_CAPF_GUARD_BAND_BOTTOM: return 0.0f; - default: - DBG("unknown paramf %d", param); - return 0; } + debug_printf("unknown paramf %d\n", param); + return 0; } static int @@ -343,11 +338,16 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return 8; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: + case PIPE_SHADER_CAP_MAX_OUTPUTS: return 16; case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: - return ((screen->gpu_id >= 300) ? 1024 : 64) * sizeof(float[4]); + /* NOTE: seems to be limit for a3xx is actually 512 but + * split between VS and FS. Use lower limit of 256 to + * avoid getting into impossible situations: + */ + return ((is_a3xx(screen) || is_a4xx(screen)) ? 256 : 64) * sizeof(float[4]); case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: return 1; case PIPE_SHADER_CAP_MAX_PREDS: @@ -360,23 +360,24 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: return 1; case PIPE_SHADER_CAP_SUBROUTINES: + case PIPE_SHADER_CAP_DOUBLES: + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: return 0; case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: return 1; case PIPE_SHADER_CAP_INTEGERS: - /* we should be able to support this on a3xx, but not - * implemented yet: - */ - return ((screen->gpu_id >= 300) && glsl130) ? 1 : 0; + if (glsl120) + return 0; + return (is_a3xx(screen) || is_a4xx(screen)) ? 1 : 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return 16; case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_TGSI; - default: - DBG("unknown shader param %d", param); - return 0; } + debug_printf("unknown shader param %d\n", param); return 0; } @@ -393,6 +394,9 @@ fd_screen_bo_get_handle(struct pipe_screen *pscreen, } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { whandle->handle = fd_bo_handle(bo); return TRUE; + } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + whandle->handle = fd_bo_dmabuf(bo); + return TRUE; } else { return FALSE; } @@ -406,12 +410,17 @@ fd_screen_bo_from_handle(struct pipe_screen *pscreen, struct fd_screen *screen = fd_screen(pscreen); struct fd_bo *bo; - if (whandle->type != DRM_API_HANDLE_TYPE_SHARED) { + if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) { + bo = fd_bo_from_name(screen->dev, whandle->handle); + } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) { + bo = fd_bo_from_handle(screen->dev, whandle->handle, 0); + } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) { + bo = fd_bo_from_dmabuf(screen->dev, whandle->handle); + } else { DBG("Attempt to import unsupported handle type %d", whandle->type); return NULL; } - bo = fd_bo_from_name(screen->dev, whandle->handle); if (!bo) { DBG("ref name 0x%08x failed", whandle->handle); return NULL; @@ -434,7 +443,7 @@ fd_screen_create(struct fd_device *dev) if (fd_mesa_debug & FD_DBG_NOBIN) fd_binning_enabled = false; - glsl130 = !!(fd_mesa_debug & FD_DBG_GLSL130); + glsl120 = !!(fd_mesa_debug & FD_DBG_GLSL120); if (!screen) return NULL; @@ -493,7 +502,7 @@ fd_screen_create(struct fd_device *dev) * before enabling: * * If you have a different adreno version, feel free to add it to one - * of the two cases below and see what happens. And if it works, please + * of the cases below and see what happens. And if it works, please * send a patch ;-) */ switch (screen->gpu_id) { @@ -504,6 +513,9 @@ fd_screen_create(struct fd_device *dev) case 330: fd3_screen_init(pscreen); break; + case 420: + fd4_screen_init(pscreen); + break; default: debug_printf("unsupported GPU: a%03d\n", screen->gpu_id); goto fail;