X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Ffreedreno%2Ffreedreno_util.h;h=d6c80f2f29bddac80e0dd8d4b8bbec154ec3cb0b;hb=8cdc6c1e4b632cea6934836ca4962a555a1172c6;hp=e03f37dd627e38f2414b589f5b3b9a49715590bd;hpb=2482153d52f0ff27513b63a5aebd688a74beb91a;p=mesa.git diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h index e03f37dd627..d6c80f2f29b 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.h +++ b/src/gallium/drivers/freedreno/freedreno_util.h @@ -61,30 +61,36 @@ enum adreno_stencil_op fd_stencil_op(unsigned op); #define MAX_RENDER_TARGETS A6XX_MAX_RENDER_TARGETS -#define FD_DBG_MSGS 0x0001 -#define FD_DBG_DISASM 0x0002 -#define FD_DBG_DCLEAR 0x0004 -#define FD_DBG_DDRAW 0x0008 -#define FD_DBG_NOSCIS 0x0010 -#define FD_DBG_DIRECT 0x0020 -#define FD_DBG_NOBYPASS 0x0040 -#define FD_DBG_FRAGHALF 0x0080 -#define FD_DBG_NOBIN 0x0100 -/* unused 0x0200 */ -#define FD_DBG_GLSL120 0x0400 -#define FD_DBG_SHADERDB 0x0800 -#define FD_DBG_FLUSH 0x1000 -#define FD_DBG_DEQP 0x2000 -#define FD_DBG_INORDER 0x4000 -#define FD_DBG_BSTAT 0x8000 -#define FD_DBG_NOGROW 0x10000 -#define FD_DBG_LRZ 0x20000 -#define FD_DBG_NOINDR 0x40000 -#define FD_DBG_NOBLIT 0x80000 -#define FD_DBG_HIPRIO 0x100000 -#define FD_DBG_TTILE 0x200000 -#define FD_DBG_PERFC 0x400000 -#define FD_DBG_SOFTPIN 0x800000 +enum fd_debug_flag { + FD_DBG_MSGS = BITFIELD_BIT(0), + FD_DBG_DISASM = BITFIELD_BIT(1), + FD_DBG_DCLEAR = BITFIELD_BIT(2), + FD_DBG_DDRAW = BITFIELD_BIT(3), + FD_DBG_NOSCIS = BITFIELD_BIT(4), + FD_DBG_DIRECT = BITFIELD_BIT(5), + FD_DBG_NOBYPASS = BITFIELD_BIT(6), + FD_DBG_FRAGHALF = BITFIELD_BIT(7), + FD_DBG_NOBIN = BITFIELD_BIT(8), + FD_DBG_NOGMEM = BITFIELD_BIT(9), + FD_DBG_GLSL120 = BITFIELD_BIT(10), + FD_DBG_SHADERDB = BITFIELD_BIT(11), + FD_DBG_FLUSH = BITFIELD_BIT(12), + FD_DBG_DEQP = BITFIELD_BIT(13), + FD_DBG_INORDER = BITFIELD_BIT(14), + FD_DBG_BSTAT = BITFIELD_BIT(15), + FD_DBG_NOGROW = BITFIELD_BIT(16), + FD_DBG_LRZ = BITFIELD_BIT(17), + FD_DBG_NOINDR = BITFIELD_BIT(18), + FD_DBG_NOBLIT = BITFIELD_BIT(19), + FD_DBG_HIPRIO = BITFIELD_BIT(20), + FD_DBG_TTILE = BITFIELD_BIT(21), + FD_DBG_PERFC = BITFIELD_BIT(22), + FD_DBG_NOUBWC = BITFIELD_BIT(23), + FD_DBG_NOLRZ = BITFIELD_BIT(24), + FD_DBG_NOTILE = BITFIELD_BIT(25), + FD_DBG_LAYOUT = BITFIELD_BIT(26), + FD_DBG_NOFP16 = BITFIELD_BIT(27), +}; extern int fd_mesa_debug; extern bool fd_binning_enabled; @@ -114,15 +120,19 @@ static inline uint32_t DRAW(enum pc_di_primtype prim_type, } static inline uint32_t DRAW_A20X(enum pc_di_primtype prim_type, + enum pc_di_face_cull_sel faceness_cull_select, enum pc_di_src_sel source_select, enum pc_di_index_size index_size, - enum pc_di_vis_cull_mode vis_cull_mode, + bool pre_fetch_cull_enable, + bool grp_cull_enable, uint16_t count) { return (prim_type << 0) | (source_select << 6) | + (faceness_cull_select << 8) | ((index_size & 1) << 11) | ((index_size >> 1) << 13) | - (vis_cull_mode << 9) | + (pre_fetch_cull_enable << 14) | + (grp_cull_enable << 15) | (count << 16); } @@ -194,6 +204,18 @@ fd_half_precision(struct pipe_framebuffer_state *pfb) return true; } +/* Note sure if this is same on all gens, but seems to be same on the later + * gen's + */ +static inline unsigned +fd_calc_guardband(unsigned x) +{ + float l = log2(x); + if (l <= 8) + return 511; + return 511 - ((l - 8) * 65); +} + #define LOG_DWORDS 0 static inline void emit_marker(struct fd_ringbuffer *ring, int scratch_idx); @@ -228,8 +250,8 @@ OUT_RINGP(struct fd_ringbuffer *ring, uint32_t data, */ static inline void -OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo, - uint32_t offset, uint64_t or, int32_t shift) +__out_reloc(struct fd_ringbuffer *ring, struct fd_bo *bo, + uint32_t offset, uint64_t or, int32_t shift, uint32_t flags) { if (LOG_DWORDS) { DBG("ring[%p]: OUT_RELOC %04x: %p+%u << %d", ring, @@ -238,7 +260,7 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo, debug_assert(offset < fd_bo_size(bo)); fd_ringbuffer_reloc(ring, &(struct fd_reloc){ .bo = bo, - .flags = FD_RELOC_READ, + .flags = flags, .offset = offset, .or = or, .shift = shift, @@ -246,23 +268,25 @@ OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo, }); } +static inline void +OUT_RELOC(struct fd_ringbuffer *ring, struct fd_bo *bo, + uint32_t offset, uint64_t or, int32_t shift) +{ + __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ); +} + static inline void OUT_RELOCW(struct fd_ringbuffer *ring, struct fd_bo *bo, uint32_t offset, uint64_t or, int32_t shift) { - if (LOG_DWORDS) { - DBG("ring[%p]: OUT_RELOCW %04x: %p+%u << %d", ring, - (uint32_t)(ring->cur - ring->start), bo, offset, shift); - } - debug_assert(offset < fd_bo_size(bo)); - fd_ringbuffer_reloc(ring, &(struct fd_reloc){ - .bo = bo, - .flags = FD_RELOC_READ | FD_RELOC_WRITE, - .offset = offset, - .or = or, - .shift = shift, - .orhi = or >> 32, - }); + __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_WRITE); +} + +static inline void +OUT_RELOCD(struct fd_ringbuffer *ring, struct fd_bo *bo, + uint32_t offset, uint64_t or, int32_t shift) +{ + __out_reloc(ring, bo, offset, or, shift, FD_RELOC_READ | FD_RELOC_DUMP); } static inline void @@ -441,9 +465,11 @@ fd_msaa_samples(unsigned samples) switch (samples) { default: debug_assert(0); + case 0: case 1: return MSAA_ONE; case 2: return MSAA_TWO; case 4: return MSAA_FOUR; + case 8: return MSAA_EIGHT; } } @@ -460,6 +486,7 @@ fd4_stage2shadersb(gl_shader_stage type) case MESA_SHADER_FRAGMENT: return SB4_FS_SHADER; case MESA_SHADER_COMPUTE: + case MESA_SHADER_KERNEL: return SB4_CS_SHADER; default: unreachable("bad shader type"); @@ -467,4 +494,17 @@ fd4_stage2shadersb(gl_shader_stage type) } } +static inline enum a4xx_index_size +fd4_size2indextype(unsigned index_size) +{ + switch (index_size) { + case 1: return INDEX4_SIZE_8_BIT; + case 2: return INDEX4_SIZE_16_BIT; + case 4: return INDEX4_SIZE_32_BIT; + } + DBG("unsupported index size: %d", index_size); + assert(0); + return INDEX4_SIZE_32_BIT; +} + #endif /* FREEDRENO_UTIL_H_ */