X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fi915%2Fi915_clear.c;h=b17707f3f64ab13a776e2db393f737fbb6048d9a;hb=877128505431adaf817dc8069172ebe4a1cdf5d8;hp=7341156310da648781d94fda4501e5bce3e59b6b;hpb=866f9b18c68ede63c00917ec9c3dae3524ca8826;p=mesa.git diff --git a/src/gallium/drivers/i915/i915_clear.c b/src/gallium/drivers/i915/i915_clear.c index 7341156310d..b17707f3f64 100644 --- a/src/gallium/drivers/i915/i915_clear.c +++ b/src/gallium/drivers/i915/i915_clear.c @@ -1,6 +1,6 @@ /************************************************************************** * - * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas. + * Copyright 2007 VMware, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining a @@ -18,7 +18,7 @@ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. @@ -74,7 +74,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, } /* correctly swizzle clear value */ - if (i915->current.need_target_fixup) + if (i915->current.target_fixup_format) util_pack_color(color->f, cbuf->format, &u_color); else util_pack_color(color->f, PIPE_FORMAT_B8G8R8A8_UNORM, &u_color); @@ -95,17 +95,16 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, if (buffers & PIPE_CLEAR_STENCIL || depth_tex->b.b.format != PIPE_FORMAT_Z24_UNORM_S8_UINT) { clear_params |= CLEARPARAM_WRITE_STENCIL; - clear_stencil = packed_z_stencil & 0xff; - clear_depth = packed_z_stencil; - } else - clear_depth = packed_z_stencil & 0xffffff00; + clear_stencil = packed_z_stencil >> 24; + } + clear_depth = packed_z_stencil & 0xffffff; depth_clear_bbp = 32; } else { clear_depth = (packed_z_stencil & 0xffff) | (packed_z_stencil << 16); depth_clear_bbp = 16; } - } else if (buffers & PIPE_CLEAR_DEPTH) { + } else if (buffers & PIPE_CLEAR_STENCIL) { struct pipe_surface *zbuf = i915->framebuffer.zsbuf; clear_params |= CLEARPARAM_WRITE_STENCIL; @@ -114,7 +113,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, packed_z_stencil = util_pack_z_stencil(depth_tex->b.b.format, depth, stencil); depth_clear_bbp = 32; - clear_stencil = packed_z_stencil & 0xff; + clear_stencil = packed_z_stencil >> 24; } /* hw can't fastclear both depth and color if their bbp mismatch. */ @@ -124,7 +123,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, i915_emit_hardware_state(i915); if (!BEGIN_BATCH(1 + 2*(7 + 7))) { - FLUSH_BATCH(NULL); + FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); i915_emit_hardware_state(i915); i915->vbo_flushed = 1; @@ -175,7 +174,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, i915_emit_hardware_state(i915); if (!BEGIN_BATCH(1 + 7 + 7)) { - FLUSH_BATCH(NULL); + FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); i915_emit_hardware_state(i915); i915->vbo_flushed = 1; @@ -207,7 +206,7 @@ i915_clear_emit(struct pipe_context *pipe, unsigned buffers, /* Flush after clear, its expected to be a costly operation. * This is not required, just a heuristic, but without the flush we'd need to * clobber the SCISSOR_ENABLE dynamic state. */ - FLUSH_BATCH(NULL); + FLUSH_BATCH(NULL, I915_FLUSH_ASYNC); i915->last_fired_vertices = i915->fired_vertices; i915->fired_vertices = 0;