X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Filo%2Filo_3d.c;h=30686d6075f1029666ae010e20a9c758bb176945;hb=26fefae9a715b5498b5ffcd835556b02e4f0c68b;hp=980bdb4451e5ed1747a3841a9ffcaa25bce77023;hpb=bbb30398e58440bf542427a408810cf0e31297b5;p=mesa.git diff --git a/src/gallium/drivers/ilo/ilo_3d.c b/src/gallium/drivers/ilo/ilo_3d.c index 980bdb4451e..30686d6075f 100644 --- a/src/gallium/drivers/ilo/ilo_3d.c +++ b/src/gallium/drivers/ilo/ilo_3d.c @@ -25,9 +25,11 @@ * Chia-I Wu */ +#include "util/u_prim.h" #include "intel_winsys.h" #include "ilo_3d_pipeline.h" +#include "ilo_blit.h" #include "ilo_context.h" #include "ilo_cp.h" #include "ilo_query.h" @@ -45,11 +47,10 @@ process_query_for_occlusion_counter(struct ilo_3d *hw3d, /* in pairs */ assert(q->reg_read % 2 == 0); - q->bo->map(q->bo, false); - vals = q->bo->get_virtual(q->bo); + vals = intel_bo_map(q->bo, false); for (i = 1; i < q->reg_read; i += 2) depth_count += vals[i] - vals[i - 1]; - q->bo->unmap(q->bo); + intel_bo_unmap(q->bo); /* accumulate so that the query can be resumed if wanted */ q->data.u64 += depth_count; @@ -70,10 +71,9 @@ process_query_for_timestamp(struct ilo_3d *hw3d, struct ilo_query *q) assert(q->reg_read == 1); - q->bo->map(q->bo, false); - vals = q->bo->get_virtual(q->bo); + vals = intel_bo_map(q->bo, false); timestamp = vals[0]; - q->bo->unmap(q->bo); + intel_bo_unmap(q->bo); q->data.u64 = timestamp_to_ns(timestamp); q->reg_read = 0; @@ -88,19 +88,53 @@ process_query_for_time_elapsed(struct ilo_3d *hw3d, struct ilo_query *q) /* in pairs */ assert(q->reg_read % 2 == 0); - q->bo->map(q->bo, false); - vals = q->bo->get_virtual(q->bo); + vals = intel_bo_map(q->bo, false); for (i = 1; i < q->reg_read; i += 2) elapsed += vals[i] - vals[i - 1]; - q->bo->unmap(q->bo); + intel_bo_unmap(q->bo); /* accumulate so that the query can be resumed if wanted */ q->data.u64 += timestamp_to_ns(elapsed); q->reg_read = 0; } +static void +process_query_for_pipeline_statistics(struct ilo_3d *hw3d, + struct ilo_query *q) +{ + const uint64_t *vals; + int i; + + assert(q->reg_read % 22 == 0); + + vals = intel_bo_map(q->bo, false); + + for (i = 0; i < q->reg_read; i += 22) { + struct pipe_query_data_pipeline_statistics *stats = + &q->data.pipeline_statistics; + const uint64_t *begin = vals + i; + const uint64_t *end = begin + 11; + + stats->ia_vertices += end[0] - begin[0]; + stats->ia_primitives += end[1] - begin[1]; + stats->vs_invocations += end[2] - begin[2]; + stats->gs_invocations += end[3] - begin[3]; + stats->gs_primitives += end[4] - begin[4]; + stats->c_invocations += end[5] - begin[5]; + stats->c_primitives += end[6] - begin[6]; + stats->ps_invocations += end[7] - begin[7]; + stats->hs_invocations += end[8] - begin[8]; + stats->ds_invocations += end[9] - begin[9]; + stats->cs_invocations += end[10] - begin[10]; + } + + intel_bo_unmap(q->bo); + + q->reg_read = 0; +} + static void ilo_3d_resume_queries(struct ilo_3d *hw3d) { @@ -125,6 +159,17 @@ ilo_3d_resume_queries(struct ilo_3d *hw3d) ilo_3d_pipeline_emit_write_timestamp(hw3d->pipeline, q->bo, q->reg_read++); } + + /* resume pipeline statistics queries */ + LIST_FOR_EACH_ENTRY(q, &hw3d->pipeline_statistics_queries, list) { + /* accumulate the result if the bo is alreay full */ + if (q->reg_read >= q->reg_total) + process_query_for_pipeline_statistics(hw3d, q); + + ilo_3d_pipeline_emit_write_statistics(hw3d->pipeline, + q->bo, q->reg_read); + q->reg_read += 11; + } } static void @@ -145,23 +190,36 @@ ilo_3d_pause_queries(struct ilo_3d *hw3d) ilo_3d_pipeline_emit_write_timestamp(hw3d->pipeline, q->bo, q->reg_read++); } + + /* pause pipeline statistics queries */ + LIST_FOR_EACH_ENTRY(q, &hw3d->pipeline_statistics_queries, list) { + assert(q->reg_read < q->reg_total); + ilo_3d_pipeline_emit_write_statistics(hw3d->pipeline, + q->bo, q->reg_read); + q->reg_read += 11; + } } static void -ilo_3d_release_render_ring(struct ilo_cp *cp, void *data) +ilo_3d_own_render_ring(struct ilo_3d *hw3d) { - struct ilo_3d *hw3d = data; - - ilo_3d_pause_queries(hw3d); + ilo_cp_set_owner(hw3d->cp, INTEL_RING_RENDER, &hw3d->owner); } static void -ilo_3d_own_render_ring(struct ilo_3d *hw3d) +ilo_3d_reserve_for_query(struct ilo_3d *hw3d, struct ilo_query *q, + enum ilo_3d_pipeline_action act) { - ilo_cp_set_ring(hw3d->cp, ILO_CP_RING_RENDER); + q->reg_cmd_size = ilo_3d_pipeline_estimate_size(hw3d->pipeline, act, NULL); - if (ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve)) - ilo_3d_resume_queries(hw3d); + /* XXX we should check the aperture size */ + if (ilo_cp_space(hw3d->cp) < q->reg_cmd_size * 2) { + ilo_cp_submit(hw3d->cp, "out of space"); + assert(ilo_cp_space(hw3d->cp) >= q->reg_cmd_size * 2); + } + + /* reserve space for pausing the query */ + hw3d->owner.reserve += q->reg_cmd_size; } /** @@ -176,16 +234,10 @@ ilo_3d_begin_query(struct ilo_context *ilo, struct ilo_query *q) switch (q->type) { case PIPE_QUERY_OCCLUSION_COUNTER: - /* reserve some space for pausing the query */ - q->reg_cmd_size = ilo_3d_pipeline_estimate_size(hw3d->pipeline, - ILO_3D_PIPELINE_WRITE_DEPTH_COUNT, NULL); - hw3d->owner_reserve += q->reg_cmd_size; - ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve); - + ilo_3d_reserve_for_query(hw3d, q, ILO_3D_PIPELINE_WRITE_DEPTH_COUNT); q->data.u64 = 0; if (ilo_query_alloc_bo(q, 2, -1, hw3d->cp->winsys)) { - /* XXX we should check the aperture size */ ilo_3d_pipeline_emit_write_depth_count(hw3d->pipeline, q->bo, q->reg_read++); @@ -196,16 +248,10 @@ ilo_3d_begin_query(struct ilo_context *ilo, struct ilo_query *q) /* nop */ break; case PIPE_QUERY_TIME_ELAPSED: - /* reserve some space for pausing the query */ - q->reg_cmd_size = ilo_3d_pipeline_estimate_size(hw3d->pipeline, - ILO_3D_PIPELINE_WRITE_TIMESTAMP, NULL); - hw3d->owner_reserve += q->reg_cmd_size; - ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve); - + ilo_3d_reserve_for_query(hw3d, q, ILO_3D_PIPELINE_WRITE_TIMESTAMP); q->data.u64 = 0; if (ilo_query_alloc_bo(q, 2, -1, hw3d->cp->winsys)) { - /* XXX we should check the aperture size */ ilo_3d_pipeline_emit_write_timestamp(hw3d->pipeline, q->bo, q->reg_read++); @@ -220,6 +266,19 @@ ilo_3d_begin_query(struct ilo_context *ilo, struct ilo_query *q) q->data.u64 = 0; list_add(&q->list, &hw3d->prim_emitted_queries); break; + case PIPE_QUERY_PIPELINE_STATISTICS: + ilo_3d_reserve_for_query(hw3d, q, ILO_3D_PIPELINE_WRITE_STATISTICS); + memset(&q->data.pipeline_statistics, 0, + sizeof(q->data.pipeline_statistics)); + + if (ilo_query_alloc_bo(q, 11 * 2, -1, hw3d->cp->winsys)) { + ilo_3d_pipeline_emit_write_statistics(hw3d->pipeline, + q->bo, q->reg_read); + q->reg_read += 11; + + list_add(&q->list, &hw3d->pipeline_statistics_queries); + } + break; default: assert(!"unknown query type"); break; @@ -241,8 +300,9 @@ ilo_3d_end_query(struct ilo_context *ilo, struct ilo_query *q) list_del(&q->list); assert(q->reg_read < q->reg_total); - hw3d->owner_reserve -= q->reg_cmd_size; - ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve); + assert(hw3d->owner.reserve >= q->reg_cmd_size); + hw3d->owner.reserve -= q->reg_cmd_size; + ilo_3d_pipeline_emit_write_depth_count(hw3d->pipeline, q->bo, q->reg_read++); break; @@ -258,8 +318,9 @@ ilo_3d_end_query(struct ilo_context *ilo, struct ilo_query *q) list_del(&q->list); assert(q->reg_read < q->reg_total); - hw3d->owner_reserve -= q->reg_cmd_size; - ilo_cp_set_owner(hw3d->cp, &hw3d->owner, hw3d->owner_reserve); + assert(hw3d->owner.reserve >= q->reg_cmd_size); + hw3d->owner.reserve -= q->reg_cmd_size; + ilo_3d_pipeline_emit_write_timestamp(hw3d->pipeline, q->bo, q->reg_read++); break; @@ -267,6 +328,17 @@ ilo_3d_end_query(struct ilo_context *ilo, struct ilo_query *q) case PIPE_QUERY_PRIMITIVES_EMITTED: list_del(&q->list); break; + case PIPE_QUERY_PIPELINE_STATISTICS: + list_del(&q->list); + + assert(q->reg_read + 11 <= q->reg_total); + assert(hw3d->owner.reserve >= q->reg_cmd_size); + hw3d->owner.reserve -= q->reg_cmd_size; + + ilo_3d_pipeline_emit_write_statistics(hw3d->pipeline, + q->bo, q->reg_read); + q->reg_read += 11; + break; default: assert(!"unknown query type"); break; @@ -297,6 +369,10 @@ ilo_3d_process_query(struct ilo_context *ilo, struct ilo_query *q) case PIPE_QUERY_PRIMITIVES_GENERATED: case PIPE_QUERY_PRIMITIVES_EMITTED: break; + case PIPE_QUERY_PIPELINE_STATISTICS: + if (q->bo) + process_query_for_pipeline_statistics(hw3d, q); + break; default: assert(!"unknown query type"); break; @@ -307,23 +383,41 @@ ilo_3d_process_query(struct ilo_context *ilo, struct ilo_query *q) * Hook for CP new-batch. */ void -ilo_3d_cp_flushed(struct ilo_3d *hw3d) +ilo_3d_cp_submitted(struct ilo_3d *hw3d) { - if (ilo_debug & ILO_DEBUG_3D) - ilo_3d_pipeline_dump(hw3d->pipeline); - /* invalidate the pipeline */ ilo_3d_pipeline_invalidate(hw3d->pipeline, ILO_3D_PIPELINE_INVALIDATE_BATCH_BO | - ILO_3D_PIPELINE_INVALIDATE_STATE_BO); - if (!hw3d->cp->render_ctx) { - ilo_3d_pipeline_invalidate(hw3d->pipeline, - ILO_3D_PIPELINE_INVALIDATE_HW); - } + ILO_3D_PIPELINE_INVALIDATE_STATE_BO | + ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO); hw3d->new_batch = true; } +static void +ilo_3d_own_cp(struct ilo_cp *cp, void *data) +{ + struct ilo_3d *hw3d = data; + + /* multiply by 2 for both resuming and pausing */ + if (ilo_cp_space(hw3d->cp) < hw3d->owner.reserve * 2) { + ilo_cp_submit(hw3d->cp, "out of space"); + assert(ilo_cp_space(hw3d->cp) >= hw3d->owner.reserve * 2); + } + + ilo_3d_resume_queries(hw3d); + + assert(ilo_cp_space(hw3d->cp) >= hw3d->owner.reserve); +} + +static void +ilo_3d_release_cp(struct ilo_cp *cp, void *data) +{ + struct ilo_3d *hw3d = data; + + ilo_3d_pause_queries(hw3d); +} + /** * Create a 3D context. */ @@ -337,8 +431,10 @@ ilo_3d_create(struct ilo_cp *cp, const struct ilo_dev_info *dev) return NULL; hw3d->cp = cp; - hw3d->owner.release_callback = ilo_3d_release_render_ring; - hw3d->owner.release_data = hw3d; + hw3d->owner.own = ilo_3d_own_cp; + hw3d->owner.release = ilo_3d_release_cp; + hw3d->owner.data = hw3d; + hw3d->owner.reserve = 0; hw3d->new_batch = true; @@ -346,6 +442,7 @@ ilo_3d_create(struct ilo_cp *cp, const struct ilo_dev_info *dev) list_inithead(&hw3d->time_elapsed_queries); list_inithead(&hw3d->prim_generated_queries); list_inithead(&hw3d->prim_emitted_queries); + list_inithead(&hw3d->pipeline_statistics_queries); hw3d->pipeline = ilo_3d_pipeline_create(cp, dev); if (!hw3d->pipeline) { @@ -367,11 +464,10 @@ ilo_3d_destroy(struct ilo_3d *hw3d) } static bool -draw_vbo(struct ilo_3d *hw3d, const struct ilo_context *ilo, - const struct pipe_draw_info *info, +draw_vbo(struct ilo_3d *hw3d, const struct ilo_state_vector *vec, int *prim_generated, int *prim_emitted) { - bool need_flush; + bool need_flush = false; int max_len; ilo_3d_own_render_ring(hw3d); @@ -383,22 +479,22 @@ draw_vbo(struct ilo_3d *hw3d, const struct ilo_context *ilo, * happens in the middle of a batch buffer, we need to insert manual * flushes. */ - need_flush = (ilo->dirty & ILO_DIRTY_FRAMEBUFFER); + need_flush = (vec->dirty & ILO_DIRTY_FB); /* same to SO target changes */ - need_flush |= (ilo->dirty & ILO_DIRTY_STREAM_OUTPUT_TARGETS); + need_flush |= (vec->dirty & ILO_DIRTY_SO); } /* make sure there is enough room first */ max_len = ilo_3d_pipeline_estimate_size(hw3d->pipeline, - ILO_3D_PIPELINE_DRAW, ilo); + ILO_3D_PIPELINE_DRAW, vec); if (need_flush) { max_len += ilo_3d_pipeline_estimate_size(hw3d->pipeline, ILO_3D_PIPELINE_FLUSH, NULL); } if (max_len > ilo_cp_space(hw3d->cp)) { - ilo_cp_flush(hw3d->cp); + ilo_cp_submit(hw3d->cp, "out of space"); need_flush = false; assert(max_len <= ilo_cp_space(hw3d->cp)); } @@ -406,7 +502,7 @@ draw_vbo(struct ilo_3d *hw3d, const struct ilo_context *ilo, if (need_flush) ilo_3d_pipeline_emit_flush(hw3d->pipeline); - return ilo_3d_pipeline_emit_draw(hw3d->pipeline, ilo, info, + return ilo_3d_pipeline_emit_draw(hw3d->pipeline, vec, prim_generated, prim_emitted); } @@ -422,9 +518,10 @@ update_prim_count(struct ilo_3d *hw3d, int generated, int emitted) q->data.u64 += emitted; } -static bool -pass_render_condition(struct ilo_3d *hw3d, struct pipe_context *pipe) +bool +ilo_3d_pass_render_condition(struct ilo_context *ilo) { + struct ilo_3d *hw3d = ilo->hw3d; uint64_t result; bool wait; @@ -443,13 +540,50 @@ pass_render_condition(struct ilo_3d *hw3d, struct pipe_context *pipe) break; } - if (pipe->get_query_result(pipe, hw3d->render_condition.query, - wait, (union pipe_query_result *) &result)) { - return (result > 0); - } - else { + if (ilo->base.get_query_result(&ilo->base, hw3d->render_condition.query, + wait, (union pipe_query_result *) &result)) + return (!result == hw3d->render_condition.cond); + else return true; - } +} + +void +ilo_3d_draw_rectlist(struct ilo_3d *hw3d, const struct ilo_blitter *blitter) +{ + ilo_3d_own_render_ring(hw3d); + + /* + * From the Sandy Bridge PRM, volume 2 part 1, page 313: + * + * "If other rendering operations have preceded this clear, a + * PIPE_CONTROL with write cache flush enabled and Z-inhibit + * disabled must be issued before the rectangle primitive used for + * the depth buffer clear operation." + * + * From the Sandy Bridge PRM, volume 2 part 1, page 314: + * + * "Depth buffer clear pass must be followed by a PIPE_CONTROL + * command with DEPTH_STALL bit set and Then followed by Depth + * FLUSH" + * + * But the pipeline has to be flushed both before and after not only + * because of these workarounds. We need them for reasons such as + * + * - we may sample from a texture that was rendered to + * - we may sample from the fb shortly after + * + * Skip checking blitter->op and do the flushes. + * + * XXX need space check + */ + if (!hw3d->new_batch) + ilo_3d_pipeline_emit_flush(hw3d->pipeline); + + ilo_3d_pipeline_emit_rectlist(hw3d->pipeline, blitter); + + ilo_3d_pipeline_emit_flush(hw3d->pipeline); + + hw3d->new_batch = false; } #define UPDATE_MIN2(a, b) (a) = MIN2((a), (b)) @@ -524,36 +658,34 @@ ilo_find_sub_primitives(const void *elements, unsigned element_size, } static inline bool -ilo_check_restart_index(struct ilo_context *ilo, - const struct pipe_draw_info *info) +ilo_check_restart_index(const struct ilo_context *ilo, unsigned restart_index) { /* * Haswell (GEN(7.5)) supports an arbitrary cut index, check everything * older. */ - if (ilo->dev->gen >= ILO_GEN(7.5)) + if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7.5)) return true; /* Note: indices must be unsigned byte, unsigned short or unsigned int */ - switch (ilo->index_buffer.index_size) { + switch (ilo->state_vector.ib.index_size) { case 1: - return ((info->restart_index & 0xff) == 0xff); + return ((restart_index & 0xff) == 0xff); break; case 2: - return ((info->restart_index & 0xffff) == 0xffff); + return ((restart_index & 0xffff) == 0xffff); break; case 4: - return (info->restart_index == 0xffffffff); + return (restart_index == 0xffffffff); break; } return false; } static inline bool -ilo_check_restart_prim_type(struct ilo_context *ilo, - const struct pipe_draw_info *info) +ilo_check_restart_prim_type(const struct ilo_context *ilo, unsigned prim) { - switch (info->mode) { + switch (prim) { case PIPE_PRIM_POINTS: case PIPE_PRIM_LINES: case PIPE_PRIM_LINE_STRIP: @@ -568,7 +700,7 @@ ilo_check_restart_prim_type(struct ilo_context *ilo, case PIPE_PRIM_QUAD_STRIP: case PIPE_PRIM_QUADS: case PIPE_PRIM_TRIANGLE_FAN: - if (ilo->dev->gen >= ILO_GEN(7.5)) { + if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7.5)) { /* Haswell and newer parts can handle these prim types. */ return true; } @@ -589,7 +721,7 @@ static void ilo_draw_vbo_with_sw_restart(struct pipe_context *pipe, const struct pipe_draw_info *info) { - struct ilo_context *ilo = ilo_context(pipe); + struct ilo_state_vector *vec = &ilo_context(pipe)->state_vector; struct pipe_draw_info *restart_info = NULL; int sub_prim_count = 1; @@ -605,19 +737,23 @@ ilo_draw_vbo_with_sw_restart(struct pipe_context *pipe, return; } - struct pipe_transfer *transfer = NULL; - const void *map = NULL; - map = pipe_buffer_map(pipe, - ilo->index_buffer.buffer, - PIPE_TRANSFER_READ, - &transfer); + if (vec->ib.buffer) { + struct pipe_transfer *transfer; + const void *map; + + map = pipe_buffer_map(pipe, vec->ib.buffer, + PIPE_TRANSFER_READ, &transfer); - sub_prim_count = ilo_find_sub_primitives(map + ilo->index_buffer.offset, - ilo->index_buffer.index_size, - info, - restart_info); + sub_prim_count = ilo_find_sub_primitives(map + vec->ib.offset, + vec->ib.index_size, info, restart_info); - pipe_buffer_unmap(pipe, transfer); + pipe_buffer_unmap(pipe, transfer); + } + else { + sub_prim_count = + ilo_find_sub_primitives(vec->ib.user_buffer, + vec->ib.index_size, info, restart_info); + } info = restart_info; @@ -638,7 +774,22 @@ ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) struct ilo_3d *hw3d = ilo->hw3d; int prim_generated, prim_emitted; - if (!pass_render_condition(hw3d, pipe)) + if (ilo_debug & ILO_DEBUG_DRAW) { + if (info->indexed) { + ilo_printf("indexed draw %s: " + "index start %d, count %d, vertex range [%d, %d]\n", + u_prim_name(info->mode), info->start, info->count, + info->min_index, info->max_index); + } + else { + ilo_printf("draw %s: vertex start %d, count %d\n", + u_prim_name(info->mode), info->start, info->count); + } + + ilo_state_vector_dump_dirty(&ilo->state_vector); + } + + if (!ilo_3d_pass_render_condition(ilo)) return; if (info->primitive_restart && info->indexed) { @@ -646,40 +797,29 @@ ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) * Want to draw an indexed primitive using primitive restart * Check that HW can handle the request and fall to SW if not. */ - if (!ilo_check_restart_index(ilo, info) || - !ilo_check_restart_prim_type(ilo, info)) { + if (!ilo_check_restart_index(ilo, info->restart_index) || + !ilo_check_restart_prim_type(ilo, info->mode)) { ilo_draw_vbo_with_sw_restart(pipe, info); return; } } - /* assume the cache is still in use by the previous batch */ - if (hw3d->new_batch) - ilo_shader_cache_mark_busy(ilo->shader_cache); + ilo_finalize_3d_states(ilo, info); - ilo_finalize_states(ilo); + ilo_shader_cache_upload(ilo->shader_cache, &hw3d->cp->builder); - /* the shaders may be uploaded to a new shader cache */ - if (hw3d->shader_cache_seqno != ilo->shader_cache->seqno) { - ilo_3d_pipeline_invalidate(hw3d->pipeline, - ILO_3D_PIPELINE_INVALIDATE_KERNEL_BO); - } - - /* - * The VBs and/or IB may have different BOs due to being mapped with - * PIPE_TRANSFER_DISCARD_x. We should track that instead of setting the - * dirty flags for the performance reason. - */ - ilo->dirty |= ILO_DIRTY_VERTEX_BUFFERS | ILO_DIRTY_INDEX_BUFFER; + ilo_blit_resolve_framebuffer(ilo); /* If draw_vbo ever fails, return immediately. */ - if (!draw_vbo(hw3d, ilo, info, &prim_generated, &prim_emitted)) + if (!draw_vbo(hw3d, &ilo->state_vector, &prim_generated, &prim_emitted)) return; /* clear dirty status */ - ilo->dirty = 0x0; + ilo->state_vector.dirty = 0x0; hw3d->new_batch = false; - hw3d->shader_cache_seqno = ilo->shader_cache->seqno; + + /* avoid dangling pointer reference */ + ilo->state_vector.draw = NULL; update_prim_count(hw3d, prim_generated, prim_emitted); @@ -690,6 +830,7 @@ ilo_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) static void ilo_render_condition(struct pipe_context *pipe, struct pipe_query *query, + boolean condition, uint mode) { struct ilo_context *ilo = ilo_context(pipe); @@ -698,6 +839,7 @@ ilo_render_condition(struct pipe_context *pipe, /* reference count? */ hw3d->render_condition.query = query; hw3d->render_condition.mode = mode; + hw3d->render_condition.cond = condition; } static void @@ -706,14 +848,14 @@ ilo_texture_barrier(struct pipe_context *pipe) struct ilo_context *ilo = ilo_context(pipe); struct ilo_3d *hw3d = ilo->hw3d; - if (ilo->cp->ring != ILO_CP_RING_RENDER) + if (ilo->cp->ring != INTEL_RING_RENDER) return; ilo_3d_pipeline_emit_flush(hw3d->pipeline); /* don't know why */ - if (ilo->dev->gen >= ILO_GEN(7)) - ilo_cp_flush(hw3d->cp); + if (ilo_dev_gen(ilo->dev) >= ILO_GEN(7)) + ilo_cp_submit(hw3d->cp, "texture barrier"); } static void