X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Filo%2Filo_gpe_gen7.c;h=d421c16c685e106b330d3e804da3e010827ce94c;hb=194a61cd39ce21ca8e6a57ca496bc094de629c47;hp=f6cc6e927105589777cd0205a406debc91fb3d36;hpb=f9a4288bd282dfab97a40fc6dc9c046812e7d681;p=mesa.git diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen7.c b/src/gallium/drivers/ilo/ilo_gpe_gen7.c index f6cc6e92710..d421c16c685 100644 --- a/src/gallium/drivers/ilo/ilo_gpe_gen7.c +++ b/src/gallium/drivers/ilo/ilo_gpe_gen7.c @@ -42,7 +42,7 @@ ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev, int start_grf, vue_read_len, max_threads; uint32_t dw2, dw4, dw5; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); start_grf = ilo_shader_get_kernel_param(gs, ILO_KERNEL_URB_DATA_START_REG); vue_read_len = ilo_shader_get_kernel_param(gs, ILO_KERNEL_INPUT_COUNT); @@ -51,6 +51,9 @@ ilo_gpe_init_gs_cso_gen7(const struct ilo_dev_info *dev, vue_read_len = (vue_read_len + 1) / 2; switch (dev->gen) { + case ILO_GEN(7.5): + max_threads = (dev->gt >= 2) ? 256 : 70; + break; case ILO_GEN(7): max_threads = (dev->gt == 2) ? 128 : 36; break; @@ -83,7 +86,7 @@ ilo_gpe_init_rasterizer_wm_gen7(const struct ilo_dev_info *dev, { uint32_t dw1, dw2; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); dw1 = GEN7_WM_POSITION_ZW_PIXEL | GEN7_WM_LINE_AA_WIDTH_2_0 | @@ -132,18 +135,29 @@ ilo_gpe_init_fs_cso_gen7(const struct ilo_dev_info *dev, uint32_t dw2, dw4, dw5; uint32_t wm_interps, wm_dw1; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); start_grf = ilo_shader_get_kernel_param(fs, ILO_KERNEL_URB_DATA_START_REG); - /* see brwCreateContext() */ - max_threads = (dev->gt == 2) ? 172 : 48; dw2 = (true) ? 0 : GEN7_PS_FLOATING_POINT_MODE_ALT; - dw4 = (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT | - GEN7_PS_POSOFFSET_NONE; + dw4 = GEN7_PS_POSOFFSET_NONE; + + /* see brwCreateContext() */ + switch (dev->gen) { + case ILO_GEN(7.5): + max_threads = (dev->gt == 3) ? 408 : (dev->gt == 2) ? 204 : 102; + dw4 |= (max_threads - 1) << HSW_PS_MAX_THREADS_SHIFT; + dw4 |= 1 << HSW_PS_SAMPLE_MASK_SHIFT; + break; + case ILO_GEN(7): + default: + max_threads = (dev->gt == 2) ? 172 : 48; + dw4 |= (max_threads - 1) << IVB_PS_MAX_THREADS_SHIFT; + break; + } - if (false) + if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_PCB_CBUF0_SIZE)) dw4 |= GEN7_PS_PUSH_CONSTANT_ENABLE; if (ilo_shader_get_kernel_param(fs, ILO_KERNEL_INPUT_COUNT)) @@ -226,7 +240,7 @@ ilo_gpe_init_view_surface_null_gen7(const struct ilo_dev_info *dev, { uint32_t *dw; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); /* * From the Ivy Bridge PRM, volume 4 part 1, page 62: @@ -299,7 +313,7 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev, int surface_type, surface_format, num_entries; uint32_t *dw; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); surface_type = (structured) ? 5 : BRW_SURFACE_BUFFER; @@ -396,6 +410,13 @@ ilo_gpe_init_view_surface_for_buffer_gen7(const struct ilo_dev_info *dev, dw[6] = 0; dw[7] = 0; + if (dev->gen >= ILO_GEN(7.5)) { + dw[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + } + /* do not increment reference count */ surf->bo = buf->bo; } @@ -408,7 +429,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, unsigned num_levels, unsigned first_layer, unsigned num_layers, - bool is_rt, bool render_cache_rw, + bool is_rt, bool offset_to_layer, struct ilo_view_surface *surf) { int surface_type, surface_format; @@ -416,7 +437,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, unsigned layer_offset, x_offset, y_offset; uint32_t *dw; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); surface_type = ilo_gpe_gen6_translate_texture(tex->base.target); assert(surface_type != BRW_SURFACE_BUFFER); @@ -484,52 +505,44 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, } if (is_rt) { - /* - * Compute the offset to the layer manually. - * - * For rendering, the hardware requires LOD to be the same for all - * render targets and the depth buffer. We need to compute the offset - * to the layer manually and always set LOD to 0. - */ - if (true) { - /* we lose the capability for layered rendering */ - assert(num_layers == 1); - - layer_offset = ilo_texture_get_slice_offset(tex, - first_level, first_layer, &x_offset, &y_offset); - - assert(x_offset % 4 == 0); - assert(y_offset % 2 == 0); - x_offset /= 4; - y_offset /= 2; - - /* derive the size for the LOD */ - width = u_minify(width, first_level); - height = u_minify(height, first_level); - if (surface_type == BRW_SURFACE_3D) - depth = u_minify(depth, first_level); - else - depth = 1; - - first_level = 0; - first_layer = 0; - lod = 0; - } - else { - layer_offset = 0; - x_offset = 0; - y_offset = 0; - } - assert(num_levels == 1); lod = first_level; } + else { + lod = num_levels - 1; + } + + /* + * Offset to the layer. When rendering, the hardware requires LOD and + * Depth to be the same for all render targets and the depth buffer. We + * need to offset to the layer manually and always set LOD and Depth to 0. + */ + if (offset_to_layer) { + /* we lose the capability for layered rendering */ + assert(is_rt && num_layers == 1); + + layer_offset = ilo_texture_get_slice_offset(tex, + first_level, first_layer, &x_offset, &y_offset); + + assert(x_offset % 4 == 0); + assert(y_offset % 2 == 0); + x_offset /= 4; + y_offset /= 2; + + /* derive the size for the LOD */ + width = u_minify(width, first_level); + height = u_minify(height, first_level); + + first_level = 0; + first_layer = 0; + + lod = 0; + depth = 1; + } else { layer_offset = 0; x_offset = 0; y_offset = 0; - - lod = num_levels - 1; } /* @@ -601,7 +614,7 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, else dw[0] |= GEN7_SURFACE_ARYSPC_LOD0; - if (render_cache_rw) + if (is_rt) dw[0] |= BRW_SURFACE_RC_READ_WRITE; if (surface_type == BRW_SURFACE_CUBE && !is_rt) @@ -646,6 +659,13 @@ ilo_gpe_init_view_surface_for_texture_gen7(const struct ilo_dev_info *dev, dw[6] = 0; dw[7] = 0; + if (dev->gen >= ILO_GEN(7.5)) { + dw[7] |= SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + } + /* do not increment reference count */ surf->bo = tex->bo; } @@ -675,6 +695,7 @@ ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev, [ILO_GPE_GEN7_3DSTATE_VERTEX_BUFFERS] = { 1, 4 }, [ILO_GPE_GEN7_3DSTATE_VERTEX_ELEMENTS] = { 1, 2 }, [ILO_GPE_GEN7_3DSTATE_INDEX_BUFFER] = { 0, 3 }, + [ILO_GPE_GEN7_3DSTATE_VF] = { 0, 2 }, [ILO_GPE_GEN7_3DSTATE_CC_STATE_POINTERS] = { 0, 2 }, [ILO_GPE_GEN7_3DSTATE_SCISSOR_STATE_POINTERS] = { 0, 2 }, [ILO_GPE_GEN7_3DSTATE_VS] = { 0, 6 }, @@ -732,7 +753,7 @@ ilo_gpe_gen7_estimate_command_size(const struct ilo_dev_info *dev, const int body = gen7_command_size_table[cmd].body; const int count = arg; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); assert(cmd < ILO_GPE_GEN7_COMMAND_COUNT); return (likely(count)) ? header + body * count : 0; @@ -767,7 +788,7 @@ ilo_gpe_gen7_estimate_state_size(const struct ilo_dev_info *dev, const int count = arg; int estimate; - ILO_GPE_VALID_GEN(dev, 7, 7); + ILO_GPE_VALID_GEN(dev, 7, 7.5); assert(state < ILO_GPE_GEN7_STATE_COUNT); if (likely(count)) {