X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_blit.c;h=f0a43e959a58c1d7602ccdeb0801659ad5f46e10;hb=bb3545a6ee419c4802ac4153eb690a93dc2f339d;hp=e10e54667f43100fb6c3583b93d4ebcb7073ea1d;hpb=5d331251cfbc304982517c60a854706fa6b60f71;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_blit.c b/src/gallium/drivers/iris/iris_blit.c index e10e54667f4..f0a43e959a5 100644 --- a/src/gallium/drivers/iris/iris_blit.c +++ b/src/gallium/drivers/iris/iris_blit.c @@ -25,7 +25,7 @@ #include "pipe/p_state.h" #include "pipe/p_context.h" #include "pipe/p_screen.h" -#include "util/u_format.h" +#include "util/format/u_format.h" #include "util/u_inlines.h" #include "util/ralloc.h" #include "intel/blorp/blorp.h" @@ -229,7 +229,7 @@ apply_blit_scissor(const struct pipe_scissor_state *scissor, } void -iris_blorp_surf_for_resource(struct iris_vtable *vtbl, +iris_blorp_surf_for_resource(struct isl_device *isl_dev, struct blorp_surf *surf, struct pipe_resource *p_res, enum isl_aux_usage aux_usage, @@ -250,7 +250,7 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->bo, .offset = res->offset, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, - .mocs = vtbl->mocs(res->bo), + .mocs = iris_mocs(res->bo, isl_dev), }, .aux_usage = aux_usage, }; @@ -261,7 +261,7 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->aux.bo, .offset = res->aux.offset, .reloc_flags = is_render_target ? EXEC_OBJECT_WRITE : 0, - .mocs = vtbl->mocs(res->bo), + .mocs = iris_mocs(res->bo, isl_dev), }; surf->clear_color = iris_resource_get_clear_color(res, NULL, NULL); @@ -269,11 +269,9 @@ iris_blorp_surf_for_resource(struct iris_vtable *vtbl, .buffer = res->aux.clear_color_bo, .offset = res->aux.clear_color_offset, .reloc_flags = 0, - .mocs = vtbl->mocs(res->aux.clear_color_bo), + .mocs = iris_mocs(res->aux.clear_color_bo, isl_dev), }; } - - // XXX: ASTC } static bool @@ -320,6 +318,21 @@ tex_cache_flush_hack(struct iris_batch *batch, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); } +static enum isl_aux_usage +iris_resource_blorp_write_aux_usage(struct iris_context *ice, + struct iris_resource *res, + enum isl_format render_format) +{ + if (res->surf.usage & (ISL_SURF_USAGE_DEPTH_BIT | + ISL_SURF_USAGE_STENCIL_BIT)) { + assert(render_format == res->surf.format); + return res->aux.usage; + } else { + return iris_resource_render_aux_usage(ice, res, render_format, + false, false); + } +} + /** * The pipe->blit() driver hook. * @@ -349,16 +362,21 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) blorp_flags |= BLORP_BATCH_PREDICATE_ENABLE; } + if (iris_resource_unfinished_aux_import(src_res)) + iris_resource_finish_aux_import(ctx->screen, src_res); + if (iris_resource_unfinished_aux_import(dst_res)) + iris_resource_finish_aux_import(ctx->screen, dst_res); + struct iris_format_info src_fmt = iris_format_for_usage(devinfo, info->src.format, ISL_SURF_USAGE_TEXTURE_BIT); enum isl_aux_usage src_aux_usage = - iris_resource_texture_aux_usage(ice, src_res, src_fmt.fmt, 0); + iris_resource_texture_aux_usage(ice, src_res, src_fmt.fmt); if (iris_resource_level_has_hiz(src_res, info->src.level)) - src_aux_usage = ISL_AUX_USAGE_NONE; + assert(src_res->surf.format == src_fmt.fmt); - bool src_clear_supported = src_aux_usage != ISL_AUX_USAGE_NONE && + bool src_clear_supported = isl_aux_usage_has_fast_clears(src_aux_usage) && src_res->surf.format == src_fmt.fmt; iris_resource_prepare_access(ice, batch, src_res, info->src.level, 1, @@ -369,14 +387,16 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) iris_format_for_usage(devinfo, info->dst.format, ISL_SURF_USAGE_RENDER_TARGET_BIT); enum isl_aux_usage dst_aux_usage = - iris_resource_render_aux_usage(ice, dst_res, dst_fmt.fmt, false, false); - bool dst_clear_supported = dst_aux_usage != ISL_AUX_USAGE_NONE; + iris_resource_blorp_write_aux_usage(ice, dst_res, dst_fmt.fmt); + bool dst_clear_supported = isl_aux_usage_has_fast_clears(dst_aux_usage); struct blorp_surf src_surf, dst_surf; - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, info->src.resource, - src_aux_usage, info->src.level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, info->dst.resource, - dst_aux_usage, info->dst.level, true); + iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf, + info->src.resource, src_aux_usage, + info->src.level, false); + iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf, + info->dst.resource, dst_aux_usage, + info->dst.level, true); iris_resource_prepare_access(ice, batch, dst_res, info->dst.level, 1, info->dst.box.z, info->dst.box.depth, @@ -493,29 +513,13 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) iris_format_for_usage(devinfo, src_res->base.format, ISL_SURF_USAGE_TEXTURE_BIT); stc_src_aux_usage = - iris_resource_texture_aux_usage(ice, src_res, src_fmt.fmt, 0); + iris_resource_texture_aux_usage(ice, src_res, src_fmt.fmt); struct iris_format_info dst_fmt = iris_format_for_usage(devinfo, stc_dst->base.format, ISL_SURF_USAGE_RENDER_TARGET_BIT); stc_dst_aux_usage = - iris_resource_render_aux_usage(ice, stc_dst, dst_fmt.fmt, false, false); - - /* Resolve destination surface before blit because : - * 1. when we try to blit from the same surface, we can't read and - * write to the same surfaces at the same time when we have - * compression enabled so it's safe to resolve surface first and then - * do blit. - * 2. While bliting from one surface to another surface, we might be - * mixing compression formats, Our experiments shows that if after - * blit if we set DepthStencilResource flag to 0, blit passes but - * clear fails. - * - * XXX: In second case by destructing the compression, we might lose - * some performance. - */ - if (devinfo->gen >= 12) - stc_dst_aux_usage = ISL_AUX_USAGE_NONE; + iris_resource_blorp_write_aux_usage(ice, stc_dst, dst_fmt.fmt); iris_resource_prepare_access(ice, batch, src_res, info->src.level, 1, info->src.box.z, info->src.box.depth, @@ -523,10 +527,12 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) iris_resource_prepare_access(ice, batch, stc_dst, info->dst.level, 1, info->dst.box.z, info->dst.box.depth, stc_dst_aux_usage, false); - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, &src_res->base, - stc_src_aux_usage, info->src.level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, &stc_dst->base, - stc_dst_aux_usage, info->dst.level, true); + iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf, + &src_res->base, stc_src_aux_usage, + info->src.level, false); + iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf, + &stc_dst->base, stc_dst_aux_usage, + info->dst.level, true); for (int slice = 0; slice < info->dst.box.depth; slice++) { iris_batch_maybe_flush(batch, 1500); @@ -563,12 +569,27 @@ iris_blit(struct pipe_context *ctx, const struct pipe_blit_info *info) } static void -get_copy_region_aux_settings(const struct gen_device_info *devinfo, +get_copy_region_aux_settings(struct iris_context *ice, struct iris_resource *res, enum isl_aux_usage *out_aux_usage, - bool *out_clear_supported) + bool *out_clear_supported, + bool is_render_target) { + struct iris_screen *screen = (void *) ice->ctx.screen; + const struct gen_device_info *devinfo = &screen->devinfo; + switch (res->aux.usage) { + case ISL_AUX_USAGE_HIZ: + case ISL_AUX_USAGE_HIZ_CCS: + case ISL_AUX_USAGE_HIZ_CCS_WT: + if (is_render_target) { + *out_aux_usage = res->aux.usage; + } else { + *out_aux_usage = iris_resource_texture_aux_usage(ice, res, + res->surf.format); + } + *out_clear_supported = (*out_aux_usage != ISL_AUX_USAGE_NONE); + break; case ISL_AUX_USAGE_MCS: case ISL_AUX_USAGE_MCS_CCS: case ISL_AUX_USAGE_CCS_E: @@ -580,6 +601,10 @@ get_copy_region_aux_settings(const struct gen_device_info *devinfo, */ *out_clear_supported = devinfo->gen >= 9; break; + case ISL_AUX_USAGE_STC_CCS: + *out_aux_usage = res->aux.usage; + *out_clear_supported = false; + break; default: *out_aux_usage = ISL_AUX_USAGE_NONE; *out_clear_supported = false; @@ -608,16 +633,15 @@ iris_copy_region(struct blorp_context *blorp, struct blorp_batch blorp_batch; struct iris_context *ice = blorp->driver_ctx; struct iris_screen *screen = (void *) ice->ctx.screen; - const struct gen_device_info *devinfo = &screen->devinfo; struct iris_resource *src_res = (void *) src; struct iris_resource *dst_res = (void *) dst; enum isl_aux_usage src_aux_usage, dst_aux_usage; bool src_clear_supported, dst_clear_supported; - get_copy_region_aux_settings(devinfo, src_res, &src_aux_usage, - &src_clear_supported); - get_copy_region_aux_settings(devinfo, dst_res, &dst_aux_usage, - &dst_clear_supported); + get_copy_region_aux_settings(ice, src_res, &src_aux_usage, + &src_clear_supported, false); + get_copy_region_aux_settings(ice, dst_res, &dst_aux_usage, + &dst_clear_supported, true); if (iris_batch_references(batch, src_res->bo)) tex_cache_flush_hack(batch, ISL_FORMAT_UNSUPPORTED, src_res->surf.format); @@ -643,10 +667,10 @@ iris_copy_region(struct blorp_context *blorp, // XXX: what about one surface being a buffer and not the other? struct blorp_surf src_surf, dst_surf; - iris_blorp_surf_for_resource(&ice->vtbl, &src_surf, src, src_aux_usage, - src_level, false); - iris_blorp_surf_for_resource(&ice->vtbl, &dst_surf, dst, dst_aux_usage, - dst_level, true); + iris_blorp_surf_for_resource(&screen->isl_dev, &src_surf, + src, src_aux_usage, src_level, false); + iris_blorp_surf_for_resource(&screen->isl_dev, &dst_surf, + dst, dst_aux_usage, dst_level, true); iris_resource_prepare_access(ice, batch, src_res, src_level, 1, src_box->z, src_box->depth, @@ -696,44 +720,52 @@ get_preferred_batch(struct iris_context *ice, struct iris_bo *bo) */ static void iris_resource_copy_region(struct pipe_context *ctx, - struct pipe_resource *dst, + struct pipe_resource *p_dst, unsigned dst_level, unsigned dstx, unsigned dsty, unsigned dstz, - struct pipe_resource *src, + struct pipe_resource *p_src, unsigned src_level, const struct pipe_box *src_box) { struct iris_context *ice = (void *) ctx; + struct iris_screen *screen = (void *) ctx->screen; struct iris_batch *batch = &ice->batches[IRIS_BATCH_RENDER]; + struct iris_resource *src = (void *) p_src; + struct iris_resource *dst = (void *) p_dst; + + if (iris_resource_unfinished_aux_import(src)) + iris_resource_finish_aux_import(ctx->screen, src); + if (iris_resource_unfinished_aux_import(dst)) + iris_resource_finish_aux_import(ctx->screen, dst); /* Use MI_COPY_MEM_MEM for tiny (<= 16 byte, % 4) buffer copies. */ - if (src->target == PIPE_BUFFER && dst->target == PIPE_BUFFER && + if (p_src->target == PIPE_BUFFER && p_dst->target == PIPE_BUFFER && (src_box->width % 4 == 0) && src_box->width <= 16) { - struct iris_bo *dst_bo = iris_resource_bo(dst); + struct iris_bo *dst_bo = iris_resource_bo(p_dst); batch = get_preferred_batch(ice, dst_bo); iris_batch_maybe_flush(batch, 24 + 5 * (src_box->width / 4)); iris_emit_pipe_control_flush(batch, "stall for MI_COPY_MEM_MEM copy_region", PIPE_CONTROL_CS_STALL); - ice->vtbl.copy_mem_mem(batch, dst_bo, dstx, iris_resource_bo(src), - src_box->x, src_box->width); + screen->vtbl.copy_mem_mem(batch, dst_bo, dstx, iris_resource_bo(p_src), + src_box->x, src_box->width); return; } - iris_copy_region(&ice->blorp, batch, dst, dst_level, dstx, dsty, dstz, - src, src_level, src_box); + iris_copy_region(&ice->blorp, batch, p_dst, dst_level, dstx, dsty, dstz, + p_src, src_level, src_box); - if (util_format_is_depth_and_stencil(dst->format) && - util_format_has_stencil(util_format_description(src->format))) { + if (util_format_is_depth_and_stencil(p_dst->format) && + util_format_has_stencil(util_format_description(p_src->format))) { struct iris_resource *junk, *s_src_res, *s_dst_res; - iris_get_depth_stencil_resources(src, &junk, &s_src_res); - iris_get_depth_stencil_resources(dst, &junk, &s_dst_res); + iris_get_depth_stencil_resources(p_src, &junk, &s_src_res); + iris_get_depth_stencil_resources(p_dst, &junk, &s_dst_res); iris_copy_region(&ice->blorp, batch, &s_dst_res->base, dst_level, dstx, dsty, dstz, &s_src_res->base, src_level, src_box); } - iris_flush_and_dirty_for_history(ice, batch, (struct iris_resource *) dst, + iris_flush_and_dirty_for_history(ice, batch, dst, PIPE_CONTROL_RENDER_TARGET_FLUSH, "cache history: post copy_region"); }