X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_resource.c;h=03ce35462fa64575334d3dc4ffbe3ffd49490974;hb=2993088500365405516663fa48b1764e8c8d1ffa;hp=0ea72a9075b6432f826c3ad82c8d831a37eed507;hpb=e5528151a733d06f67a70d0bf739d961a09fc215;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 0ea72a9075b..03ce35462fa 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -51,8 +51,6 @@ #include "drm-uapi/drm_fourcc.h" #include "drm-uapi/i915_drm.h" -// XXX: u_transfer_helper...for separate stencil... - enum modifier_priority { MODIFIER_PRIORITY_INVALID = 0, MODIFIER_PRIORITY_LINEAR, @@ -189,25 +187,38 @@ iris_get_depth_stencil_resources(struct pipe_resource *res, return; } - const struct util_format_description *desc = - util_format_description(res->format); - - if (util_format_has_depth(desc)) { + if (res->format != PIPE_FORMAT_S8_UINT) { *out_z = (void *) res; *out_s = (void *) iris_resource_get_separate_stencil(res); } else { - assert(util_format_has_stencil(desc)); *out_z = NULL; *out_s = (void *) res; } } +void +iris_resource_disable_aux(struct iris_resource *res) +{ + iris_bo_unreference(res->aux.bo); + free(res->aux.state); + + // XXX: clear color BO + + res->aux.usage = ISL_AUX_USAGE_NONE; + res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE; + res->aux.surf.size_B = 0; + res->aux.bo = NULL; + res->aux.state = NULL; +} + static void iris_resource_destroy(struct pipe_screen *screen, struct pipe_resource *resource) { struct iris_resource *res = (struct iris_resource *)resource; + iris_resource_disable_aux(res); + iris_bo_unreference(res->bo); free(res); } @@ -224,9 +235,246 @@ iris_alloc_resource(struct pipe_screen *pscreen, res->base.screen = pscreen; pipe_reference_init(&res->base.reference, 1); + res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE; + return res; } +unsigned +iris_get_num_logical_layers(const struct iris_resource *res, unsigned level) +{ + if (res->surf.dim == ISL_SURF_DIM_3D) + return minify(res->surf.logical_level0_px.depth, level); + else + return res->surf.logical_level0_px.array_len; +} + +static enum isl_aux_state ** +create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial) +{ + uint32_t total_slices = 0; + for (uint32_t level = 0; level < res->surf.levels; level++) + total_slices += iris_get_num_logical_layers(res, level); + + const size_t per_level_array_size = + res->surf.levels * sizeof(enum isl_aux_state *); + + /* We're going to allocate a single chunk of data for both the per-level + * reference array and the arrays of aux_state. This makes cleanup + * significantly easier. + */ + const size_t total_size = + per_level_array_size + total_slices * sizeof(enum isl_aux_state); + + void *data = malloc(total_size); + if (!data) + return NULL; + + enum isl_aux_state **per_level_arr = data; + enum isl_aux_state *s = data + per_level_array_size; + for (uint32_t level = 0; level < res->surf.levels; level++) { + per_level_arr[level] = s; + const unsigned level_layers = iris_get_num_logical_layers(res, level); + for (uint32_t a = 0; a < level_layers; a++) + *(s++) = initial; + } + assert((void *)s == data + total_size); + + return per_level_arr; +} + +/** + * Allocate the initial aux surface for a resource based on aux.usage + */ +static bool +iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) +{ + struct isl_device *isl_dev = &screen->isl_dev; + enum isl_aux_state initial_state; + UNUSED bool ok = false; + uint8_t memset_value = 0; + uint32_t alloc_flags = 0; + + assert(!res->aux.bo); + + switch (res->aux.usage) { + case ISL_AUX_USAGE_NONE: + res->aux.surf.size_B = 0; + break; + case ISL_AUX_USAGE_HIZ: + initial_state = ISL_AUX_STATE_AUX_INVALID; + memset_value = 0; + ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf); + break; + case ISL_AUX_USAGE_MCS: + /* The Ivybridge PRM, Vol 2 Part 1 p326 says: + * + * "When MCS buffer is enabled and bound to MSRT, it is required + * that it is cleared prior to any rendering." + * + * Since we only use the MCS buffer for rendering, we just clear it + * immediately on allocation. The clear value for MCS buffers is all + * 1's, so we simply memset it to 0xff. + */ + initial_state = ISL_AUX_STATE_CLEAR; + memset_value = 0xFF; + ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf); + break; + case ISL_AUX_USAGE_CCS_D: + case ISL_AUX_USAGE_CCS_E: + /* When CCS_E is used, we need to ensure that the CCS starts off in + * a valid state. From the Sky Lake PRM, "MCS Buffer for Render + * Target(s)": + * + * "If Software wants to enable Color Compression without Fast + * clear, Software needs to initialize MCS with zeros." + * + * A CCS value of 0 indicates that the corresponding block is in the + * pass-through state which is what we want. + * + * For CCS_D, do the same thing. On Gen9+, this avoids having any + * undefined bits in the aux buffer. + */ + initial_state = ISL_AUX_STATE_PASS_THROUGH; + alloc_flags |= BO_ALLOC_ZEROED; + ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0); + break; + } + + /* No work is needed for a zero-sized auxiliary buffer. */ + if (res->aux.surf.size_B == 0) + return true; + + /* Assert that ISL gave us a valid aux surf */ + assert(ok); + + /* Create the aux_state for the auxiliary buffer. */ + res->aux.state = create_aux_state_map(res, initial_state); + if (!res->aux.state) + return false; + + /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules + * the drm allocator. Therefore, one can pass the ISL dimensions in terms + * of bytes instead of trying to recalculate based on different format + * block sizes. + */ + res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", + res->aux.surf.size_B, + IRIS_MEMZONE_OTHER, I915_TILING_Y, + res->aux.surf.row_pitch_B, alloc_flags); + if (!res->aux.bo) { + iris_resource_disable_aux(res); + return false; + } + + /* Optionally, initialize the auxiliary data to the desired value. */ + if (memset_value != 0) { + void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW); + if (!map) { + iris_resource_disable_aux(res); + return false; + } + + memset(map, memset_value, res->aux.surf.size_B); + iris_bo_unmap(res->aux.bo); + } + + if (res->aux.usage == ISL_AUX_USAGE_HIZ) { + for (unsigned level = 0; level < res->surf.levels; ++level) { + uint32_t width = u_minify(res->surf.phys_level0_sa.width, level); + uint32_t height = u_minify(res->surf.phys_level0_sa.height, level); + + /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned. + * For LOD == 0, we can grow the dimensions to make it work. + */ + if (level == 0 || ((width & 7) == 0 && (height & 3) == 0)) + res->aux.has_hiz |= 1 << level; + } + } + + return true; +} + +static bool +supports_mcs(const struct isl_surf *surf) +{ + /* MCS compression only applies to multisampled resources. */ + if (surf->samples <= 1) + return false; + + /* See isl_surf_get_mcs_surf for details. */ + if (surf->samples == 16 && surf->logical_level0_px.width > 8192) + return false; + + /* Depth and stencil buffers use the IMS (interleaved) layout. */ + if (isl_surf_usage_is_depth_or_stencil(surf->usage)) + return false; + + return true; +} + +static bool +supports_ccs(const struct gen_device_info *devinfo, + const struct isl_surf *surf) +{ + /* Gen9+ only supports CCS for Y-tiled buffers. */ + if (surf->tiling != ISL_TILING_Y0) + return false; + + /* CCS only supports singlesampled resources. */ + if (surf->samples > 1) + return false; + + /* The PRM doesn't say this explicitly, but fast-clears don't appear to + * work for 3D textures until Gen9 where the layout of 3D textures changes + * to match 2D array textures. + */ + if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D) + return false; + + /* Note: still need to check the format! */ + + return true; +} + +static struct pipe_resource * +iris_resource_create_for_buffer(struct pipe_screen *pscreen, + const struct pipe_resource *templ) +{ + struct iris_screen *screen = (struct iris_screen *)pscreen; + struct iris_resource *res = iris_alloc_resource(pscreen, templ); + + assert(templ->target == PIPE_BUFFER); + assert(templ->height0 <= 1); + assert(templ->depth0 <= 1); + assert(templ->format == PIPE_FORMAT_NONE || + util_format_get_blocksize(templ->format) == 1); + + res->internal_format = templ->format; + res->surf.tiling = ISL_TILING_LINEAR; + + enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER; + const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree"; + if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) { + memzone = IRIS_MEMZONE_SHADER; + name = "shader kernels"; + } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) { + memzone = IRIS_MEMZONE_SURFACE; + name = "surface state"; + } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) { + memzone = IRIS_MEMZONE_DYNAMIC; + name = "dynamic state"; + } + + res->bo = iris_bo_alloc(screen->bufmgr, name, templ->width0, memzone); + if (!res->bo) { + iris_resource_destroy(pscreen, &res->base); + return NULL; + } + + return &res->base; +} + static struct pipe_resource * iris_resource_create_with_modifiers(struct pipe_screen *pscreen, const struct pipe_resource *templ, @@ -236,48 +484,48 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, struct iris_screen *screen = (struct iris_screen *)pscreen; struct gen_device_info *devinfo = &screen->devinfo; struct iris_resource *res = iris_alloc_resource(pscreen, templ); - const struct util_format_description *format_desc = - util_format_description(templ->format); if (!res) return NULL; + const struct util_format_description *format_desc = + util_format_description(templ->format); const bool has_depth = util_format_has_depth(format_desc); - uint64_t modifier = DRM_FORMAT_MOD_INVALID; - - if (modifiers_count == 0 || !modifiers) { - if (has_depth) { - modifier = I915_FORMAT_MOD_Y_TILED; - } else if (templ->target == PIPE_TEXTURE_1D || - templ->target == PIPE_TEXTURE_1D_ARRAY) { - modifier = DRM_FORMAT_MOD_LINEAR; - } else if (templ->bind & PIPE_BIND_DISPLAY_TARGET) { - /* Display is X-tiled for historical reasons. */ - modifier = I915_FORMAT_MOD_X_TILED; - } else { - modifier = I915_FORMAT_MOD_Y_TILED; - } - /* XXX: make sure this doesn't do stupid things for internal textures */ - } + uint64_t modifier = + select_best_modifier(devinfo, modifiers, modifiers_count); - if (templ->target == PIPE_BUFFER || templ->usage == PIPE_USAGE_STAGING) - modifier = DRM_FORMAT_MOD_LINEAR; + isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; - if (templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) - modifier = DRM_FORMAT_MOD_LINEAR; + if (modifier != DRM_FORMAT_MOD_INVALID) { + res->mod_info = isl_drm_modifier_get_info(modifier); - if (modifier == DRM_FORMAT_MOD_INVALID) { - /* User requested specific modifiers */ - modifier = select_best_modifier(devinfo, modifiers, modifiers_count); - if (modifier == DRM_FORMAT_MOD_INVALID) + tiling_flags = 1 << res->mod_info->tiling; + } else { + if (modifiers_count > 0) { + fprintf(stderr, "Unsupported modifier, resource creation failed.\n"); return NULL; - } + } - const struct isl_drm_modifier_info *mod_info = - isl_drm_modifier_get_info(modifier); + /* No modifiers - we can select our own tiling. */ - enum isl_tiling tiling = templ->format == PIPE_FORMAT_S8_UINT ? - ISL_TILING_W : mod_info->tiling; + if (has_depth) { + /* Depth must be Y-tiled */ + tiling_flags = ISL_TILING_Y0_BIT; + } else if (templ->format == PIPE_FORMAT_S8_UINT) { + /* Stencil must be W-tiled */ + tiling_flags = ISL_TILING_W_BIT; + } else if (templ->target == PIPE_BUFFER || + templ->target == PIPE_TEXTURE_1D || + templ->target == PIPE_TEXTURE_1D_ARRAY) { + /* Use linear for buffers and 1D textures */ + tiling_flags = ISL_TILING_LINEAR_BIT; + } + + /* Use linear for staging buffers */ + if (templ->usage == PIPE_USAGE_STAGING || + templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) ) + tiling_flags = ISL_TILING_LINEAR_BIT; + } isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind); @@ -314,41 +562,69 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, .min_alignment_B = 0, .row_pitch_B = 0, .usage = usage, - .tiling_flags = 1 << tiling); + .tiling_flags = tiling_flags); assert(isl_surf_created_successfully); - enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER; - const char *name = templ->target == PIPE_BUFFER ? "buffer" : "miptree"; - if (templ->flags & IRIS_RESOURCE_FLAG_SHADER_MEMZONE) { - memzone = IRIS_MEMZONE_SHADER; - name = "shader kernels"; - } else if (templ->flags & IRIS_RESOURCE_FLAG_SURFACE_MEMZONE) { - memzone = IRIS_MEMZONE_SURFACE; - name = "surface state"; - } else if (templ->flags & IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE) { - memzone = IRIS_MEMZONE_DYNAMIC; - name = "dynamic state"; + if (res->mod_info) { + res->aux.possible_usages |= 1 << res->mod_info->aux_usage; + } else if (res->surf.samples > 1) { + if (supports_mcs(&res->surf)) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS; + } else { + if (has_depth) { + if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ))) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ; + } else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) && + supports_ccs(devinfo, &res->surf)) { + if (isl_format_supports_ccs_e(devinfo, res->surf.format)) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E; + + if (isl_format_supports_ccs_d(devinfo, res->surf.format)) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D; + } } + // XXX: we don't actually do aux yet + res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE; + + res->aux.usage = util_last_bit(res->aux.possible_usages) - 1; + + const char *name = "miptree"; + enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER; + + /* These are for u_upload_mgr buffers only */ + assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE | + IRIS_RESOURCE_FLAG_SURFACE_MEMZONE | + IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE))); + res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B, memzone, isl_tiling_to_i915_tiling(res->surf.tiling), res->surf.row_pitch_B, 0); + if (!res->bo) goto fail; + if (!iris_resource_alloc_aux(screen, res)) + goto fail; + return &res->base; fail: + fprintf(stderr, "XXX: resource creation failed\n"); iris_resource_destroy(pscreen, &res->base); return NULL; + } static struct pipe_resource * iris_resource_create(struct pipe_screen *pscreen, const struct pipe_resource *templ) { - return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0); + if (templ->target == PIPE_BUFFER) + return iris_resource_create_for_buffer(pscreen, templ); + else + return iris_resource_create_with_modifiers(pscreen, templ, NULL, 0); } static uint64_t @@ -371,12 +647,14 @@ iris_resource_from_user_memory(struct pipe_screen *pscreen, void *user_memory) { struct iris_screen *screen = (struct iris_screen *)pscreen; - struct gen_device_info *devinfo = &screen->devinfo; struct iris_bufmgr *bufmgr = screen->bufmgr; struct iris_resource *res = iris_alloc_resource(pscreen, templ); if (!res) return NULL; + assert(templ->target == PIPE_BUFFER); + + res->internal_format = templ->format; res->bo = iris_bo_create_userptr(bufmgr, "user", user_memory, templ->width0, IRIS_MEMZONE_OTHER); @@ -385,30 +663,6 @@ iris_resource_from_user_memory(struct pipe_screen *pscreen, return NULL; } - res->internal_format = templ->format; - - // XXX: usage... - isl_surf_usage_flags_t isl_usage = 0; - - const struct iris_format_info fmt = - iris_format_for_usage(devinfo, templ->format, isl_usage); - - isl_surf_init(&screen->isl_dev, &res->surf, - .dim = target_to_isl_surf_dim(templ->target), - .format = fmt.fmt, - .width = templ->width0, - .height = templ->height0, - .depth = templ->depth0, - .levels = templ->last_level + 1, - .array_len = templ->array_size, - .samples = MAX2(templ->nr_samples, 1), - .min_alignment_B = 0, - .row_pitch_B = 0, - .usage = isl_usage, - .tiling_flags = 1 << ISL_TILING_LINEAR); - - assert(res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)); - return &res->base; } @@ -447,33 +701,41 @@ iris_resource_from_handle(struct pipe_screen *pscreen, uint64_t modifier = whandle->modifier; if (modifier == DRM_FORMAT_MOD_INVALID) { - modifier = tiling_to_modifier(res->bo->tiling_mode); + modifier = tiling_to_modifier(res->bo->tiling_mode); } - const struct isl_drm_modifier_info *mod_info = - isl_drm_modifier_get_info(modifier); - assert(mod_info); + res->mod_info = isl_drm_modifier_get_info(modifier); + assert(res->mod_info); - // XXX: usage... - isl_surf_usage_flags_t isl_usage = ISL_SURF_USAGE_DISPLAY_BIT; + isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind); const struct iris_format_info fmt = iris_format_for_usage(devinfo, templ->format, isl_usage); + res->internal_format = templ->format; + + if (templ->target == PIPE_BUFFER) { + res->surf.tiling = ISL_TILING_LINEAR; + } else { + isl_surf_init(&screen->isl_dev, &res->surf, + .dim = target_to_isl_surf_dim(templ->target), + .format = fmt.fmt, + .width = templ->width0, + .height = templ->height0, + .depth = templ->depth0, + .levels = templ->last_level + 1, + .array_len = templ->array_size, + .samples = MAX2(templ->nr_samples, 1), + .min_alignment_B = 0, + .row_pitch_B = whandle->stride, + .usage = isl_usage, + .tiling_flags = 1 << res->mod_info->tiling); - isl_surf_init(&screen->isl_dev, &res->surf, - .dim = target_to_isl_surf_dim(templ->target), - .format = fmt.fmt, - .width = templ->width0, - .height = templ->height0, - .depth = templ->depth0, - .levels = templ->last_level + 1, - .array_len = templ->array_size, - .samples = MAX2(templ->nr_samples, 1), - .min_alignment_B = 0, - .row_pitch_B = 0, - .usage = isl_usage, - .tiling_flags = 1 << mod_info->tiling); - - assert(res->bo->tiling_mode == isl_tiling_to_i915_tiling(res->surf.tiling)); + assert(res->bo->tiling_mode == + isl_tiling_to_i915_tiling(res->surf.tiling)); + + // XXX: create_ccs_buf_for_image? + if (!iris_resource_alloc_aux(screen, res)) + goto fail; + } return &res->base; @@ -489,10 +751,34 @@ iris_resource_get_handle(struct pipe_screen *pscreen, struct winsys_handle *whandle, unsigned usage) { + struct iris_context *ice = (struct iris_context *)ctx; struct iris_resource *res = (struct iris_resource *)resource; + /* If this is a buffer, stride should be 0 - no need to special case */ whandle->stride = res->surf.row_pitch_B; - whandle->modifier = tiling_to_modifier(res->bo->tiling_mode); + whandle->modifier = + res->mod_info ? res->mod_info->modifier + : tiling_to_modifier(res->bo->tiling_mode); + + if (ctx && + (!res->mod_info || res->mod_info->aux_usage != res->aux.usage)) { + struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER]; + iris_resource_prepare_access(ice, render_batch, res, + 0, INTEL_REMAINING_LEVELS, + 0, INTEL_REMAINING_LAYERS, + ISL_AUX_USAGE_NONE, false); + if (res->aux.usage != ISL_AUX_USAGE_NONE) { + iris_resource_disable_aux(res); + ice->state.dirty |= IRIS_ALL_DIRTY_BINDINGS; + } + } else { + if (res->aux.usage != ISL_AUX_USAGE_NONE) { + enum isl_aux_state aux_state = + iris_resource_get_aux_state(res, 0, 0); + assert(aux_state == ISL_AUX_STATE_RESOLVED || + aux_state == ISL_AUX_STATE_PASS_THROUGH); + } + } switch (whandle->type) { case WINSYS_HANDLE_TYPE_SHARED: @@ -563,11 +849,11 @@ s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled) if (swizzled) { /* adjust for bit6 swizzling */ if (((byte_x / 8) % 2) == 1) { - if (((byte_y / 8) % 2) == 0) { - u += 64; - } else { - u -= 64; - } + if (((byte_y / 8) % 2) == 0) { + u += 64; + } else { + u -= 64; + } } } @@ -752,11 +1038,7 @@ iris_map_tiled_memcpy(struct iris_transfer *map) unsigned x1, x2, y1, y2; tile_extents(surf, &box, xfer->level, &x1, &x2, &y1, &y2); - /* When transferring cubes, box.depth is counted in cubes, but - * box.z is counted in faces. We want to transfer only the - * specified face, but for all array elements. So, use 's' - * (the zero-based slice count) rather than box.z. - */ + /* Use 's' rather than 'box.z' to rebase the first slice to 0. */ void *ptr = map->ptr + s * xfer->layer_stride; isl_memcpy_tiled_to_linear(x1, x2, y1, y2, ptr, src, xfer->stride, @@ -775,10 +1057,6 @@ iris_map_direct(struct iris_transfer *map) struct pipe_transfer *xfer = &map->base; struct pipe_box *box = &xfer->box; struct iris_resource *res = (struct iris_resource *) xfer->resource; - struct isl_surf *surf = &res->surf; - const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); - const unsigned cpp = fmtl->bpb / 8; - unsigned x0_el, y0_el; void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage); @@ -788,6 +1066,12 @@ iris_map_direct(struct iris_transfer *map) map->ptr = ptr + box->x; } else { + struct isl_surf *surf = &res->surf; + const struct isl_format_layout *fmtl = + isl_format_get_layout(surf->format); + const unsigned cpp = fmtl->bpb / 8; + unsigned x0_el, y0_el; + get_image_offset_el(surf, xfer->level, box->z, &x0_el, &y0_el); xfer->stride = isl_surf_get_row_pitch_B(surf); @@ -809,18 +1093,27 @@ iris_transfer_map(struct pipe_context *ctx, struct iris_resource *res = (struct iris_resource *)resource; struct isl_surf *surf = &res->surf; + /* If we can discard the whole resource, we can also discard the + * subrange being accessed. + */ + if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) + usage |= PIPE_TRANSFER_DISCARD_RANGE; + if (surf->tiling != ISL_TILING_LINEAR && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) return NULL; - if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) && - iris_batch_references(&ice->render_batch, res->bo)) { - iris_batch_flush(&ice->render_batch); + if (resource->target != PIPE_BUFFER) { + iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res, + level, box->z, box->depth, + usage & PIPE_TRANSFER_WRITE); } - if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) && - iris_batch_references(&ice->compute_batch, res->bo)) { - iris_batch_flush(&ice->compute_batch); + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { + for (int i = 0; i < IRIS_BATCH_COUNT; i++) { + if (iris_batch_references(&ice->batches[i], res->bo)) + iris_batch_flush(&ice->batches[i]); + } } if ((usage & PIPE_TRANSFER_DONTBLOCK) && iris_bo_busy(res->bo)) @@ -829,9 +1122,6 @@ iris_transfer_map(struct pipe_context *ctx, struct iris_transfer *map = slab_alloc(&ice->transfer_pool); struct pipe_transfer *xfer = &map->base; - // PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE - // PIPE_TRANSFER_DISCARD_RANGE - if (!map) return NULL; @@ -863,24 +1153,39 @@ iris_transfer_map(struct pipe_context *ctx, return map->ptr; } +static void +iris_transfer_flush_region(struct pipe_context *ctx, + struct pipe_transfer *xfer, + const struct pipe_box *box) +{ + struct iris_context *ice = (struct iris_context *)ctx; + struct iris_resource *res = (struct iris_resource *) xfer->resource; + + for (int i = 0; i < IRIS_BATCH_COUNT; i++) { + if (ice->batches[i].contains_draw || + ice->batches[i].cache.render->entries) { + iris_batch_maybe_flush(&ice->batches[i], 24); + iris_flush_and_dirty_for_history(ice, &ice->batches[i], res); + } + } +} + static void iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer) { struct iris_context *ice = (struct iris_context *)ctx; struct iris_transfer *map = (void *) xfer; struct iris_resource *res = (struct iris_resource *) xfer->resource; - struct isl_surf *surf = &res->surf; if (map->unmap) map->unmap(map); - /* XXX: big ol' hack! need to re-emit UBOs. want bind_history? */ - if (surf->tiling == ISL_TILING_LINEAR) { - ice->state.dirty |= IRIS_DIRTY_CONSTANTS_VS | IRIS_DIRTY_BINDINGS_VS - | IRIS_DIRTY_CONSTANTS_TCS | IRIS_DIRTY_BINDINGS_TCS - | IRIS_DIRTY_CONSTANTS_TES | IRIS_DIRTY_BINDINGS_TES - | IRIS_DIRTY_CONSTANTS_GS | IRIS_DIRTY_BINDINGS_GS - | IRIS_DIRTY_CONSTANTS_FS | IRIS_DIRTY_BINDINGS_FS; + for (int i = 0; i < IRIS_BATCH_COUNT; i++) { + if (ice->batches[i].contains_draw || + ice->batches[i].cache.render->entries) { + iris_batch_maybe_flush(&ice->batches[i], 24); + iris_flush_and_dirty_for_history(ice, &ice->batches[i], res); + } } pipe_resource_reference(&xfer->resource, NULL); @@ -892,6 +1197,50 @@ iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource) { } +void +iris_flush_and_dirty_for_history(struct iris_context *ice, + struct iris_batch *batch, + struct iris_resource *res) +{ + if (res->base.target != PIPE_BUFFER) + return; + + unsigned flush = PIPE_CONTROL_CS_STALL; + + /* We've likely used the rendering engine (i.e. BLORP) to write to this + * surface. Flush the render cache so the data actually lands. + */ + if (batch->name != IRIS_BATCH_COMPUTE) + flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + + uint64_t dirty = 0ull; + + if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) { + flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE | + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + dirty |= IRIS_DIRTY_CONSTANTS_VS | + IRIS_DIRTY_CONSTANTS_TCS | + IRIS_DIRTY_CONSTANTS_TES | + IRIS_DIRTY_CONSTANTS_GS | + IRIS_DIRTY_CONSTANTS_FS | + IRIS_DIRTY_CONSTANTS_CS | + IRIS_ALL_DIRTY_BINDINGS; + } + + if (res->bind_history & PIPE_BIND_SAMPLER_VIEW) + flush |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; + + if (res->bind_history & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER)) + flush |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + + if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE)) + flush |= PIPE_CONTROL_DATA_CACHE_FLUSH; + + iris_emit_pipe_control_flush(batch, flush); + + ice->state.dirty |= dirty; +} + static enum pipe_format iris_resource_get_internal_format(struct pipe_resource *p_res) { @@ -904,7 +1253,7 @@ static const struct u_transfer_vtbl transfer_vtbl = { .resource_destroy = iris_resource_destroy, .transfer_map = iris_transfer_map, .transfer_unmap = iris_transfer_unmap, - .transfer_flush_region = u_default_transfer_flush_region, + .transfer_flush_region = iris_transfer_flush_region, .get_internal_format = iris_resource_get_internal_format, .set_stencil = iris_resource_set_separate_stencil, .get_stencil = iris_resource_get_separate_stencil,