X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_resource.c;h=a8d0291862ebdc5eb80eba7125f1181ee004654c;hb=f58e0405b6ca15d9b82122d82311e8b82f4a0939;hp=971e7adda7eeeacd744f4257f6a26bd2311bf1d0;hpb=ddd716e746767d2ec8599c0ad623c582ba46e5d1;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index 971e7adda7e..a8d0291862e 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -70,15 +70,29 @@ static const uint64_t priority_to_modifier[] = { static bool modifier_is_supported(const struct gen_device_info *devinfo, - uint64_t modifier) + enum pipe_format pfmt, uint64_t modifier) { /* XXX: do something real */ switch (modifier) { + case I915_FORMAT_MOD_Y_TILED_CCS: { + if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) + return false; + + enum isl_format rt_format = + iris_format_for_usage(devinfo, pfmt, + ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt; + + enum isl_format linear_format = isl_format_srgb_to_linear(rt_format); + + if (!isl_format_supports_ccs_e(devinfo, linear_format)) + return false; + + return true; + } case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_X_TILED: case DRM_FORMAT_MOD_LINEAR: return true; - case I915_FORMAT_MOD_Y_TILED_CCS: case DRM_FORMAT_MOD_INVALID: default: return false; @@ -86,14 +100,14 @@ modifier_is_supported(const struct gen_device_info *devinfo, } static uint64_t -select_best_modifier(struct gen_device_info *devinfo, +select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt, const uint64_t *modifiers, int count) { enum modifier_priority prio = MODIFIER_PRIORITY_INVALID; for (int i = 0; i < count; i++) { - if (!modifier_is_supported(devinfo, modifiers[i])) + if (!modifier_is_supported(devinfo, pfmt, modifiers[i])) continue; switch (modifiers[i]) { @@ -118,7 +132,7 @@ select_best_modifier(struct gen_device_info *devinfo, return priority_to_modifier[prio]; } -static enum isl_surf_dim +enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target) { switch (target) { @@ -155,13 +169,13 @@ iris_query_dmabuf_modifiers(struct pipe_screen *pscreen, DRM_FORMAT_MOD_LINEAR, I915_FORMAT_MOD_X_TILED, I915_FORMAT_MOD_Y_TILED, - // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, }; int supported_mods = 0; for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) { - if (!modifier_is_supported(devinfo, all_modifiers[i])) + if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i])) continue; if (supported_mods < max) { @@ -204,7 +218,11 @@ iris_resource_get_separate_stencil(struct pipe_resource *p_res) /* For packed depth-stencil, we treat depth as the primary resource * and store S8 as the "second plane" resource. */ - return p_res->next; + if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT) + return p_res->next; + + return NULL; + } static void @@ -235,6 +253,35 @@ iris_get_depth_stencil_resources(struct pipe_resource *res, } } +enum isl_dim_layout +iris_get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, + enum pipe_texture_target target) +{ + switch (target) { + case PIPE_TEXTURE_1D: + case PIPE_TEXTURE_1D_ARRAY: + return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ? + ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); + + case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_2D_ARRAY: + case PIPE_TEXTURE_RECT: + case PIPE_TEXTURE_CUBE: + case PIPE_TEXTURE_CUBE_ARRAY: + return ISL_DIM_LAYOUT_GEN4_2D; + + case PIPE_TEXTURE_3D: + return (devinfo->gen >= 9 ? + ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D); + + case PIPE_MAX_TEXTURE_TYPES: + case PIPE_BUFFER: + break; + } + unreachable("invalid texture type"); +} + void iris_resource_disable_aux(struct iris_resource *res) { @@ -330,31 +377,39 @@ create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial) return per_level_arr; } +static unsigned +iris_get_aux_clear_color_state_size(struct iris_screen *screen) +{ + const struct gen_device_info *devinfo = &screen->devinfo; + return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0; +} + /** - * Allocate the initial aux surface for a resource based on aux.usage + * Configure aux for the resource, but don't allocate it. For images which + * might be shared with modifiers, we must allocate the image and aux data in + * a single bo. */ static bool -iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) +iris_resource_configure_aux(struct iris_screen *screen, + struct iris_resource *res, bool imported, + uint64_t *aux_size_B, + uint32_t *alloc_flags) { struct isl_device *isl_dev = &screen->isl_dev; enum isl_aux_state initial_state; UNUSED bool ok = false; - uint8_t memset_value = 0; - uint32_t alloc_flags = 0; - const struct gen_device_info *devinfo = &screen->devinfo; - const unsigned clear_color_state_size = devinfo->gen >= 10 ? - screen->isl_dev.ss.clear_color_state_size : - (devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0); + *aux_size_B = 0; + *alloc_flags = 0; assert(!res->aux.bo); switch (res->aux.usage) { case ISL_AUX_USAGE_NONE: res->aux.surf.size_B = 0; + ok = true; break; case ISL_AUX_USAGE_HIZ: initial_state = ISL_AUX_STATE_AUX_INVALID; - memset_value = 0; ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf); break; case ISL_AUX_USAGE_MCS: @@ -368,7 +423,6 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) * 1's, so we simply memset it to 0xff. */ initial_state = ISL_AUX_STATE_CLEAR; - memset_value = 0xFF; ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf); break; case ISL_AUX_USAGE_CCS_D: @@ -386,23 +440,30 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) * For CCS_D, do the same thing. On Gen9+, this avoids having any * undefined bits in the aux buffer. */ - initial_state = ISL_AUX_STATE_PASS_THROUGH; - alloc_flags |= BO_ALLOC_ZEROED; + if (imported) + initial_state = + isl_drm_modifier_get_default_aux_state(res->mod_info->modifier); + else + initial_state = ISL_AUX_STATE_PASS_THROUGH; + *alloc_flags |= BO_ALLOC_ZEROED; ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0); break; } + /* We should have a valid aux_surf. */ + if (!ok) + return false; + /* No work is needed for a zero-sized auxiliary buffer. */ if (res->aux.surf.size_B == 0) return true; - /* Assert that ISL gave us a valid aux surf */ - assert(ok); - - /* Create the aux_state for the auxiliary buffer. */ - res->aux.state = create_aux_state_map(res, initial_state); - if (!res->aux.state) - return false; + if (!res->aux.state) { + /* Create the aux_state for the auxiliary buffer. */ + res->aux.state = create_aux_state_map(res, initial_state); + if (!res->aux.state) + return false; + } uint64_t size = res->aux.surf.size_B; @@ -413,20 +474,32 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) * anyways, and copy it back to the surface state during state emission. */ res->aux.clear_color_offset = size; - size += clear_color_state_size; + size += iris_get_aux_clear_color_state_size(screen); + *aux_size_B = size; - /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules - * the drm allocator. Therefore, one can pass the ISL dimensions in terms - * of bytes instead of trying to recalculate based on different format - * block sizes. - */ - res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, - IRIS_MEMZONE_OTHER, I915_TILING_Y, - res->aux.surf.row_pitch_B, alloc_flags); - if (!res->aux.bo) { - return false; + if (res->aux.usage == ISL_AUX_USAGE_HIZ) { + for (unsigned level = 0; level < res->surf.levels; ++level) { + uint32_t width = u_minify(res->surf.phys_level0_sa.width, level); + uint32_t height = u_minify(res->surf.phys_level0_sa.height, level); + + /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned. + * For LOD == 0, we can grow the dimensions to make it work. + */ + if (level == 0 || ((width & 7) == 0 && (height & 3) == 0)) + res->aux.has_hiz |= 1 << level; + } } + return true; +} + +/** + * Initialize the aux buffer contents. + */ +static bool +iris_resource_init_aux_buf(struct iris_resource *res, uint32_t alloc_flags, + unsigned clear_color_state_size) +{ if (!(alloc_flags & BO_ALLOC_ZEROED)) { void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW); @@ -435,8 +508,11 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) return false; } - if (memset_value != 0) - memset(map, memset_value, res->aux.surf.size_B); + if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) { + uint8_t memset_value = res->aux.usage == ISL_AUX_USAGE_MCS ? 0xFF : 0; + memset((char*)map + res->aux.offset, memset_value, + res->aux.surf.size_B); + } /* Zero the indirect clear color to match ::fast_clear_color. */ memset((char *)map + res->aux.clear_color_offset, 0, @@ -450,22 +526,81 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) iris_bo_reference(res->aux.clear_color_bo); } - if (res->aux.usage == ISL_AUX_USAGE_HIZ) { - for (unsigned level = 0; level < res->surf.levels; ++level) { - uint32_t width = u_minify(res->surf.phys_level0_sa.width, level); - uint32_t height = u_minify(res->surf.phys_level0_sa.height, level); + return true; +} - /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned. - * For LOD == 0, we can grow the dimensions to make it work. - */ - if (level == 0 || ((width & 7) == 0 && (height & 3) == 0)) - res->aux.has_hiz |= 1 << level; - } +/** + * Allocate the initial aux surface for a resource based on aux.usage + */ +static bool +iris_resource_alloc_separate_aux(struct iris_screen *screen, + struct iris_resource *res) +{ + uint32_t alloc_flags; + uint64_t size; + if (!iris_resource_configure_aux(screen, res, false, &size, &alloc_flags)) + return false; + + if (size == 0) + return true; + + /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules + * the drm allocator. Therefore, one can pass the ISL dimensions in terms + * of bytes instead of trying to recalculate based on different format + * block sizes. + */ + res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, 4096, + IRIS_MEMZONE_OTHER, I915_TILING_Y, + res->aux.surf.row_pitch_B, alloc_flags); + if (!res->aux.bo) { + return false; } + if (!iris_resource_init_aux_buf(res, alloc_flags, + iris_get_aux_clear_color_state_size(screen))) + return false; + return true; } +void +iris_resource_finish_aux_import(struct pipe_screen *pscreen, + struct iris_resource *res) +{ + struct iris_screen *screen = (struct iris_screen *)pscreen; + assert(iris_resource_unfinished_aux_import(res)); + assert(!res->mod_info->supports_clear_color); + + struct iris_resource *aux_res = (void *) res->base.next; + assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset && + aux_res->aux.bo); + + assert(res->bo == aux_res->aux.bo); + iris_bo_reference(aux_res->aux.bo); + res->aux.bo = aux_res->aux.bo; + + res->aux.offset = aux_res->aux.offset; + + assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B)); + assert(res->aux.clear_color_bo == NULL); + res->aux.clear_color_offset = 0; + + assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B); + + unsigned clear_color_state_size = + iris_get_aux_clear_color_state_size(screen); + + if (clear_color_state_size > 0) { + res->aux.clear_color_bo = + iris_bo_alloc(screen->bufmgr, "clear color buffer", + clear_color_state_size, IRIS_MEMZONE_OTHER); + res->aux.clear_color_offset = 0; + } + + iris_resource_destroy(&screen->base, res->base.next); + res->base.next = NULL; +} + static bool supports_mcs(const struct isl_surf *surf) { @@ -473,10 +608,6 @@ supports_mcs(const struct isl_surf *surf) if (surf->samples <= 1) return false; - /* See isl_surf_get_mcs_surf for details. */ - if (surf->samples == 16 && surf->logical_level0_px.width > 8192) - return false; - /* Depth and stencil buffers use the IMS (interleaved) layout. */ if (isl_surf_usage_is_depth_or_stencil(surf->usage)) return false; @@ -488,21 +619,10 @@ static bool supports_ccs(const struct gen_device_info *devinfo, const struct isl_surf *surf) { - /* Gen9+ only supports CCS for Y-tiled buffers. */ - if (surf->tiling != ISL_TILING_Y0) - return false; - /* CCS only supports singlesampled resources. */ if (surf->samples > 1) return false; - /* The PRM doesn't say this explicitly, but fast-clears don't appear to - * work for 3D textures until Gen9 where the layout of 3D textures changes - * to match 2D array textures. - */ - if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D) - return false; - /* Note: still need to check the format! */ return true; @@ -563,7 +683,7 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, util_format_description(templ->format); const bool has_depth = util_format_has_depth(format_desc); uint64_t modifier = - select_best_modifier(devinfo, modifiers, modifiers_count); + select_best_modifier(devinfo, templ->format, modifiers, modifiers_count); isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; @@ -675,16 +795,53 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, IRIS_RESOURCE_FLAG_SURFACE_MEMZONE | IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE))); - res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B, - memzone, + uint32_t aux_preferred_alloc_flags; + uint64_t aux_size = 0; + bool aux_enabled = + iris_resource_configure_aux(screen, res, false, &aux_size, + &aux_preferred_alloc_flags); + aux_enabled = aux_enabled && res->aux.surf.size_B > 0; + const bool separate_aux = aux_enabled && !res->mod_info; + uint64_t aux_offset; + uint64_t bo_size; + + if (aux_enabled && !separate_aux) { + /* Allocate aux data with main surface. This is required for modifiers + * with aux data (ccs). + */ + aux_offset = ALIGN(res->surf.size_B, res->aux.surf.alignment_B); + bo_size = aux_offset + aux_size; + } else { + aux_offset = 0; + bo_size = res->surf.size_B; + } + + res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, 4096, memzone, isl_tiling_to_i915_tiling(res->surf.tiling), res->surf.row_pitch_B, flags); if (!res->bo) goto fail; - if (!iris_resource_alloc_aux(screen, res)) - goto fail; + if (aux_enabled) { + if (separate_aux) { + if (!iris_resource_alloc_separate_aux(screen, res)) + aux_enabled = false; + } else { + res->aux.bo = res->bo; + iris_bo_reference(res->aux.bo); + res->aux.offset += aux_offset; + unsigned clear_color_state_size = + iris_get_aux_clear_color_state_size(screen); + if (clear_color_state_size > 0) + res->aux.clear_color_offset += aux_offset; + if (!iris_resource_init_aux_buf(res, flags, clear_color_state_size)) + aux_enabled = false; + } + } + + if (!aux_enabled) + iris_resource_disable_aux(res); return &res->base; @@ -791,26 +948,57 @@ iris_resource_from_handle(struct pipe_screen *pscreen, if (templ->target == PIPE_BUFFER) { res->surf.tiling = ISL_TILING_LINEAR; } else { - isl_surf_init(&screen->isl_dev, &res->surf, - .dim = target_to_isl_surf_dim(templ->target), - .format = fmt.fmt, - .width = templ->width0, - .height = templ->height0, - .depth = templ->depth0, - .levels = templ->last_level + 1, - .array_len = templ->array_size, - .samples = MAX2(templ->nr_samples, 1), - .min_alignment_B = 0, - .row_pitch_B = whandle->stride, - .usage = isl_usage, - .tiling_flags = 1 << res->mod_info->tiling); - - assert(res->bo->tiling_mode == - isl_tiling_to_i915_tiling(res->surf.tiling)); - - // XXX: create_ccs_buf_for_image? - if (!iris_resource_alloc_aux(screen, res)) - goto fail; + if (whandle->modifier == DRM_FORMAT_MOD_INVALID || whandle->plane == 0) { + UNUSED const bool isl_surf_created_successfully = + isl_surf_init(&screen->isl_dev, &res->surf, + .dim = target_to_isl_surf_dim(templ->target), + .format = fmt.fmt, + .width = templ->width0, + .height = templ->height0, + .depth = templ->depth0, + .levels = templ->last_level + 1, + .array_len = templ->array_size, + .samples = MAX2(templ->nr_samples, 1), + .min_alignment_B = 0, + .row_pitch_B = whandle->stride, + .usage = isl_usage, + .tiling_flags = 1 << res->mod_info->tiling); + assert(isl_surf_created_successfully); + assert(res->bo->tiling_mode == + isl_tiling_to_i915_tiling(res->surf.tiling)); + + // XXX: create_ccs_buf_for_image? + if (whandle->modifier == DRM_FORMAT_MOD_INVALID) { + if (!iris_resource_alloc_separate_aux(screen, res)) + goto fail; + } else { + if (res->mod_info->aux_usage != ISL_AUX_USAGE_NONE) { + uint32_t alloc_flags; + uint64_t size; + res->aux.usage = res->mod_info->aux_usage; + res->aux.possible_usages = 1 << res->mod_info->aux_usage; + res->aux.sampler_usages = res->aux.possible_usages; + bool ok = iris_resource_configure_aux(screen, res, true, &size, + &alloc_flags); + assert(ok); + /* The gallium dri layer will create a separate plane resource + * for the aux image. iris_resource_finish_aux_import will + * merge the separate aux parameters back into a single + * iris_resource. + */ + } + } + } else { + /* Save modifier import information to reconstruct later. After + * import, this will be available under a second image accessible + * from the main image with res->base.next. See + * iris_resource_finish_aux_import. + */ + res->aux.surf.row_pitch_B = whandle->stride; + res->aux.offset = whandle->offset; + res->aux.bo = res->bo; + res->bo = NULL; + } } return &res->base; @@ -835,7 +1023,54 @@ iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource) mod ? mod->supports_clear_color : false); } -static boolean +static bool +iris_resource_get_param(struct pipe_screen *screen, + struct pipe_resource *resource, + unsigned int plane, + enum pipe_resource_param param, + uint64_t *value) +{ + struct iris_resource *res = (struct iris_resource *)resource; + bool mod_with_aux = + res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; + bool wants_aux = mod_with_aux && plane > 0; + struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo; + bool result; + unsigned handle; + + switch (param) { + case PIPE_RESOURCE_PARAM_NPLANES: + *value = mod_with_aux ? 2 : 1; + return true; + case PIPE_RESOURCE_PARAM_STRIDE: + *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B; + return true; + case PIPE_RESOURCE_PARAM_OFFSET: + *value = wants_aux ? res->aux.offset : 0; + return true; + case PIPE_RESOURCE_PARAM_MODIFIER: + *value = res->mod_info ? res->mod_info->modifier : + tiling_to_modifier(res->bo->tiling_mode); + return true; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED: + result = iris_bo_flink(bo, &handle) == 0; + if (result) + *value = handle; + return result; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: + *value = iris_bo_export_gem_handle(bo); + return true; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD: + result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0; + if (result) + *value = handle; + return result; + default: + return false; + } +} + +static bool iris_resource_get_handle(struct pipe_screen *pscreen, struct pipe_context *ctx, struct pipe_resource *resource, @@ -843,17 +1078,30 @@ iris_resource_get_handle(struct pipe_screen *pscreen, unsigned usage) { struct iris_resource *res = (struct iris_resource *)resource; + bool mod_with_aux = + res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; - /* Disable aux usage if explicit flush not set and this is the - * first time we are dealing with this resource. + /* Disable aux usage if explicit flush not set and this is the first time + * we are dealing with this resource and the resource was not created with + * a modifier with aux. */ - if ((!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0)) { - if (p_atomic_read(&resource->reference.count) == 1) + if (!mod_with_aux && + (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) && + p_atomic_read(&resource->reference.count) == 1) { iris_resource_disable_aux(res); } - /* If this is a buffer, stride should be 0 - no need to special case */ - whandle->stride = res->surf.row_pitch_B; + struct iris_bo *bo; + if (mod_with_aux && whandle->plane > 0) { + assert(res->aux.bo); + bo = res->aux.bo; + whandle->stride = res->aux.surf.row_pitch_B; + whandle->offset = res->aux.offset; + } else { + /* If this is a buffer, stride should be 0 - no need to special case */ + whandle->stride = res->surf.row_pitch_B; + bo = res->bo; + } whandle->modifier = res->mod_info ? res->mod_info->modifier : tiling_to_modifier(res->bo->tiling_mode); @@ -871,12 +1119,12 @@ iris_resource_get_handle(struct pipe_screen *pscreen, switch (whandle->type) { case WINSYS_HANDLE_TYPE_SHARED: - return iris_bo_flink(res->bo, &whandle->handle) == 0; + return iris_bo_flink(bo, &whandle->handle) == 0; case WINSYS_HANDLE_TYPE_KMS: - whandle->handle = iris_bo_export_gem_handle(res->bo); + whandle->handle = iris_bo_export_gem_handle(bo); return true; case WINSYS_HANDLE_TYPE_FD: - return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0; + return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0; } return false; @@ -999,6 +1247,7 @@ iris_map_copy_region(struct iris_transfer *map) .nr_samples = xfer->resource->nr_samples, .nr_storage_samples = xfer->resource->nr_storage_samples, .array_size = box->depth, + .format = res->internal_format, }; if (xfer->resource->target == PIPE_BUFFER) @@ -1008,22 +1257,6 @@ iris_map_copy_region(struct iris_transfer *map) else templ.target = PIPE_TEXTURE_2D; - /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use - * xfer->resource->format directly. Pick a bpb compatible format so - * resource creation will succeed; blorp_copy will override it anyway. - */ - switch (util_format_get_blocksizebits(res->internal_format)) { - case 8: templ.format = PIPE_FORMAT_R8_UINT; break; - case 16: templ.format = PIPE_FORMAT_R8G8_UINT; break; - case 24: templ.format = PIPE_FORMAT_R8G8B8_UINT; break; - case 32: templ.format = PIPE_FORMAT_R8G8B8A8_UINT; break; - case 48: templ.format = PIPE_FORMAT_R16G16B16_UINT; break; - case 64: templ.format = PIPE_FORMAT_R16G16B16A16_UINT; break; - case 96: templ.format = PIPE_FORMAT_R32G32B32_UINT; break; - case 128: templ.format = PIPE_FORMAT_R32G32B32A32_UINT; break; - default: unreachable("Invalid bpb"); - } - map->staging = iris_resource_create(pscreen, &templ); assert(map->staging); @@ -1038,6 +1271,7 @@ iris_map_copy_region(struct iris_transfer *map) xfer->resource, xfer->level, box); /* Ensure writes to the staging BO land before we map it below. */ iris_emit_pipe_control_flush(map->batch, + "transfer read: flush before mapping", PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); } @@ -1064,6 +1298,109 @@ get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z, } } +/** + * This function computes the tile_w (in bytes) and tile_h (in rows) of + * different tiling patterns. + */ +static void +iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, + uint32_t *tile_w, uint32_t *tile_h) +{ + switch (tiling) { + case ISL_TILING_X: + *tile_w = 512; + *tile_h = 8; + break; + case ISL_TILING_Y0: + *tile_w = 128; + *tile_h = 32; + break; + case ISL_TILING_LINEAR: + *tile_w = cpp; + *tile_h = 1; + break; + default: + unreachable("not reached"); + } + +} + +/** + * This function computes masks that may be used to select the bits of the X + * and Y coordinates that indicate the offset within a tile. If the BO is + * untiled, the masks are set to 0. + */ +static void +iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, + uint32_t *mask_x, uint32_t *mask_y) +{ + uint32_t tile_w_bytes, tile_h; + + iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h); + + *mask_x = tile_w_bytes / cpp - 1; + *mask_y = tile_h - 1; +} + +/** + * Compute the offset (in bytes) from the start of the BO to the given x + * and y coordinate. For tiled BOs, caller must ensure that x and y are + * multiples of the tile size. + */ +static uint32_t +iris_resource_get_aligned_offset(const struct iris_resource *res, + uint32_t x, uint32_t y) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format); + unsigned cpp = fmtl->bpb / 8; + uint32_t pitch = res->surf.row_pitch_B; + + switch (res->surf.tiling) { + default: + unreachable("not reached"); + case ISL_TILING_LINEAR: + return y * pitch + x * cpp; + case ISL_TILING_X: + assert((x % (512 / cpp)) == 0); + assert((y % 8) == 0); + return y * pitch + x / (512 / cpp) * 4096; + case ISL_TILING_Y0: + assert((x % (128 / cpp)) == 0); + assert((y % 32) == 0); + return y * pitch + x / (128 / cpp) * 4096; + } +} + +/** + * Rendering with tiled buffers requires that the base address of the buffer + * be aligned to a page boundary. For renderbuffers, and sometimes with + * textures, we may want the surface to point at a texture image level that + * isn't at a page boundary. + * + * This function returns an appropriately-aligned base offset + * according to the tiling restrictions, plus any required x/y offset + * from there. + */ +uint32_t +iris_resource_get_tile_offsets(const struct iris_resource *res, + uint32_t level, uint32_t z, + uint32_t *tile_x, uint32_t *tile_y) +{ + uint32_t x, y; + uint32_t mask_x, mask_y; + + const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format); + const unsigned cpp = fmtl->bpb / 8; + + iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y); + get_image_offset_el(&res->surf, level, z, &x, &y); + + *tile_x = x & mask_x; + *tile_y = y & mask_y; + + return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y); +} + /** * Get pointer offset into stencil buffer. * @@ -1283,7 +1620,6 @@ iris_map_tiled_memcpy(struct iris_transfer *map) const bool has_swizzling = false; - // XXX: PIPE_TRANSFER_READ? if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) { char *src = iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS); @@ -1371,21 +1707,29 @@ iris_transfer_map(struct pipe_context *ctx, usage |= PIPE_TRANSFER_DISCARD_RANGE; } - bool map_would_stall = false; - - if (resource->target != PIPE_BUFFER) { - iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res, - level, box->z, box->depth, - usage & PIPE_TRANSFER_WRITE); - } - if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) && can_promote_to_async(res, box, usage)) { usage |= PIPE_TRANSFER_UNSYNCHRONIZED; } + bool need_resolve = false; + bool need_color_resolve = false; + + if (resource->target != PIPE_BUFFER) { + bool need_hiz_resolve = iris_resource_level_has_hiz(res, level); + + need_color_resolve = + (res->aux.usage == ISL_AUX_USAGE_CCS_D || + res->aux.usage == ISL_AUX_USAGE_CCS_E) && + iris_has_color_unresolved(res, level, 1, box->z, box->depth); + + need_resolve = need_color_resolve || need_hiz_resolve; + } + + bool map_would_stall = false; + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { - map_would_stall = resource_is_busy(ice, res); + map_would_stall = need_resolve || resource_is_busy(ice, res); if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) @@ -1433,21 +1777,29 @@ iris_transfer_map(struct pipe_context *ctx, * temporary and map that, to avoid the resolve. (It might be better to * a tiled temporary and use the tiled_memcpy paths...) */ - if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && - res->aux.usage != ISL_AUX_USAGE_CCS_E && - res->aux.usage != ISL_AUX_USAGE_CCS_D) { + if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && !need_color_resolve) + no_gpu = true; + + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + if (fmtl->txc == ISL_TXC_ASTC) no_gpu = true; - } if ((map_would_stall || res->aux.usage == ISL_AUX_USAGE_CCS_E) && !no_gpu) { - /* If we need a synchronous mapping and the resource is busy, - * we copy to/from a linear temporary buffer using the GPU. + /* If we need a synchronous mapping and the resource is busy, or needs + * resolving, we copy to/from a linear temporary buffer using the GPU. */ map->batch = &ice->batches[IRIS_BATCH_RENDER]; map->blorp = &ice->blorp; iris_map_copy_region(map); } else { - /* Otherwise we're free to map on the CPU. Flush if needed. */ + /* Otherwise we're free to map on the CPU. */ + + if (need_resolve) { + iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res, + level, box->z, box->depth, + usage & PIPE_TRANSFER_WRITE); + } + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { for (int i = 0; i < IRIS_BATCH_COUNT; i++) { if (iris_batch_references(&ice->batches[i], res->bo)) @@ -1480,11 +1832,22 @@ iris_transfer_flush_region(struct pipe_context *ctx, if (map->staging) iris_flush_staging_region(xfer, box); - for (int i = 0; i < IRIS_BATCH_COUNT; i++) { - if (ice->batches[i].contains_draw || - ice->batches[i].cache.render->entries) { - iris_batch_maybe_flush(&ice->batches[i], 24); - iris_flush_and_dirty_for_history(ice, &ice->batches[i], res); + uint32_t history_flush = 0; + + if (res->base.target == PIPE_BUFFER) { + history_flush |= iris_flush_bits_for_history(res) | + (map->staging ? PIPE_CONTROL_RENDER_TARGET_FLUSH : 0); + } + + if (history_flush & ~PIPE_CONTROL_CS_STALL) { + for (int i = 0; i < IRIS_BATCH_COUNT; i++) { + struct iris_batch *batch = &ice->batches[i]; + if (batch->contains_draw || batch->cache.render->entries) { + iris_batch_maybe_flush(batch, 24); + iris_emit_pipe_control_flush(batch, + "cache history: transfer flush", + history_flush); + } } } @@ -1568,20 +1931,18 @@ iris_flush_bits_for_history(struct iris_resource *res) void iris_flush_and_dirty_for_history(struct iris_context *ice, struct iris_batch *batch, - struct iris_resource *res) + struct iris_resource *res, + uint32_t extra_flags, + const char *reason) { if (res->base.target != PIPE_BUFFER) return; - uint32_t flush = iris_flush_bits_for_history(res); + uint32_t flush = iris_flush_bits_for_history(res) | extra_flags; - /* We've likely used the rendering engine (i.e. BLORP) to write to this - * surface. Flush the render cache so the data actually lands. - */ - if (batch->name != IRIS_BATCH_COMPUTE) - flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + iris_emit_pipe_control_flush(batch, reason, flush); - iris_emit_pipe_control_flush(batch, flush); + iris_dirty_for_history(ice, res); } bool @@ -1639,6 +2000,7 @@ iris_init_screen_resource_functions(struct pipe_screen *pscreen) pscreen->resource_from_user_memory = iris_resource_from_user_memory; pscreen->resource_from_handle = iris_resource_from_handle; pscreen->resource_get_handle = iris_resource_get_handle; + pscreen->resource_get_param = iris_resource_get_param; pscreen->resource_destroy = u_transfer_helper_resource_destroy; pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl, true, true, false, true);