X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_resource.c;h=ed24d629fe5e464021411920a9d30fb33b37d2c9;hb=dcb4230e5e51c1f2ff84c436134c231996af85e9;hp=c16fc8eb0158519863ba85d56e3fa6c007c00085;hpb=7339660e80331ed773fc6dbb8295384d4ef6954e;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_resource.c b/src/gallium/drivers/iris/iris_resource.c index c16fc8eb015..ed24d629fe5 100644 --- a/src/gallium/drivers/iris/iris_resource.c +++ b/src/gallium/drivers/iris/iris_resource.c @@ -37,7 +37,8 @@ #include "util/os_memory.h" #include "util/u_cpu_detect.h" #include "util/u_inlines.h" -#include "util/u_format.h" +#include "util/format/u_format.h" +#include "util/u_threaded_context.h" #include "util/u_transfer.h" #include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" @@ -46,7 +47,8 @@ #include "iris_context.h" #include "iris_resource.h" #include "iris_screen.h" -#include "intel/common/gen_debug.h" +#include "intel/common/gen_aux_map.h" +#include "intel/dev/gen_debug.h" #include "isl/isl.h" #include "drm-uapi/drm_fourcc.h" #include "drm-uapi/i915_drm.h" @@ -69,15 +71,29 @@ static const uint64_t priority_to_modifier[] = { static bool modifier_is_supported(const struct gen_device_info *devinfo, - uint64_t modifier) + enum pipe_format pfmt, uint64_t modifier) { /* XXX: do something real */ switch (modifier) { + case I915_FORMAT_MOD_Y_TILED_CCS: { + if (unlikely(INTEL_DEBUG & DEBUG_NO_RBC)) + return false; + + enum isl_format rt_format = + iris_format_for_usage(devinfo, pfmt, + ISL_SURF_USAGE_RENDER_TARGET_BIT).fmt; + + enum isl_format linear_format = isl_format_srgb_to_linear(rt_format); + + if (!isl_format_supports_ccs_e(devinfo, linear_format)) + return false; + + return devinfo->gen >= 9 && devinfo->gen <= 11; + } case I915_FORMAT_MOD_Y_TILED: case I915_FORMAT_MOD_X_TILED: case DRM_FORMAT_MOD_LINEAR: return true; - case I915_FORMAT_MOD_Y_TILED_CCS: case DRM_FORMAT_MOD_INVALID: default: return false; @@ -85,14 +101,14 @@ modifier_is_supported(const struct gen_device_info *devinfo, } static uint64_t -select_best_modifier(struct gen_device_info *devinfo, +select_best_modifier(struct gen_device_info *devinfo, enum pipe_format pfmt, const uint64_t *modifiers, int count) { enum modifier_priority prio = MODIFIER_PRIORITY_INVALID; for (int i = 0; i < count; i++) { - if (!modifier_is_supported(devinfo, modifiers[i])) + if (!modifier_is_supported(devinfo, pfmt, modifiers[i])) continue; switch (modifiers[i]) { @@ -117,7 +133,7 @@ select_best_modifier(struct gen_device_info *devinfo, return priority_to_modifier[prio]; } -static enum isl_surf_dim +enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target) { switch (target) { @@ -154,13 +170,13 @@ iris_query_dmabuf_modifiers(struct pipe_screen *pscreen, DRM_FORMAT_MOD_LINEAR, I915_FORMAT_MOD_X_TILED, I915_FORMAT_MOD_Y_TILED, - // XXX: (broken) I915_FORMAT_MOD_Y_TILED_CCS, + I915_FORMAT_MOD_Y_TILED_CCS, }; int supported_mods = 0; for (int i = 0; i < ARRAY_SIZE(all_modifiers); i++) { - if (!modifier_is_supported(devinfo, all_modifiers[i])) + if (!modifier_is_supported(devinfo, pfmt, all_modifiers[i])) continue; if (supported_mods < max) { @@ -203,7 +219,11 @@ iris_resource_get_separate_stencil(struct pipe_resource *p_res) /* For packed depth-stencil, we treat depth as the primary resource * and store S8 as the "second plane" resource. */ - return p_res->next; + if (p_res->next && p_res->next->format == PIPE_FORMAT_S8_UINT) + return p_res->next; + + return NULL; + } static void @@ -234,6 +254,35 @@ iris_get_depth_stencil_resources(struct pipe_resource *res, } } +enum isl_dim_layout +iris_get_isl_dim_layout(const struct gen_device_info *devinfo, + enum isl_tiling tiling, + enum pipe_texture_target target) +{ + switch (target) { + case PIPE_TEXTURE_1D: + case PIPE_TEXTURE_1D_ARRAY: + return (devinfo->gen >= 9 && tiling == ISL_TILING_LINEAR ? + ISL_DIM_LAYOUT_GEN9_1D : ISL_DIM_LAYOUT_GEN4_2D); + + case PIPE_TEXTURE_2D: + case PIPE_TEXTURE_2D_ARRAY: + case PIPE_TEXTURE_RECT: + case PIPE_TEXTURE_CUBE: + case PIPE_TEXTURE_CUBE_ARRAY: + return ISL_DIM_LAYOUT_GEN4_2D; + + case PIPE_TEXTURE_3D: + return (devinfo->gen >= 9 ? + ISL_DIM_LAYOUT_GEN4_2D : ISL_DIM_LAYOUT_GEN4_3D); + + case PIPE_MAX_TEXTURE_TYPES: + case PIPE_BUFFER: + break; + } + unreachable("invalid texture type"); +} + void iris_resource_disable_aux(struct iris_resource *res) { @@ -244,8 +293,10 @@ iris_resource_disable_aux(struct iris_resource *res) res->aux.usage = ISL_AUX_USAGE_NONE; res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE; res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE; + res->aux.has_hiz = 0; res->aux.surf.size_B = 0; res->aux.bo = NULL; + res->aux.extra_aux.surf.size_B = 0; res->aux.clear_color_bo = NULL; res->aux.state = NULL; } @@ -256,6 +307,9 @@ iris_resource_destroy(struct pipe_screen *screen, { struct iris_resource *res = (struct iris_resource *)resource; + if (resource->target == PIPE_BUFFER) + util_range_destroy(&res->valid_buffer_range); + iris_resource_disable_aux(res); iris_bo_unreference(res->bo); @@ -277,6 +331,9 @@ iris_alloc_resource(struct pipe_screen *pscreen, res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE; res->aux.sampler_usages = 1 << ISL_AUX_USAGE_NONE; + if (templ->target == PIPE_BUFFER) + util_range_init(&res->valid_buffer_range); + return res; } @@ -292,6 +349,8 @@ iris_get_num_logical_layers(const struct iris_resource *res, unsigned level) static enum isl_aux_state ** create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial) { + assert(res->aux.state == NULL); + uint32_t total_slices = 0; for (uint32_t level = 0; level < res->surf.levels; level++) total_slices += iris_get_num_logical_layers(res, level); @@ -323,34 +382,144 @@ create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial) return per_level_arr; } +static unsigned +iris_get_aux_clear_color_state_size(struct iris_screen *screen) +{ + const struct gen_device_info *devinfo = &screen->devinfo; + return devinfo->gen >= 10 ? screen->isl_dev.ss.clear_color_state_size : 0; +} + +static void +map_aux_addresses(struct iris_screen *screen, struct iris_resource *res) +{ + const struct gen_device_info *devinfo = &screen->devinfo; + if (devinfo->gen >= 12 && isl_aux_usage_has_ccs(res->aux.usage)) { + void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr); + assert(aux_map_ctx); + const unsigned aux_offset = res->aux.extra_aux.surf.size_B > 0 ? + res->aux.extra_aux.offset : res->aux.offset; + gen_aux_map_add_image(aux_map_ctx, &res->surf, res->bo->gtt_offset, + res->aux.bo->gtt_offset + aux_offset); + res->bo->aux_map_address = res->aux.bo->gtt_offset; + } +} + +static bool +want_ccs_e_for_format(const struct gen_device_info *devinfo, + enum isl_format format) +{ + if (!isl_format_supports_ccs_e(devinfo, format)) + return false; + + const struct isl_format_layout *fmtl = isl_format_get_layout(format); + + /* CCS_E seems to significantly hurt performance with 32-bit floating + * point formats. For example, Paraview's "Wavelet Volume" case uses + * both R32_FLOAT and R32G32B32A32_FLOAT, and enabling CCS_E for those + * formats causes a 62% FPS drop. + * + * However, many benchmarks seem to use 16-bit float with no issues. + */ + if (fmtl->channels.r.bits == 32 && fmtl->channels.r.type == ISL_SFLOAT) + return false; + + return true; +} + /** - * Allocate the initial aux surface for a resource based on aux.usage + * Configure aux for the resource, but don't allocate it. For images which + * might be shared with modifiers, we must allocate the image and aux data in + * a single bo. + * + * Returns false on unexpected error (e.g. allocation failed, or invalid + * configuration result). */ static bool -iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) +iris_resource_configure_aux(struct iris_screen *screen, + struct iris_resource *res, bool imported, + uint64_t *aux_size_B, + uint32_t *alloc_flags) { - struct isl_device *isl_dev = &screen->isl_dev; - enum isl_aux_state initial_state; - UNUSED bool ok = false; - uint8_t memset_value = 0; - uint32_t alloc_flags = 0; const struct gen_device_info *devinfo = &screen->devinfo; - const unsigned clear_color_state_size = devinfo->gen >= 10 ? - screen->isl_dev.ss.clear_color_state_size : - (devinfo->gen >= 9 ? screen->isl_dev.ss.clear_value_size : 0); + /* Try to create the auxiliary surfaces allowed by the modifier or by + * the user if no modifier is specified. + */ + assert(!res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE || + res->mod_info->aux_usage == ISL_AUX_USAGE_CCS_E); + + const bool has_mcs = !res->mod_info && + isl_surf_get_mcs_surf(&screen->isl_dev, &res->surf, &res->aux.surf); + + const bool has_hiz = !res->mod_info && !(INTEL_DEBUG & DEBUG_NO_HIZ) && + isl_surf_get_hiz_surf(&screen->isl_dev, &res->surf, &res->aux.surf); + + const bool has_ccs = + ((!res->mod_info && !(INTEL_DEBUG & DEBUG_NO_RBC)) || + (res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE)) && + isl_surf_get_ccs_surf(&screen->isl_dev, &res->surf, &res->aux.surf, + &res->aux.extra_aux.surf, 0); + + /* Having both HIZ and MCS is impossible. */ + assert(!has_mcs || !has_hiz); + + /* Ensure aux surface creation for MCS_CCS and HIZ_CCS is correct. */ + if (has_ccs && (has_mcs || has_hiz)) { + assert(res->aux.extra_aux.surf.size_B > 0 && + res->aux.extra_aux.surf.usage & ISL_SURF_USAGE_CCS_BIT); + assert(res->aux.surf.size_B > 0 && + res->aux.surf.usage & + (ISL_SURF_USAGE_HIZ_BIT | ISL_SURF_USAGE_MCS_BIT)); + } + + if (res->mod_info && has_ccs) { + /* Only allow a CCS modifier if the aux was created successfully. */ + res->aux.possible_usages |= 1 << res->mod_info->aux_usage; + } else if (has_mcs) { + res->aux.possible_usages |= + 1 << (has_ccs ? ISL_AUX_USAGE_MCS_CCS : ISL_AUX_USAGE_MCS); + } else if (has_hiz) { + res->aux.possible_usages |= + 1 << (has_ccs ? ISL_AUX_USAGE_HIZ_CCS : ISL_AUX_USAGE_HIZ); + } else if (has_ccs) { + if (want_ccs_e_for_format(devinfo, res->surf.format)) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E; + + if (isl_format_supports_ccs_d(devinfo, res->surf.format)) + res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D; + } + + res->aux.usage = util_last_bit(res->aux.possible_usages) - 1; + + res->aux.sampler_usages = res->aux.possible_usages; + + /* We don't always support sampling with hiz. But when we do, it must be + * single sampled. + */ + if (!devinfo->has_sample_with_hiz || res->surf.samples > 1) + res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ); + + /* We don't always support sampling with HIZ_CCS. But when we do, treat it + * as CCS_E.*/ + res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ_CCS); + if (isl_surf_supports_hiz_ccs_wt(devinfo, &res->surf, res->aux.usage)) + res->aux.sampler_usages |= 1 << ISL_AUX_USAGE_CCS_E; + + enum isl_aux_state initial_state; + *aux_size_B = 0; + *alloc_flags = 0; assert(!res->aux.bo); switch (res->aux.usage) { case ISL_AUX_USAGE_NONE: - res->aux.surf.size_B = 0; - break; + /* Having no aux buffer is only okay if there's no modifier with aux. */ + return !res->mod_info || res->mod_info->aux_usage == ISL_AUX_USAGE_NONE; case ISL_AUX_USAGE_HIZ: + case ISL_AUX_USAGE_HIZ_CCS: initial_state = ISL_AUX_STATE_AUX_INVALID; - memset_value = 0; - ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf); break; case ISL_AUX_USAGE_MCS: + case ISL_AUX_USAGE_MCS_CCS: /* The Ivybridge PRM, Vol 2 Part 1 p326 says: * * "When MCS buffer is enabled and bound to MSRT, it is required @@ -361,8 +530,6 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) * 1's, so we simply memset it to 0xff. */ initial_state = ISL_AUX_STATE_CLEAR; - memset_value = 0xFF; - ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf); break; case ISL_AUX_USAGE_CCS_D: case ISL_AUX_USAGE_CCS_E: @@ -379,57 +546,100 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) * For CCS_D, do the same thing. On Gen9+, this avoids having any * undefined bits in the aux buffer. */ - initial_state = ISL_AUX_STATE_PASS_THROUGH; - alloc_flags |= BO_ALLOC_ZEROED; - ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0); + if (imported) + initial_state = + isl_drm_modifier_get_default_aux_state(res->mod_info->modifier); + else + initial_state = ISL_AUX_STATE_PASS_THROUGH; + *alloc_flags |= BO_ALLOC_ZEROED; break; } - /* No work is needed for a zero-sized auxiliary buffer. */ - if (res->aux.surf.size_B == 0) - return true; - - /* Assert that ISL gave us a valid aux surf */ - assert(ok); - /* Create the aux_state for the auxiliary buffer. */ res->aux.state = create_aux_state_map(res, initial_state); if (!res->aux.state) return false; + /* Increase the aux offset if the main and aux surfaces will share a BO. */ + res->aux.offset = + !res->mod_info || res->mod_info->aux_usage == res->aux.usage ? + ALIGN(res->surf.size_B, res->aux.surf.alignment_B) : 0; uint64_t size = res->aux.surf.size_B; + /* Allocate space in the buffer for storing the CCS. */ + if (res->aux.extra_aux.surf.size_B > 0) { + const uint64_t padded_aux_size = + ALIGN(size, res->aux.extra_aux.surf.alignment_B); + res->aux.extra_aux.offset = res->aux.offset + padded_aux_size; + size = padded_aux_size + res->aux.extra_aux.surf.size_B; + } + /* Allocate space in the buffer for storing the clear color. On modern * platforms (gen > 9), we can read it directly from such buffer. * * On gen <= 9, we are going to store the clear color on the buffer * anyways, and copy it back to the surface state during state emission. + * + * Also add some padding to make sure the fast clear color state buffer + * starts at a 4K alignment. We believe that 256B might be enough, but due + * to lack of testing we will leave this as 4K for now. */ - res->aux.clear_color_offset = size; - size += clear_color_state_size; + size = ALIGN(size, 4096); + res->aux.clear_color_offset = res->aux.offset + size; + size += iris_get_aux_clear_color_state_size(screen); + *aux_size_B = size; - /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules - * the drm allocator. Therefore, one can pass the ISL dimensions in terms - * of bytes instead of trying to recalculate based on different format - * block sizes. - */ - res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, - IRIS_MEMZONE_OTHER, I915_TILING_Y, - res->aux.surf.row_pitch_B, alloc_flags); - if (!res->aux.bo) { - return false; + if (isl_aux_usage_has_hiz(res->aux.usage)) { + for (unsigned level = 0; level < res->surf.levels; ++level) { + uint32_t width = u_minify(res->surf.phys_level0_sa.width, level); + uint32_t height = u_minify(res->surf.phys_level0_sa.height, level); + + /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned. + * For LOD == 0, we can grow the dimensions to make it work. + */ + if (level == 0 || ((width & 7) == 0 && (height & 3) == 0)) + res->aux.has_hiz |= 1 << level; + } } + return true; +} + +/** + * Initialize the aux buffer contents. + * + * Returns false on unexpected error (e.g. mapping a BO failed). + */ +static bool +iris_resource_init_aux_buf(struct iris_resource *res, uint32_t alloc_flags, + unsigned clear_color_state_size) +{ if (!(alloc_flags & BO_ALLOC_ZEROED)) { void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW); - if (!map) { - iris_resource_disable_aux(res); + if (!map) return false; + + if (iris_resource_get_aux_state(res, 0, 0) != ISL_AUX_STATE_AUX_INVALID) { + uint8_t memset_value = isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0; + memset((char*)map + res->aux.offset, memset_value, + res->aux.surf.size_B); } - if (memset_value != 0) - memset(map, memset_value, res->aux.surf.size_B); + /* Bspec section titled : MCS/CCS Buffers for Render Target(s) states: + * - If Software wants to enable Color Compression without Fast clear, + * Software needs to initialize MCS with zeros. + * - Lossless compression and CCS initialized to all F (using HW Fast + * Clear or SW direct Clear) + * + * We think, the first bullet point above is referring to CCS aux + * surface. Since we initialize the MCS in the clear state, we also + * initialize the CCS in the clear state (via SW direct clear) to keep + * the two in sync. + */ + memset((char*)map + res->aux.extra_aux.offset, + isl_aux_usage_has_mcs(res->aux.usage) ? 0xFF : 0, + res->aux.extra_aux.surf.size_B); /* Zero the indirect clear color to match ::fast_clear_color. */ memset((char *)map + res->aux.clear_color_offset, 0, @@ -443,62 +653,85 @@ iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res) iris_bo_reference(res->aux.clear_color_bo); } - if (res->aux.usage == ISL_AUX_USAGE_HIZ) { - for (unsigned level = 0; level < res->surf.levels; ++level) { - uint32_t width = u_minify(res->surf.phys_level0_sa.width, level); - uint32_t height = u_minify(res->surf.phys_level0_sa.height, level); - - /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned. - * For LOD == 0, we can grow the dimensions to make it work. - */ - if (level == 0 || ((width & 7) == 0 && (height & 3) == 0)) - res->aux.has_hiz |= 1 << level; - } - } - return true; } +/** + * Allocate the initial aux surface for a resource based on aux.usage + * + * Returns false on unexpected error (e.g. allocation failed, or invalid + * configuration result). + */ static bool -supports_mcs(const struct isl_surf *surf) +iris_resource_alloc_separate_aux(struct iris_screen *screen, + struct iris_resource *res) { - /* MCS compression only applies to multisampled resources. */ - if (surf->samples <= 1) + uint32_t alloc_flags; + uint64_t size; + if (!iris_resource_configure_aux(screen, res, false, &size, &alloc_flags)) return false; - /* See isl_surf_get_mcs_surf for details. */ - if (surf->samples == 16 && surf->logical_level0_px.width > 8192) + if (size == 0) + return true; + + /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules + * the drm allocator. Therefore, one can pass the ISL dimensions in terms + * of bytes instead of trying to recalculate based on different format + * block sizes. + */ + res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer", size, 4096, + IRIS_MEMZONE_OTHER, + isl_tiling_to_i915_tiling(res->aux.surf.tiling), + res->aux.surf.row_pitch_B, alloc_flags); + if (!res->aux.bo) { return false; + } - /* Depth and stencil buffers use the IMS (interleaved) layout. */ - if (isl_surf_usage_is_depth_or_stencil(surf->usage)) + if (!iris_resource_init_aux_buf(res, alloc_flags, + iris_get_aux_clear_color_state_size(screen))) return false; + map_aux_addresses(screen, res); + return true; } -static bool -supports_ccs(const struct gen_device_info *devinfo, - const struct isl_surf *surf) +void +iris_resource_finish_aux_import(struct pipe_screen *pscreen, + struct iris_resource *res) { - /* Gen9+ only supports CCS for Y-tiled buffers. */ - if (surf->tiling != ISL_TILING_Y0) - return false; + struct iris_screen *screen = (struct iris_screen *)pscreen; + assert(iris_resource_unfinished_aux_import(res)); + assert(!res->mod_info->supports_clear_color); - /* CCS only supports singlesampled resources. */ - if (surf->samples > 1) - return false; + struct iris_resource *aux_res = (void *) res->base.next; + assert(aux_res->aux.surf.row_pitch_B && aux_res->aux.offset && + aux_res->aux.bo); - /* The PRM doesn't say this explicitly, but fast-clears don't appear to - * work for 3D textures until Gen9 where the layout of 3D textures changes - * to match 2D array textures. - */ - if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D) - return false; + assert(res->bo == aux_res->aux.bo); + iris_bo_reference(aux_res->aux.bo); + res->aux.bo = aux_res->aux.bo; - /* Note: still need to check the format! */ + res->aux.offset = aux_res->aux.offset; - return true; + assert(res->bo->size >= (res->aux.offset + res->aux.surf.size_B)); + assert(res->aux.clear_color_bo == NULL); + res->aux.clear_color_offset = 0; + + assert(aux_res->aux.surf.row_pitch_B == res->aux.surf.row_pitch_B); + + unsigned clear_color_state_size = + iris_get_aux_clear_color_state_size(screen); + + if (clear_color_state_size > 0) { + res->aux.clear_color_bo = + iris_bo_alloc(screen->bufmgr, "clear color buffer", + clear_color_state_size, IRIS_MEMZONE_OTHER); + res->aux.clear_color_offset = 0; + } + + iris_resource_destroy(&screen->base, res->base.next); + res->base.next = NULL; } static struct pipe_resource * @@ -556,7 +789,7 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, util_format_description(templ->format); const bool has_depth = util_format_has_depth(format_desc); uint64_t modifier = - select_best_modifier(devinfo, modifiers, modifiers_count); + select_best_modifier(devinfo, templ->format, modifiers, modifiers_count); isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK; @@ -567,28 +800,15 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, } else { if (modifiers_count > 0) { fprintf(stderr, "Unsupported modifier, resource creation failed.\n"); - return NULL; - } - - /* No modifiers - we can select our own tiling. */ - - if (has_depth) { - /* Depth must be Y-tiled */ - tiling_flags = ISL_TILING_Y0_BIT; - } else if (templ->format == PIPE_FORMAT_S8_UINT) { - /* Stencil must be W-tiled */ - tiling_flags = ISL_TILING_W_BIT; - } else if (templ->target == PIPE_BUFFER || - templ->target == PIPE_TEXTURE_1D || - templ->target == PIPE_TEXTURE_1D_ARRAY) { - /* Use linear for buffers and 1D textures */ - tiling_flags = ISL_TILING_LINEAR_BIT; + goto fail; } /* Use linear for staging buffers */ if (templ->usage == PIPE_USAGE_STAGING || templ->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR) ) tiling_flags = ISL_TILING_LINEAR_BIT; + else if (templ->bind & PIPE_BIND_SCANOUT) + tiling_flags = ISL_TILING_X_BIT; } isl_surf_usage_flags_t usage = pipe_bind_to_isl_usage(templ->bind); @@ -629,33 +849,6 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, .tiling_flags = tiling_flags); assert(isl_surf_created_successfully); - if (res->mod_info) { - res->aux.possible_usages |= 1 << res->mod_info->aux_usage; - } else if (supports_mcs(&res->surf)) { - res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS; - } else if (has_depth) { - if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ))) - res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ; - } else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) && - supports_ccs(devinfo, &res->surf)) { - if (isl_format_supports_ccs_e(devinfo, res->surf.format)) - res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E; - - if (isl_format_supports_ccs_d(devinfo, res->surf.format)) - res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D; - } - - res->aux.usage = util_last_bit(res->aux.possible_usages) - 1; - - res->aux.sampler_usages = res->aux.possible_usages; - - /* We don't always support sampling with hiz. But when we do, it must be - * single sampled. - */ - if (!devinfo->has_sample_with_hiz || res->surf.samples > 1) { - res->aux.sampler_usages &= ~(1 << ISL_AUX_USAGE_HIZ); - } - const char *name = "miptree"; enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER; @@ -668,7 +861,20 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, IRIS_RESOURCE_FLAG_SURFACE_MEMZONE | IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE))); - res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B, + uint32_t aux_preferred_alloc_flags; + uint64_t aux_size = 0; + if (!iris_resource_configure_aux(screen, res, false, &aux_size, + &aux_preferred_alloc_flags)) { + goto fail; + } + + /* Modifiers require the aux data to be in the same buffer as the main + * surface, but we combine them even when a modifiers is not being used. + */ + const uint64_t bo_size = + MAX2(res->surf.size_B, res->aux.offset + aux_size); + uint32_t alignment = MAX2(4096, res->surf.alignment_B); + res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, bo_size, alignment, memzone, isl_tiling_to_i915_tiling(res->surf.tiling), res->surf.row_pitch_B, flags); @@ -676,8 +882,15 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen, if (!res->bo) goto fail; - if (!iris_resource_alloc_aux(screen, res)) - goto fail; + if (aux_size > 0) { + res->aux.bo = res->bo; + iris_bo_reference(res->aux.bo); + unsigned clear_color_state_size = + iris_get_aux_clear_color_state_size(screen); + if (!iris_resource_init_aux_buf(res, flags, clear_color_state_size)) + goto fail; + map_aux_addresses(screen, res); + } return &res->base; @@ -734,6 +947,8 @@ iris_resource_from_user_memory(struct pipe_screen *pscreen, return NULL; } + util_range_add(&res->base, &res->valid_buffer_range, 0, templ->width0); + return &res->base; } @@ -747,18 +962,21 @@ iris_resource_from_handle(struct pipe_screen *pscreen, struct gen_device_info *devinfo = &screen->devinfo; struct iris_bufmgr *bufmgr = screen->bufmgr; struct iris_resource *res = iris_alloc_resource(pscreen, templ); + const struct isl_drm_modifier_info *mod_inf = + isl_drm_modifier_get_info(whandle->modifier); + uint32_t tiling; + if (!res) return NULL; - if (whandle->offset != 0) { - dbg_printf("Attempt to import unsupported winsys offset %u\n", - whandle->offset); - goto fail; - } - switch (whandle->type) { case WINSYS_HANDLE_TYPE_FD: - res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle); + if (mod_inf) + tiling = isl_tiling_to_i915_tiling(mod_inf->tiling); + else + tiling = I915_TILING_LAST + 1; + res->bo = iris_bo_import_dmabuf(bufmgr, whandle->handle, + tiling, whandle->stride); break; case WINSYS_HANDLE_TYPE_SHARED: res->bo = iris_bo_gem_create_from_name(bufmgr, "winsys image", @@ -770,12 +988,16 @@ iris_resource_from_handle(struct pipe_screen *pscreen, if (!res->bo) return NULL; - uint64_t modifier = whandle->modifier; - if (modifier == DRM_FORMAT_MOD_INVALID) { - modifier = tiling_to_modifier(res->bo->tiling_mode); + res->offset = whandle->offset; + + if (mod_inf == NULL) { + mod_inf = + isl_drm_modifier_get_info(tiling_to_modifier(res->bo->tiling_mode)); } - res->mod_info = isl_drm_modifier_get_info(modifier); - assert(res->mod_info); + assert(mod_inf); + + res->external_format = whandle->format; + res->mod_info = mod_inf; isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind); @@ -786,26 +1008,55 @@ iris_resource_from_handle(struct pipe_screen *pscreen, if (templ->target == PIPE_BUFFER) { res->surf.tiling = ISL_TILING_LINEAR; } else { - isl_surf_init(&screen->isl_dev, &res->surf, - .dim = target_to_isl_surf_dim(templ->target), - .format = fmt.fmt, - .width = templ->width0, - .height = templ->height0, - .depth = templ->depth0, - .levels = templ->last_level + 1, - .array_len = templ->array_size, - .samples = MAX2(templ->nr_samples, 1), - .min_alignment_B = 0, - .row_pitch_B = whandle->stride, - .usage = isl_usage, - .tiling_flags = 1 << res->mod_info->tiling); - - assert(res->bo->tiling_mode == - isl_tiling_to_i915_tiling(res->surf.tiling)); - - // XXX: create_ccs_buf_for_image? - if (!iris_resource_alloc_aux(screen, res)) - goto fail; + /* Create a surface for each plane specified by the external format. */ + if (whandle->plane < util_format_get_num_planes(whandle->format)) { + UNUSED const bool isl_surf_created_successfully = + isl_surf_init(&screen->isl_dev, &res->surf, + .dim = target_to_isl_surf_dim(templ->target), + .format = fmt.fmt, + .width = templ->width0, + .height = templ->height0, + .depth = templ->depth0, + .levels = templ->last_level + 1, + .array_len = templ->array_size, + .samples = MAX2(templ->nr_samples, 1), + .min_alignment_B = 0, + .row_pitch_B = whandle->stride, + .usage = isl_usage, + .tiling_flags = 1 << res->mod_info->tiling); + assert(isl_surf_created_successfully); + assert(res->bo->tiling_mode == + isl_tiling_to_i915_tiling(res->surf.tiling)); + + // XXX: create_ccs_buf_for_image? + if (whandle->modifier == DRM_FORMAT_MOD_INVALID) { + if (!iris_resource_alloc_separate_aux(screen, res)) + goto fail; + } else { + if (res->mod_info->aux_usage != ISL_AUX_USAGE_NONE) { + uint32_t alloc_flags; + uint64_t size; + bool ok = iris_resource_configure_aux(screen, res, true, &size, + &alloc_flags); + assert(ok); + /* The gallium dri layer will create a separate plane resource + * for the aux image. iris_resource_finish_aux_import will + * merge the separate aux parameters back into a single + * iris_resource. + */ + } + } + } else { + /* Save modifier import information to reconstruct later. After + * import, this will be available under a second image accessible + * from the main image with res->base.next. See + * iris_resource_finish_aux_import. + */ + res->aux.surf.row_pitch_B = whandle->stride; + res->aux.offset = whandle->offset; + res->aux.bo = res->bo; + res->bo = NULL; + } } return &res->base; @@ -815,7 +1066,104 @@ fail: return NULL; } -static boolean +static void +iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource) +{ + struct iris_context *ice = (struct iris_context *)ctx; + struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER]; + struct iris_resource *res = (void *) resource; + const struct isl_drm_modifier_info *mod = res->mod_info; + + iris_resource_prepare_access(ice, render_batch, res, + 0, INTEL_REMAINING_LEVELS, + 0, INTEL_REMAINING_LAYERS, + mod ? mod->aux_usage : ISL_AUX_USAGE_NONE, + mod ? mod->supports_clear_color : false); +} + +static void +iris_resource_disable_aux_on_first_query(struct pipe_resource *resource, + unsigned usage) +{ + struct iris_resource *res = (struct iris_resource *)resource; + bool mod_with_aux = + res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; + + /* Disable aux usage if explicit flush not set and this is the first time + * we are dealing with this resource and the resource was not created with + * a modifier with aux. + */ + if (!mod_with_aux && + (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) && res->aux.usage != 0) && + p_atomic_read(&resource->reference.count) == 1) { + iris_resource_disable_aux(res); + } +} + +static bool +iris_resource_get_param(struct pipe_screen *screen, + struct pipe_context *context, + struct pipe_resource *resource, + unsigned plane, + unsigned layer, + enum pipe_resource_param param, + unsigned handle_usage, + uint64_t *value) +{ + struct iris_resource *res = (struct iris_resource *)resource; + bool mod_with_aux = + res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; + bool wants_aux = mod_with_aux && plane > 0; + bool result; + unsigned handle; + + if (iris_resource_unfinished_aux_import(res)) + iris_resource_finish_aux_import(screen, res); + + struct iris_bo *bo = wants_aux ? res->aux.bo : res->bo; + + iris_resource_disable_aux_on_first_query(resource, handle_usage); + + switch (param) { + case PIPE_RESOURCE_PARAM_NPLANES: + if (mod_with_aux) { + *value = 2; + } else { + unsigned count = 0; + for (struct pipe_resource *cur = resource; cur; cur = cur->next) + count++; + *value = count; + } + return true; + case PIPE_RESOURCE_PARAM_STRIDE: + *value = wants_aux ? res->aux.surf.row_pitch_B : res->surf.row_pitch_B; + return true; + case PIPE_RESOURCE_PARAM_OFFSET: + *value = wants_aux ? res->aux.offset : 0; + return true; + case PIPE_RESOURCE_PARAM_MODIFIER: + *value = res->mod_info ? res->mod_info->modifier : + tiling_to_modifier(res->bo->tiling_mode); + return true; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED: + result = iris_bo_flink(bo, &handle) == 0; + if (result) + *value = handle; + return result; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS: + *value = iris_bo_export_gem_handle(bo); + return true; + case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD: + result = iris_bo_export_dmabuf(bo, (int *) &handle) == 0; + if (result) + *value = handle; + return result; + default: + return false; + } +} + +static bool iris_resource_get_handle(struct pipe_screen *pscreen, struct pipe_context *ctx, struct pipe_resource *resource, @@ -823,9 +1171,24 @@ iris_resource_get_handle(struct pipe_screen *pscreen, unsigned usage) { struct iris_resource *res = (struct iris_resource *)resource; + bool mod_with_aux = + res->mod_info && res->mod_info->aux_usage != ISL_AUX_USAGE_NONE; - /* If this is a buffer, stride should be 0 - no need to special case */ - whandle->stride = res->surf.row_pitch_B; + iris_resource_disable_aux_on_first_query(resource, usage); + + struct iris_bo *bo; + if (mod_with_aux && whandle->plane > 0) { + assert(res->aux.bo); + bo = res->aux.bo; + whandle->stride = res->aux.surf.row_pitch_B; + whandle->offset = res->aux.offset; + } else { + /* If this is a buffer, stride should be 0 - no need to special case */ + whandle->stride = res->surf.row_pitch_B; + bo = res->bo; + } + + whandle->format = res->external_format; whandle->modifier = res->mod_info ? res->mod_info->modifier : tiling_to_modifier(res->bo->tiling_mode); @@ -843,36 +1206,110 @@ iris_resource_get_handle(struct pipe_screen *pscreen, switch (whandle->type) { case WINSYS_HANDLE_TYPE_SHARED: - return iris_bo_flink(res->bo, &whandle->handle) == 0; + return iris_bo_flink(bo, &whandle->handle) == 0; case WINSYS_HANDLE_TYPE_KMS: - whandle->handle = iris_bo_export_gem_handle(res->bo); + whandle->handle = iris_bo_export_gem_handle(bo); return true; case WINSYS_HANDLE_TYPE_FD: - return iris_bo_export_dmabuf(res->bo, (int *) &whandle->handle) == 0; + return iris_bo_export_dmabuf(bo, (int *) &whandle->handle) == 0; } return false; } +static bool +resource_is_busy(struct iris_context *ice, + struct iris_resource *res) +{ + bool busy = iris_bo_busy(res->bo); + + for (int i = 0; i < IRIS_BATCH_COUNT; i++) + busy |= iris_batch_references(&ice->batches[i], res->bo); + + return busy; +} + static void -iris_unmap_copy_region(struct iris_transfer *map) +iris_invalidate_resource(struct pipe_context *ctx, + struct pipe_resource *resource) { - struct pipe_transfer *xfer = &map->base; - struct pipe_box *dst_box = &xfer->box; - struct pipe_box src_box = (struct pipe_box) { - .x = xfer->resource->target == PIPE_BUFFER ? - xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT : 0, - .width = dst_box->width, - .height = dst_box->height, - .depth = dst_box->depth, - }; + struct iris_screen *screen = (void *) ctx->screen; + struct iris_context *ice = (void *) ctx; + struct iris_resource *res = (void *) resource; - if (xfer->usage & PIPE_TRANSFER_WRITE) { - iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level, - dst_box->x, dst_box->y, dst_box->z, map->staging, 0, - &src_box); + if (resource->target != PIPE_BUFFER) + return; + + if (!resource_is_busy(ice, res)) { + /* The resource is idle, so just mark that it contains no data and + * keep using the same underlying buffer object. + */ + util_range_set_empty(&res->valid_buffer_range); + return; } + /* Otherwise, try and replace the backing storage with a new BO. */ + + /* We can't reallocate memory we didn't allocate in the first place. */ + if (res->bo->userptr) + return; + + // XXX: We should support this. + if (res->bind_history & PIPE_BIND_STREAM_OUTPUT) + return; + + struct iris_bo *old_bo = res->bo; + struct iris_bo *new_bo = + iris_bo_alloc(screen->bufmgr, res->bo->name, resource->width0, + iris_memzone_for_address(old_bo->gtt_offset)); + if (!new_bo) + return; + + /* Swap out the backing storage */ + res->bo = new_bo; + + /* Rebind the buffer, replacing any state referring to the old BO's + * address, and marking state dirty so it's reemitted. + */ + ice->vtbl.rebind_buffer(ice, res); + + util_range_set_empty(&res->valid_buffer_range); + + iris_bo_unreference(old_bo); +} + +static void +iris_flush_staging_region(struct pipe_transfer *xfer, + const struct pipe_box *flush_box) +{ + if (!(xfer->usage & PIPE_TRANSFER_WRITE)) + return; + + struct iris_transfer *map = (void *) xfer; + + struct pipe_box src_box = *flush_box; + + /* Account for extra alignment padding in staging buffer */ + if (xfer->resource->target == PIPE_BUFFER) + src_box.x += xfer->box.x % IRIS_MAP_BUFFER_ALIGNMENT; + + struct pipe_box dst_box = (struct pipe_box) { + .x = xfer->box.x + flush_box->x, + .y = xfer->box.y + flush_box->y, + .z = xfer->box.z + flush_box->z, + .width = flush_box->width, + .height = flush_box->height, + .depth = flush_box->depth, + }; + + iris_copy_region(map->blorp, map->batch, xfer->resource, xfer->level, + dst_box.x, dst_box.y, dst_box.z, map->staging, 0, + &src_box); +} + +static void +iris_unmap_copy_region(struct iris_transfer *map) +{ iris_resource_destroy(map->staging->screen, map->staging); map->ptr = NULL; @@ -897,6 +1334,7 @@ iris_map_copy_region(struct iris_transfer *map) .nr_samples = xfer->resource->nr_samples, .nr_storage_samples = xfer->resource->nr_storage_samples, .array_size = box->depth, + .format = res->internal_format, }; if (xfer->resource->target == PIPE_BUFFER) @@ -906,22 +1344,6 @@ iris_map_copy_region(struct iris_transfer *map) else templ.target = PIPE_TEXTURE_2D; - /* Depth, stencil, and ASTC can't be linear surfaces, so we can't use - * xfer->resource->format directly. Pick a bpb compatible format so - * resource creation will succeed; blorp_copy will override it anyway. - */ - switch (util_format_get_blocksizebits(res->internal_format)) { - case 8: templ.format = PIPE_FORMAT_R8_UINT; break; - case 16: templ.format = PIPE_FORMAT_R8G8_UINT; break; - case 24: templ.format = PIPE_FORMAT_R8G8B8_UINT; break; - case 32: templ.format = PIPE_FORMAT_R8G8B8A8_UINT; break; - case 48: templ.format = PIPE_FORMAT_R16G16B16_UINT; break; - case 64: templ.format = PIPE_FORMAT_R16G16B16A16_UINT; break; - case 96: templ.format = PIPE_FORMAT_R32G32B32_UINT; break; - case 128: templ.format = PIPE_FORMAT_R32G32B32A32_UINT; break; - default: unreachable("Invalid bpb"); - } - map->staging = iris_resource_create(pscreen, &templ); assert(map->staging); @@ -936,6 +1358,7 @@ iris_map_copy_region(struct iris_transfer *map) xfer->resource, xfer->level, box); /* Ensure writes to the staging BO land before we map it below. */ iris_emit_pipe_control_flush(map->batch, + "transfer read: flush before mapping", PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_CS_STALL); } @@ -945,13 +1368,14 @@ iris_map_copy_region(struct iris_transfer *map) if (iris_batch_references(map->batch, staging_bo)) iris_batch_flush(map->batch); - map->ptr = iris_bo_map(map->dbg, staging_bo, xfer->usage) + extra; + map->ptr = + iris_bo_map(map->dbg, staging_bo, xfer->usage & MAP_FLAGS) + extra; map->unmap = iris_unmap_copy_region; } static void -get_image_offset_el(struct isl_surf *surf, unsigned level, unsigned z, +get_image_offset_el(const struct isl_surf *surf, unsigned level, unsigned z, unsigned *out_x0_el, unsigned *out_y0_el) { if (surf->dim == ISL_SURF_DIM_3D) { @@ -961,6 +1385,109 @@ get_image_offset_el(struct isl_surf *surf, unsigned level, unsigned z, } } +/** + * This function computes the tile_w (in bytes) and tile_h (in rows) of + * different tiling patterns. + */ +static void +iris_resource_get_tile_dims(enum isl_tiling tiling, uint32_t cpp, + uint32_t *tile_w, uint32_t *tile_h) +{ + switch (tiling) { + case ISL_TILING_X: + *tile_w = 512; + *tile_h = 8; + break; + case ISL_TILING_Y0: + *tile_w = 128; + *tile_h = 32; + break; + case ISL_TILING_LINEAR: + *tile_w = cpp; + *tile_h = 1; + break; + default: + unreachable("not reached"); + } + +} + +/** + * This function computes masks that may be used to select the bits of the X + * and Y coordinates that indicate the offset within a tile. If the BO is + * untiled, the masks are set to 0. + */ +static void +iris_resource_get_tile_masks(enum isl_tiling tiling, uint32_t cpp, + uint32_t *mask_x, uint32_t *mask_y) +{ + uint32_t tile_w_bytes, tile_h; + + iris_resource_get_tile_dims(tiling, cpp, &tile_w_bytes, &tile_h); + + *mask_x = tile_w_bytes / cpp - 1; + *mask_y = tile_h - 1; +} + +/** + * Compute the offset (in bytes) from the start of the BO to the given x + * and y coordinate. For tiled BOs, caller must ensure that x and y are + * multiples of the tile size. + */ +static uint32_t +iris_resource_get_aligned_offset(const struct iris_resource *res, + uint32_t x, uint32_t y) +{ + const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format); + unsigned cpp = fmtl->bpb / 8; + uint32_t pitch = res->surf.row_pitch_B; + + switch (res->surf.tiling) { + default: + unreachable("not reached"); + case ISL_TILING_LINEAR: + return y * pitch + x * cpp; + case ISL_TILING_X: + assert((x % (512 / cpp)) == 0); + assert((y % 8) == 0); + return y * pitch + x / (512 / cpp) * 4096; + case ISL_TILING_Y0: + assert((x % (128 / cpp)) == 0); + assert((y % 32) == 0); + return y * pitch + x / (128 / cpp) * 4096; + } +} + +/** + * Rendering with tiled buffers requires that the base address of the buffer + * be aligned to a page boundary. For renderbuffers, and sometimes with + * textures, we may want the surface to point at a texture image level that + * isn't at a page boundary. + * + * This function returns an appropriately-aligned base offset + * according to the tiling restrictions, plus any required x/y offset + * from there. + */ +uint32_t +iris_resource_get_tile_offsets(const struct iris_resource *res, + uint32_t level, uint32_t z, + uint32_t *tile_x, uint32_t *tile_y) +{ + uint32_t x, y; + uint32_t mask_x, mask_y; + + const struct isl_format_layout *fmtl = isl_format_get_layout(res->surf.format); + const unsigned cpp = fmtl->bpb / 8; + + iris_resource_get_tile_masks(res->surf.tiling, cpp, &mask_x, &mask_y); + get_image_offset_el(&res->surf, level, z, &x, &y); + + *tile_x = x & mask_x; + *tile_y = y & mask_y; + + return iris_resource_get_aligned_offset(res, x & ~mask_x, y & ~mask_y); +} + /** * Get pointer offset into stencil buffer. * @@ -978,7 +1505,7 @@ get_image_offset_el(struct isl_surf *surf, unsigned level, unsigned z, * mesa: Fix return type of _mesa_get_format_bytes() (#37351) */ static intptr_t -s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled) +s8_offset(uint32_t stride, uint32_t x, uint32_t y) { uint32_t tile_size = 4096; uint32_t tile_width = 64; @@ -1003,17 +1530,6 @@ s8_offset(uint32_t stride, uint32_t x, uint32_t y, bool swizzled) + 2 * (byte_y % 2) + 1 * (byte_x % 2); - if (swizzled) { - /* adjust for bit6 swizzling */ - if (((byte_x / 8) % 2) == 1) { - if (((byte_y / 8) % 2) == 0) { - u += 64; - } else { - u -= 64; - } - } - } - return u; } @@ -1024,12 +1540,11 @@ iris_unmap_s8(struct iris_transfer *map) const struct pipe_box *box = &xfer->box; struct iris_resource *res = (struct iris_resource *) xfer->resource; struct isl_surf *surf = &res->surf; - const bool has_swizzling = false; if (xfer->usage & PIPE_TRANSFER_WRITE) { uint8_t *untiled_s8_map = map->ptr; uint8_t *tiled_s8_map = - iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW); + iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS); for (int s = 0; s < box->depth; s++) { unsigned x0_el, y0_el; @@ -1039,8 +1554,7 @@ iris_unmap_s8(struct iris_transfer *map) for (uint32_t x = 0; x < box->width; x++) { ptrdiff_t offset = s8_offset(surf->row_pitch_B, x0_el + box->x + x, - y0_el + box->y + y, - has_swizzling); + y0_el + box->y + y); tiled_s8_map[offset] = untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x]; } @@ -1069,8 +1583,6 @@ iris_map_s8(struct iris_transfer *map) map->buffer = map->ptr = malloc(xfer->layer_stride * box->depth); assert(map->buffer); - const bool has_swizzling = false; - /* One of either READ_BIT or WRITE_BIT or both is set. READ_BIT implies no * INVALIDATE_RANGE_BIT. WRITE_BIT needs the original values read in unless * invalidate is set, since we'll be writing the whole rectangle from our @@ -1079,7 +1591,7 @@ iris_map_s8(struct iris_transfer *map) if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) { uint8_t *untiled_s8_map = map->ptr; uint8_t *tiled_s8_map = - iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW); + iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS); for (int s = 0; s < box->depth; s++) { unsigned x0_el, y0_el; @@ -1089,8 +1601,7 @@ iris_map_s8(struct iris_transfer *map) for (uint32_t x = 0; x < box->width; x++) { ptrdiff_t offset = s8_offset(surf->row_pitch_B, x0_el + box->x + x, - y0_el + box->y + y, - has_swizzling); + y0_el + box->y + y); untiled_s8_map[s * xfer->layer_stride + y * xfer->stride + x] = tiled_s8_map[offset]; } @@ -1105,7 +1616,7 @@ iris_map_s8(struct iris_transfer *map) * xs are in units of bytes and ys are in units of strides. */ static inline void -tile_extents(struct isl_surf *surf, +tile_extents(const struct isl_surf *surf, const struct pipe_box *box, unsigned level, int z, unsigned *x1_B, unsigned *x2_B, @@ -1137,7 +1648,8 @@ iris_unmap_tiled_memcpy(struct iris_transfer *map) const bool has_swizzling = false; if (xfer->usage & PIPE_TRANSFER_WRITE) { - char *dst = iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW); + char *dst = + iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS); for (int s = 0; s < box->depth; s++) { unsigned x1, x2, y1, y2; @@ -1179,9 +1691,9 @@ iris_map_tiled_memcpy(struct iris_transfer *map) const bool has_swizzling = false; - // XXX: PIPE_TRANSFER_READ? if (!(xfer->usage & PIPE_TRANSFER_DISCARD_RANGE)) { - char *src = iris_bo_map(map->dbg, res->bo, xfer->usage | MAP_RAW); + char *src = + iris_bo_map(map->dbg, res->bo, (xfer->usage | MAP_RAW) & MAP_FLAGS); for (int s = 0; s < box->depth; s++) { unsigned x1, x2, y1, y2; @@ -1206,7 +1718,7 @@ iris_map_direct(struct iris_transfer *map) struct pipe_box *box = &xfer->box; struct iris_resource *res = (struct iris_resource *) xfer->resource; - void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage); + void *ptr = iris_bo_map(map->dbg, res->bo, xfer->usage & MAP_FLAGS); if (res->base.target == PIPE_BUFFER) { xfer->stride = 0; @@ -1229,6 +1741,21 @@ iris_map_direct(struct iris_transfer *map) } } +static bool +can_promote_to_async(const struct iris_resource *res, + const struct pipe_box *box, + enum pipe_transfer_usage usage) +{ + /* If we're writing to a section of the buffer that hasn't even been + * initialized with useful data, then we can safely promote this write + * to be unsynchronized. This helps the common pattern of appending data. + */ + return res->base.target == PIPE_BUFFER && (usage & PIPE_TRANSFER_WRITE) && + !(usage & TC_TRANSFER_MAP_NO_INFER_UNSYNCHRONIZED) && + !util_ranges_intersect(&res->valid_buffer_range, box->x, + box->x + box->width); +} + static void * iris_transfer_map(struct pipe_context *ctx, struct pipe_resource *resource, @@ -1241,25 +1768,39 @@ iris_transfer_map(struct pipe_context *ctx, struct iris_resource *res = (struct iris_resource *)resource; struct isl_surf *surf = &res->surf; - /* If we can discard the whole resource, we can also discard the - * subrange being accessed. - */ - if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) - usage |= PIPE_TRANSFER_DISCARD_RANGE; + if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) { + /* Replace the backing storage with a fresh buffer for non-async maps */ + if (!(usage & (PIPE_TRANSFER_UNSYNCHRONIZED | + TC_TRANSFER_MAP_NO_INVALIDATE))) + iris_invalidate_resource(ctx, resource); - bool map_would_stall = false; + /* If we can discard the whole resource, we can discard the range. */ + usage |= PIPE_TRANSFER_DISCARD_RANGE; + } + + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED) && + can_promote_to_async(res, box, usage)) { + usage |= PIPE_TRANSFER_UNSYNCHRONIZED; + } + + bool need_resolve = false; + bool need_color_resolve = false; if (resource->target != PIPE_BUFFER) { - iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res, - level, box->z, box->depth, - usage & PIPE_TRANSFER_WRITE); + bool need_hiz_resolve = iris_resource_level_has_hiz(res, level); + + need_color_resolve = + (res->aux.usage == ISL_AUX_USAGE_CCS_D || + res->aux.usage == ISL_AUX_USAGE_CCS_E) && + iris_has_color_unresolved(res, level, 1, box->z, box->depth); + + need_resolve = need_color_resolve || need_hiz_resolve; } - if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { - map_would_stall = iris_bo_busy(res->bo); + bool map_would_stall = false; - for (int i = 0; i < IRIS_BATCH_COUNT; i++) - map_would_stall |= iris_batch_references(&ice->batches[i], res->bo); + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { + map_would_stall = need_resolve || resource_is_busy(ice, res); if (map_would_stall && (usage & PIPE_TRANSFER_DONTBLOCK) && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) @@ -1285,12 +1826,12 @@ iris_transfer_map(struct pipe_context *ctx, xfer->box = *box; *ptransfer = xfer; - xfer->usage &= (PIPE_TRANSFER_READ | - PIPE_TRANSFER_WRITE | - PIPE_TRANSFER_UNSYNCHRONIZED | - PIPE_TRANSFER_PERSISTENT | - PIPE_TRANSFER_COHERENT | - PIPE_TRANSFER_DISCARD_RANGE); + map->dest_had_defined_contents = + util_ranges_intersect(&res->valid_buffer_range, box->x, + box->x + box->width); + + if (usage & PIPE_TRANSFER_WRITE) + util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width); /* Avoid using GPU copies for persistent/coherent buffers, as the idea * there is to access them simultaneously on the CPU & GPU. This also @@ -1311,21 +1852,29 @@ iris_transfer_map(struct pipe_context *ctx, * temporary and map that, to avoid the resolve. (It might be better to * a tiled temporary and use the tiled_memcpy paths...) */ - if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && - res->aux.usage != ISL_AUX_USAGE_CCS_E && - res->aux.usage != ISL_AUX_USAGE_CCS_D) { + if (!(usage & PIPE_TRANSFER_DISCARD_RANGE) && !need_color_resolve) + no_gpu = true; + + const struct isl_format_layout *fmtl = isl_format_get_layout(surf->format); + if (fmtl->txc == ISL_TXC_ASTC) no_gpu = true; - } - if (map_would_stall && !no_gpu) { - /* If we need a synchronous mapping and the resource is busy, - * we copy to/from a linear temporary buffer using the GPU. + if ((map_would_stall || res->aux.usage == ISL_AUX_USAGE_CCS_E) && !no_gpu) { + /* If we need a synchronous mapping and the resource is busy, or needs + * resolving, we copy to/from a linear temporary buffer using the GPU. */ map->batch = &ice->batches[IRIS_BATCH_RENDER]; map->blorp = &ice->blorp; iris_map_copy_region(map); } else { - /* Otherwise we're free to map on the CPU. Flush if needed. */ + /* Otherwise we're free to map on the CPU. */ + + if (need_resolve) { + iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res, + level, box->z, box->depth, + usage & PIPE_TRANSFER_WRITE); + } + if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) { for (int i = 0; i < IRIS_BATCH_COUNT; i++) { if (iris_batch_references(&ice->batches[i], res->bo)) @@ -1353,14 +1902,39 @@ iris_transfer_flush_region(struct pipe_context *ctx, { struct iris_context *ice = (struct iris_context *)ctx; struct iris_resource *res = (struct iris_resource *) xfer->resource; + struct iris_transfer *map = (void *) xfer; + + if (map->staging) + iris_flush_staging_region(xfer, box); + + uint32_t history_flush = 0; + + if (res->base.target == PIPE_BUFFER) { + if (map->staging) + history_flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + + if (map->dest_had_defined_contents) + history_flush |= iris_flush_bits_for_history(res); - for (int i = 0; i < IRIS_BATCH_COUNT; i++) { - if (ice->batches[i].contains_draw || - ice->batches[i].cache.render->entries) { - iris_batch_maybe_flush(&ice->batches[i], 24); - iris_flush_and_dirty_for_history(ice, &ice->batches[i], res); + util_range_add(&res->base, &res->valid_buffer_range, box->x, box->x + box->width); + } + + if (history_flush & ~PIPE_CONTROL_CS_STALL) { + for (int i = 0; i < IRIS_BATCH_COUNT; i++) { + struct iris_batch *batch = &ice->batches[i]; + if (batch->contains_draw || batch->cache.render->entries) { + iris_batch_maybe_flush(batch, 24); + iris_emit_pipe_control_flush(batch, + "cache history: transfer flush", + history_flush); + } } } + + /* Make sure we flag constants dirty even if there's no need to emit + * any PIPE_CONTROLs to a batch. + */ + iris_dirty_for_history(ice, res); } static void @@ -1368,66 +1942,53 @@ iris_transfer_unmap(struct pipe_context *ctx, struct pipe_transfer *xfer) { struct iris_context *ice = (struct iris_context *)ctx; struct iris_transfer *map = (void *) xfer; - struct iris_resource *res = (struct iris_resource *) xfer->resource; + + if (!(xfer->usage & (PIPE_TRANSFER_FLUSH_EXPLICIT | + PIPE_TRANSFER_COHERENT))) { + struct pipe_box flush_box = { + .x = 0, .y = 0, .z = 0, + .width = xfer->box.width, + .height = xfer->box.height, + .depth = xfer->box.depth, + }; + iris_transfer_flush_region(ctx, xfer, &flush_box); + } if (map->unmap) map->unmap(map); - for (int i = 0; i < IRIS_BATCH_COUNT; i++) { - if (ice->batches[i].contains_draw || - ice->batches[i].cache.render->entries) { - iris_batch_maybe_flush(&ice->batches[i], 24); - iris_flush_and_dirty_for_history(ice, &ice->batches[i], res); - } - } - pipe_resource_reference(&xfer->resource, NULL); slab_free(&ice->transfer_pool, map); } -static void -iris_flush_resource(struct pipe_context *ctx, struct pipe_resource *resource) -{ - struct iris_context *ice = (struct iris_context *)ctx; - struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER]; - struct iris_resource *res = (void *) resource; - const struct isl_drm_modifier_info *mod = res->mod_info; - - iris_resource_prepare_access(ice, render_batch, res, - 0, INTEL_REMAINING_LEVELS, - 0, INTEL_REMAINING_LAYERS, - mod ? mod->aux_usage : ISL_AUX_USAGE_NONE, - mod ? mod->supports_clear_color : false); -} - +/** + * Mark state dirty that needs to be re-emitted when a resource is written. + */ void -iris_flush_and_dirty_for_history(struct iris_context *ice, - struct iris_batch *batch, - struct iris_resource *res) +iris_dirty_for_history(struct iris_context *ice, + struct iris_resource *res) { - if (res->base.target != PIPE_BUFFER) - return; + uint64_t dirty = 0ull; - unsigned flush = PIPE_CONTROL_CS_STALL; + if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) { + dirty |= ((uint64_t)res->bind_stages) << IRIS_SHIFT_FOR_DIRTY_CONSTANTS; + } - /* We've likely used the rendering engine (i.e. BLORP) to write to this - * surface. Flush the render cache so the data actually lands. - */ - if (batch->name != IRIS_BATCH_COMPUTE) - flush |= PIPE_CONTROL_RENDER_TARGET_FLUSH; + ice->state.dirty |= dirty; +} - uint64_t dirty = 0ull; +/** + * Produce a set of PIPE_CONTROL bits which ensure data written to a + * resource becomes visible, and any stale read cache data is invalidated. + */ +uint32_t +iris_flush_bits_for_history(struct iris_resource *res) +{ + uint32_t flush = PIPE_CONTROL_CS_STALL; if (res->bind_history & PIPE_BIND_CONSTANT_BUFFER) { flush |= PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; - dirty |= IRIS_DIRTY_CONSTANTS_VS | - IRIS_DIRTY_CONSTANTS_TCS | - IRIS_DIRTY_CONSTANTS_TES | - IRIS_DIRTY_CONSTANTS_GS | - IRIS_DIRTY_CONSTANTS_FS | - IRIS_DIRTY_CONSTANTS_CS | - IRIS_ALL_DIRTY_BINDINGS; } if (res->bind_history & PIPE_BIND_SAMPLER_VIEW) @@ -1439,9 +2000,24 @@ iris_flush_and_dirty_for_history(struct iris_context *ice, if (res->bind_history & (PIPE_BIND_SHADER_BUFFER | PIPE_BIND_SHADER_IMAGE)) flush |= PIPE_CONTROL_DATA_CACHE_FLUSH; - iris_emit_pipe_control_flush(batch, flush); + return flush; +} - ice->state.dirty |= dirty; +void +iris_flush_and_dirty_for_history(struct iris_context *ice, + struct iris_batch *batch, + struct iris_resource *res, + uint32_t extra_flags, + const char *reason) +{ + if (res->base.target != PIPE_BUFFER) + return; + + uint32_t flush = iris_flush_bits_for_history(res) | extra_flags; + + iris_emit_pipe_control_flush(batch, reason, flush); + + iris_dirty_for_history(ice, res); } bool @@ -1499,6 +2075,7 @@ iris_init_screen_resource_functions(struct pipe_screen *pscreen) pscreen->resource_from_user_memory = iris_resource_from_user_memory; pscreen->resource_from_handle = iris_resource_from_handle; pscreen->resource_get_handle = iris_resource_get_handle; + pscreen->resource_get_param = iris_resource_get_param; pscreen->resource_destroy = u_transfer_helper_resource_destroy; pscreen->transfer_helper = u_transfer_helper_create(&transfer_vtbl, true, true, false, true); @@ -1508,6 +2085,7 @@ void iris_init_resource_functions(struct pipe_context *ctx) { ctx->flush_resource = iris_flush_resource; + ctx->invalidate_resource = iris_invalidate_resource; ctx->transfer_map = u_transfer_helper_transfer_map; ctx->transfer_flush_region = u_transfer_helper_transfer_flush_region; ctx->transfer_unmap = u_transfer_helper_transfer_unmap;