X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_screen.c;h=295974910b41a94eed4fa211e761d2612eb7cc2d;hb=59aa7c924d88cf8c7a8f64bcb25f358eab30d713;hp=f2c45e5ec6eb219a6222cac150497a45fc5a19a9;hpb=b9ccb00e2c8ab4ba2f1b392f126e9e2f8457ebcd;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index f2c45e5ec6e..295974910b4 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -37,10 +37,13 @@ #include "pipe/p_state.h" #include "pipe/p_context.h" #include "pipe/p_screen.h" +#include "util/debug.h" #include "util/u_inlines.h" #include "util/u_format.h" +#include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" #include "util/ralloc.h" +#include "util/xmlconfig.h" #include "drm-uapi/i915_drm.h" #include "iris_context.h" #include "iris_defines.h" @@ -61,7 +64,7 @@ iris_flush_frontbuffer(struct pipe_screen *_screen, static const char * iris_get_vendor(struct pipe_screen *pscreen) { - return "Mesa Project"; + return "Intel"; } static const char * @@ -74,6 +77,7 @@ static const char * iris_get_name(struct pipe_screen *pscreen) { struct iris_screen *screen = (struct iris_screen *)pscreen; + static char buf[128]; const char *chipset; switch (screen->pci_id) { @@ -84,7 +88,9 @@ iris_get_name(struct pipe_screen *pscreen) chipset = "Unknown Intel Chipset"; break; } - return &chipset[9]; + + snprintf(buf, sizeof(buf), "Mesa %s", chipset); + return buf; } static int @@ -110,6 +116,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_DEPTH_CLIP_DISABLE: + case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: @@ -125,7 +132,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: - case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: @@ -144,7 +151,6 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DOUBLES: case PIPE_CAP_INT64: case PIPE_CAP_INT64_DIVMOD: - case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: @@ -155,12 +161,10 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_FLOAT_LINEAR: case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: case PIPE_CAP_POLYGON_OFFSET_CLAMP: - case PIPE_CAP_POST_DEPTH_COVERAGE: case PIPE_CAP_QUERY_SO_OVERFLOW: case PIPE_CAP_QUERY_BUFFER_OBJECT: case PIPE_CAP_TGSI_TEX_TXF_LZ: case PIPE_CAP_TGSI_TXQS: - case PIPE_CAP_TGSI_FS_FBFETCH: case PIPE_CAP_TGSI_CLOCK: case PIPE_CAP_TGSI_BALLOT: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: @@ -170,17 +174,25 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS: - case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_LOAD_CONSTBUF: + case PIPE_CAP_NIR_COMPACT_ARRAYS: + case PIPE_CAP_DRAW_PARAMETERS: + case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: + case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES: + case PIPE_CAP_INVALIDATE_BUFFER: return true; - + case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE: + case PIPE_CAP_TGSI_FS_FBFETCH: + case PIPE_CAP_POST_DEPTH_COVERAGE: + case PIPE_CAP_SHADER_STENCIL_EXPORT: + return devinfo->gen >= 9; case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: return BRW_MAX_DRAW_BUFFERS; case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: - return 15; /* 16384x16384 */ + return IRIS_MAX_MIPLEVELS; /* 16384x16384 */ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: return 12; /* 2048x2048 */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: @@ -198,6 +210,8 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */ return 32; + case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: + return IRIS_MAP_BUFFER_ALIGNMENT; case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: /* Choose a cacheline (64 bytes) so that we can safely have the CPU and * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With @@ -236,8 +250,9 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DEVICE_ID: return screen->pci_id; case PIPE_CAP_VIDEO_MEMORY: - return 0xffffffff; // XXX: bogus + return INT_MAX; // XXX: bogus case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_MAX_VARYINGS: return 32; case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: /* AMD_pinned_memory assumes the flexibility of using client memory @@ -249,6 +264,11 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) */ return devinfo->has_llc; + case PIPE_CAP_CONTEXT_PRIORITY_MASK: + return PIPE_CONTEXT_PRIORITY_LOW | + PIPE_CONTEXT_PRIORITY_MEDIUM | + PIPE_CONTEXT_PRIORITY_HIGH; + // XXX: don't hardcode 00:00:02.0 PCI here case PIPE_CAP_PCI_GROUP: return 0; @@ -295,8 +315,6 @@ iris_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type p_stage, enum pipe_shader_cap param) { - struct iris_screen *screen = (struct iris_screen *)pscreen; - struct brw_compiler *compiler = screen->compiler; gl_shader_stage stage = stage_from_pipe(p_stage); /* this is probably not totally correct.. but it's a start: */ @@ -324,13 +342,14 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 0; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput; case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput; case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp; case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - return 1; + /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects, + * which we don't want. Our compiler backend will check brw_compiler's + * options and call nir_lower_indirect_derefs appropriately anyway. + */ + return true; case PIPE_SHADER_CAP_SUBROUTINES: return 0; case PIPE_SHADER_CAP_INTEGERS: @@ -375,11 +394,8 @@ iris_get_compute_param(struct pipe_screen *pscreen, void *ret) { struct iris_screen *screen = (struct iris_screen *)pscreen; - struct brw_compiler *compiler = screen->compiler; const struct gen_device_info *devinfo = &screen->devinfo; - // XXX: cherryview fusing - const unsigned max_threads = MIN2(64, devinfo->max_cs_threads); const uint32_t max_invocations = 32 * max_threads; @@ -457,6 +473,8 @@ iris_destroy_screen(struct pipe_screen *pscreen) { struct iris_screen *screen = (struct iris_screen *) pscreen; iris_bo_unreference(screen->workaround_bo); + u_transfer_helper_destroy(pscreen->transfer_helper); + iris_bufmgr_destroy(screen->bufmgr); ralloc_free(screen); } @@ -489,13 +507,6 @@ iris_getparam(struct iris_screen *screen, int param, int *value) return 0; } -static bool -iris_getparam_boolean(struct iris_screen *screen, int param) -{ - int value = 0; - return (iris_getparam(screen, param, &value) == 0) && value; -} - static int iris_getparam_integer(struct iris_screen *screen, int param) { @@ -528,17 +539,24 @@ iris_shader_perf_log(void *data, const char *fmt, ...) struct pipe_debug_callback *dbg = data; unsigned id = 0; va_list args; + va_start(args, fmt); - if (!dbg->debug_message) - return; + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { + va_list args_copy; + va_copy(args_copy, args); + vfprintf(stderr, fmt, args_copy); + va_end(args_copy); + } + + if (dbg->debug_message) { + dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); + } - va_start(args, fmt); - dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); va_end(args); } struct pipe_screen * -iris_screen_create(int fd) +iris_screen_create(int fd, const struct pipe_screen_config *config) { struct iris_screen *screen = rzalloc(NULL, struct iris_screen); if (!screen) @@ -550,9 +568,15 @@ iris_screen_create(int fd) if (!gen_get_device_info(screen->pci_id, &screen->devinfo)) return NULL; + if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview) + return NULL; + screen->devinfo.timestamp_frequency = iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY); + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; + screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd); if (!screen->bufmgr) return NULL; @@ -564,8 +588,12 @@ iris_screen_create(int fd) brw_process_intel_debug_variable(); - bool hw_has_swizzling = false; // XXX: detect? - isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling); + screen->driconf.dual_color_blend_by_location = + driQueryOptionb(config->options, "dual_color_blend_by_location"); + + screen->precompile = env_var_as_boolean("shader_precompile", true); + + isl_device_init(&screen->isl_dev, &screen->devinfo, false); screen->compiler = brw_compiler_create(screen, &screen->devinfo); screen->compiler->shader_debug_log = iris_shader_debug_log;