X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_screen.c;h=3b391f1db5d309177dd03ee9994347c8289d6c22;hb=d0a8ad77e99385175b8266f4dc4d66dd2baa85e7;hp=0ee07a7e4f65224934eaabbf3af5bb9743fea67e;hpb=be49fb051d236306579e33b90a65cb7b7b94c3e2;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 0ee07a7e4f6..3b391f1db5d 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -39,10 +39,11 @@ #include "pipe/p_screen.h" #include "util/debug.h" #include "util/u_inlines.h" -#include "util/u_format.h" +#include "util/format/u_format.h" #include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" #include "util/ralloc.h" +#include "util/xmlconfig.h" #include "drm-uapi/i915_drm.h" #include "iris_context.h" #include "iris_defines.h" @@ -50,7 +51,11 @@ #include "iris_pipe.h" #include "iris_resource.h" #include "iris_screen.h" +#include "compiler/glsl_types.h" #include "intel/compiler/brw_compiler.h" +#include "intel/common/gen_gem.h" +#include "intel/common/gen_l3_config.h" +#include "iris_monitor.h" static void iris_flush_frontbuffer(struct pipe_screen *_screen, @@ -63,7 +68,7 @@ iris_flush_frontbuffer(struct pipe_screen *_screen, static const char * iris_get_vendor(struct pipe_screen *pscreen) { - return "Mesa Project"; + return "Intel"; } static const char * @@ -76,17 +81,14 @@ static const char * iris_get_name(struct pipe_screen *pscreen) { struct iris_screen *screen = (struct iris_screen *)pscreen; - const char *chipset; + static char buf[128]; + const char *name = gen_get_device_name(screen->pci_id); - switch (screen->pci_id) { -#undef CHIPSET -#define CHIPSET(id, symbol, str) case id: chipset = str; break; -#include "pci_ids/i965_pci_ids.h" - default: - chipset = "Unknown Intel Chipset"; - break; - } - return chipset; + if (!name) + name = "Intel Unknown"; + + snprintf(buf, sizeof(buf), "Mesa %s", name); + return buf; } static int @@ -104,8 +106,11 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: case PIPE_CAP_BLEND_EQUATION_SEPARATE: - case PIPE_CAP_SM3: + case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: + case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: + case PIPE_CAP_VERTEX_SHADER_SATURATE: case PIPE_CAP_PRIMITIVE_RESTART: + case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: case PIPE_CAP_INDEP_BLEND_ENABLE: case PIPE_CAP_INDEP_BLEND_FUNC: case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND: @@ -133,10 +138,13 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SAMPLE_SHADING: case PIPE_CAP_FORCE_PERSAMPLE_INTERP: case PIPE_CAP_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: + case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_ACCELERATED: case PIPE_CAP_UMA: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: @@ -146,9 +154,9 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DOUBLES: case PIPE_CAP_INT64: case PIPE_CAP_INT64_DIVMOD: - case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: + case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: case PIPE_CAP_CULL_DISTANCE: @@ -165,6 +173,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_BALLOT: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: case PIPE_CAP_CLEAR_TEXTURE: + case PIPE_CAP_CLEAR_SCISSORED: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: case PIPE_CAP_TEXTURE_GATHER_SM5: @@ -172,18 +181,41 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS: case PIPE_CAP_LOAD_CONSTBUF: case PIPE_CAP_NIR_COMPACT_ARRAYS: + case PIPE_CAP_DRAW_PARAMETERS: + case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: + case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: + case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES: + case PIPE_CAP_INVALIDATE_BUFFER: + case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: + case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: + case PIPE_CAP_TEXTURE_SHADOW_LOD: + case PIPE_CAP_SHADER_SAMPLES_IDENTICAL: + case PIPE_CAP_GL_SPIRV: + case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS: + case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION: + case PIPE_CAP_NATIVE_FENCE_FD: + case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: return true; - case PIPE_CAP_TGSI_FS_FBFETCH: + case PIPE_CAP_FBFETCH: + return BRW_MAX_DRAW_BUFFERS; + case PIPE_CAP_FBFETCH_COHERENT: + case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE: case PIPE_CAP_POST_DEPTH_COVERAGE: case PIPE_CAP_SHADER_STENCIL_EXPORT: + case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: + case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK: + case PIPE_CAP_ATOMIC_FLOAT_MINMAX: return devinfo->gen >= 9; + case PIPE_CAP_DEPTH_BOUNDS_TEST: + return devinfo->gen >= 12; case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: return BRW_MAX_DRAW_BUFFERS; - case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_2D_SIZE: + return 16384; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: - return 15; /* 16384x16384 */ + return IRIS_MAX_MIPLEVELS; /* 16384x16384 */ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: return 12; /* 2048x2048 */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: @@ -195,12 +227,13 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: return BRW_MAX_SOL_BINDINGS; case PIPE_CAP_GLSL_FEATURE_LEVEL: - return 460; case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: - return 140; + return 460; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */ return 32; + case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: + return IRIS_MAP_BUFFER_ALIGNMENT; case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: /* Choose a cacheline (64 bytes) so that we can safely have the CPU and * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With @@ -215,7 +248,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: return 16; // XXX: u_screen says 256 is the minimum value... case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: - return true; // XXX: ????? + return true; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: return IRIS_MAX_TEXTURE_BUFFER_SIZE; case PIPE_CAP_MAX_VIEWPORTS: @@ -238,8 +271,28 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0x8086; case PIPE_CAP_DEVICE_ID: return screen->pci_id; - case PIPE_CAP_VIDEO_MEMORY: - return 0xffffffff; // XXX: bogus + case PIPE_CAP_VIDEO_MEMORY: { + /* Once a batch uses more than 75% of the maximum mappable size, we + * assume that there's some fragmentation, and we start doing extra + * flushing, etc. That's the big cliff apps will care about. + */ + const unsigned gpu_mappable_megabytes = + (devinfo->aperture_bytes * 3 / 4) / (1024 * 1024); + + const long system_memory_pages = sysconf(_SC_PHYS_PAGES); + const long system_page_size = sysconf(_SC_PAGE_SIZE); + + if (system_memory_pages <= 0 || system_page_size <= 0) + return -1; + + const uint64_t system_memory_bytes = + (uint64_t) system_memory_pages * (uint64_t) system_page_size; + + const unsigned system_memory_megabytes = + (unsigned) (system_memory_bytes / (1024 * 1024)); + + return MIN2(system_memory_megabytes, gpu_mappable_megabytes); + } case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: case PIPE_CAP_MAX_VARYINGS: return 32; @@ -252,6 +305,16 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) * illegal snoop <-> snoop transfers. */ return devinfo->has_llc; + case PIPE_CAP_THROTTLE: + return screen->driconf.disable_throttling ? 0 : 1; + + case PIPE_CAP_CONTEXT_PRIORITY_MASK: + return PIPE_CONTEXT_PRIORITY_LOW | + PIPE_CONTEXT_PRIORITY_MEDIUM | + PIPE_CONTEXT_PRIORITY_HIGH; + + case PIPE_CAP_FRONTEND_NOOP: + return true; // XXX: don't hardcode 00:00:02.0 PCI here case PIPE_CAP_PCI_GROUP: @@ -263,6 +326,10 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_PCI_FUNCTION: return 0; + case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS: + case PIPE_CAP_INTEGER_MULTIPLY_32X16: + return true; + default: return u_pipe_screen_get_param_defaults(pscreen, param); } @@ -299,8 +366,6 @@ iris_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type p_stage, enum pipe_shader_cap param) { - struct iris_screen *screen = (struct iris_screen *)pscreen; - struct brw_compiler *compiler = screen->compiler; gl_shader_stage stage = stage_from_pipe(p_stage); /* this is probably not totally correct.. but it's a start: */ @@ -339,10 +404,12 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_SUBROUTINES: return 0; case PIPE_SHADER_CAP_INTEGERS: - case PIPE_SHADER_CAP_SCALAR_ISA: return 1; case PIPE_SHADER_CAP_INT64_ATOMICS: case PIPE_SHADER_CAP_FP16: + case PIPE_SHADER_CAP_FP16_DERIVATIVES: + case PIPE_SHADER_CAP_INT16: + case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS: return 0; case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: @@ -356,17 +423,17 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_SUPPORTED_IRS: - return 1 << PIPE_SHADER_IR_NIR; - case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: - return 32; + return (1 << PIPE_SHADER_IR_NIR); + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: + return 1; case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: + case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 0; default: unreachable("unknown shader param"); @@ -380,9 +447,9 @@ iris_get_compute_param(struct pipe_screen *pscreen, void *ret) { struct iris_screen *screen = (struct iris_screen *)pscreen; - struct brw_compiler *compiler = screen->compiler; const struct gen_device_info *devinfo = &screen->devinfo; + /* Limit max_threads to 64 for the GPGPU_WALKER command. */ const unsigned max_threads = MIN2(64, devinfo->max_cs_threads); const uint32_t max_invocations = 32 * max_threads; @@ -393,9 +460,6 @@ iris_get_compute_param(struct pipe_screen *pscreen, } while (0) switch (param) { - case PIPE_COMPUTE_CAP_ADDRESS_BITS: - RET((uint32_t []){ 32 }); - case PIPE_COMPUTE_CAP_IR_TARGET: if (ret) strcpy(ret, "gen"); @@ -413,25 +477,25 @@ iris_get_compute_param(struct pipe_screen *pscreen, case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: /* MaxComputeWorkGroupInvocations */ + case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: + /* MaxComputeVariableGroupInvocations */ RET((uint64_t []) { max_invocations }); case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* MaxComputeSharedMemorySize */ RET((uint64_t []) { 64 * 1024 }); - case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: - RET((uint32_t []) { 1 }); - case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: RET((uint32_t []) { BRW_SUBGROUP_SIZE }); + case PIPE_COMPUTE_CAP_ADDRESS_BITS: + case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: - case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: // XXX: I think these are for Clover... return 0; @@ -449,22 +513,30 @@ iris_get_timestamp(struct pipe_screen *pscreen) iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result); - result = iris_timebase_scale(&screen->devinfo, result); + result = gen_device_info_timebase_scale(&screen->devinfo, result); result &= (1ull << TIMESTAMP_BITS) - 1; return result; } -static void -iris_destroy_screen(struct pipe_screen *pscreen) +void +iris_screen_destroy(struct iris_screen *screen) { - struct iris_screen *screen = (struct iris_screen *) pscreen; + glsl_type_singleton_decref(); iris_bo_unreference(screen->workaround_bo); - u_transfer_helper_destroy(pscreen->transfer_helper); - iris_bufmgr_destroy(screen->bufmgr); + u_transfer_helper_destroy(screen->base.transfer_helper); + iris_bufmgr_unref(screen->bufmgr); + disk_cache_destroy(screen->disk_cache); + close(screen->winsys_fd); ralloc_free(screen); } +static void +iris_screen_unref(struct pipe_screen *pscreen) +{ + iris_pscreen_unref(pscreen); +} + static void iris_query_memory_info(struct pipe_screen *pscreen, struct pipe_memory_info *info) @@ -483,35 +555,46 @@ iris_get_compiler_options(struct pipe_screen *pscreen, return screen->compiler->glsl_compiler_options[stage].NirOptions; } +static struct disk_cache * +iris_get_disk_shader_cache(struct pipe_screen *pscreen) +{ + struct iris_screen *screen = (struct iris_screen *) pscreen; + return screen->disk_cache; +} + static int -iris_getparam(struct iris_screen *screen, int param, int *value) +iris_getparam(int fd, int param, int *value) { struct drm_i915_getparam gp = { .param = param, .value = value }; - if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) + if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1) return -errno; return 0; } -static bool -iris_getparam_boolean(struct iris_screen *screen, int param) -{ - int value = 0; - return (iris_getparam(screen, param, &value) == 0) && value; -} - static int -iris_getparam_integer(struct iris_screen *screen, int param) +iris_getparam_integer(int fd, int param) { int value = -1; - if (iris_getparam(screen, param, &value) == 0) + if (iris_getparam(fd, param, &value) == 0) return value; return -1; } +static const struct gen_l3_config * +iris_get_default_l3_config(const struct gen_device_info *devinfo, + bool compute) +{ + bool wants_dc_cache = true; + bool has_slm = compute; + const struct gen_l3_weights w = + gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm); + return gen_get_l3_config(devinfo, w); +} + static void iris_shader_debug_log(void *data, const char *fmt, ...) { @@ -533,68 +616,150 @@ iris_shader_perf_log(void *data, const char *fmt, ...) struct pipe_debug_callback *dbg = data; unsigned id = 0; va_list args; + va_start(args, fmt); - if (!dbg->debug_message) - return; + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { + va_list args_copy; + va_copy(args_copy, args); + vfprintf(stderr, fmt, args_copy); + va_end(args_copy); + } + + if (dbg->debug_message) { + dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); + } - va_start(args, fmt); - dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); va_end(args); } +static void +iris_detect_kernel_features(struct iris_screen *screen) +{ + /* Kernel 5.2+ */ + if (gen_gem_supports_syncobj_wait(screen->fd)) + screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT; +} + +static bool +iris_init_identifier_bo(struct iris_screen *screen) +{ + void *bo_map; + + bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE); + if (!bo_map) + return false; + + screen->workaround_bo->kflags |= EXEC_OBJECT_CAPTURE; + screen->workaround_address = (struct iris_address) { + .bo = screen->workaround_bo, + .offset = ALIGN( + intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8), + }; + + iris_bo_unmap(screen->workaround_bo); + + return true; +} + struct pipe_screen * -iris_screen_create(int fd) +iris_screen_create(int fd, const struct pipe_screen_config *config) { + /* Here are the i915 features we need for Iris (in chronoligical order) : + * - I915_PARAM_HAS_EXEC_NO_RELOC (3.10) + * - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10) + * - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13) + * - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14) + * - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16) + * + * Checking the last feature availability will include all previous ones. + */ + if (iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION) <= 0) { + debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n"); + return NULL; + } + struct iris_screen *screen = rzalloc(NULL, struct iris_screen); if (!screen) return NULL; - screen->fd = fd; - screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID); - - if (!gen_get_device_info(screen->pci_id, &screen->devinfo)) + if (!gen_get_device_info_from_fd(fd, &screen->devinfo)) return NULL; + screen->pci_id = screen->devinfo.chipset_id; + screen->no_hw = screen->devinfo.no_hw; + + p_atomic_set(&screen->refcount, 1); if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview) return NULL; - screen->devinfo.timestamp_frequency = - iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY); + bool bo_reuse = false; + int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse"); + switch (bo_reuse_mode) { + case DRI_CONF_BO_REUSE_DISABLED: + break; + case DRI_CONF_BO_REUSE_ALL: + bo_reuse = true; + break; + } - screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd); + screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse); if (!screen->bufmgr) return NULL; + screen->fd = iris_bufmgr_get_fd(screen->bufmgr); + screen->winsys_fd = fd; + + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; + screen->workaround_bo = iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER); if (!screen->workaround_bo) return NULL; + if (!iris_init_identifier_bo(screen)) + return NULL; + brw_process_intel_debug_variable(); + screen->driconf.dual_color_blend_by_location = + driQueryOptionb(config->options, "dual_color_blend_by_location"); + screen->driconf.disable_throttling = + driQueryOptionb(config->options, "disable_throttling"); + screen->driconf.always_flush_cache = + driQueryOptionb(config->options, "always_flush_cache"); + screen->precompile = env_var_as_boolean("shader_precompile", true); - bool hw_has_swizzling = false; // XXX: detect? - isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling); + isl_device_init(&screen->isl_dev, &screen->devinfo, false); screen->compiler = brw_compiler_create(screen, &screen->devinfo); screen->compiler->shader_debug_log = iris_shader_debug_log; screen->compiler->shader_perf_log = iris_shader_perf_log; screen->compiler->supports_pull_constants = false; + screen->compiler->supports_shader_constants = true; + screen->compiler->compact_params = false; + + screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false); + screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true); + + iris_disk_cache_init(screen); slab_create_parent(&screen->transfer_pool, sizeof(struct iris_transfer), 64); screen->subslice_total = - iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL); + iris_getparam_integer(screen->fd, I915_PARAM_SUBSLICE_TOTAL); assert(screen->subslice_total >= 1); + iris_detect_kernel_features(screen); + struct pipe_screen *pscreen = &screen->base; iris_init_screen_fence_functions(pscreen); iris_init_screen_resource_functions(pscreen); - pscreen->destroy = iris_destroy_screen; + pscreen->destroy = iris_screen_unref; pscreen->get_name = iris_get_name; pscreen->get_vendor = iris_get_vendor; pscreen->get_device_vendor = iris_get_device_vendor; @@ -603,11 +768,16 @@ iris_screen_create(int fd) pscreen->get_compute_param = iris_get_compute_param; pscreen->get_paramf = iris_get_paramf; pscreen->get_compiler_options = iris_get_compiler_options; + pscreen->get_disk_shader_cache = iris_get_disk_shader_cache; pscreen->is_format_supported = iris_is_format_supported; pscreen->context_create = iris_create_context; pscreen->flush_frontbuffer = iris_flush_frontbuffer; pscreen->get_timestamp = iris_get_timestamp; pscreen->query_memory_info = iris_query_memory_info; + pscreen->get_driver_query_group_info = iris_get_monitor_group_info; + pscreen->get_driver_query_info = iris_get_monitor_info; + + glsl_type_singleton_init_or_ref(); return pscreen; }