X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Firis%2Firis_screen.c;h=e92685d4ae67abc8606446892ed503fb2feb84b7;hb=de2efd5ea7fafba09a596beba68436c33ebe912e;hp=4a464ab068e8651b4908d5a2711000235b930b7a;hpb=682aeff8d04088c50d3a37e5fa62d002d3f67d91;p=mesa.git diff --git a/src/gallium/drivers/iris/iris_screen.c b/src/gallium/drivers/iris/iris_screen.c index 4a464ab068e..e92685d4ae6 100644 --- a/src/gallium/drivers/iris/iris_screen.c +++ b/src/gallium/drivers/iris/iris_screen.c @@ -4,22 +4,32 @@ * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation - * on the rights to use, copy, modify, merge, publish, distribute, sub - * license, and/or sell copies of the Software, and to permit persons to whom - * the Software is furnished to do so, subject to the following conditions: + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ + +/** + * @file iris_screen.c + * + * Screen related driver hooks and capability lists. + * + * A program may use multiple rendering contexts (iris_context), but + * they all share a common screen (iris_screen). Global driver state + * can be stored in the screen; it may be accessed by multiple threads. + */ + #include #include #include @@ -27,16 +37,23 @@ #include "pipe/p_state.h" #include "pipe/p_context.h" #include "pipe/p_screen.h" +#include "util/debug.h" #include "util/u_inlines.h" #include "util/u_format.h" +#include "util/u_transfer_helper.h" #include "util/u_upload_mgr.h" #include "util/ralloc.h" +#include "util/xmlconfig.h" #include "drm-uapi/i915_drm.h" #include "iris_context.h" +#include "iris_defines.h" +#include "iris_fence.h" #include "iris_pipe.h" #include "iris_resource.h" #include "iris_screen.h" #include "intel/compiler/brw_compiler.h" +#include "intel/common/gen_gem.h" +#include "iris_monitor.h" static void iris_flush_frontbuffer(struct pipe_screen *_screen, @@ -49,7 +66,7 @@ iris_flush_frontbuffer(struct pipe_screen *_screen, static const char * iris_get_vendor(struct pipe_screen *pscreen) { - return "Mesa Project"; + return "Intel"; } static const char * @@ -62,6 +79,7 @@ static const char * iris_get_name(struct pipe_screen *pscreen) { struct iris_screen *screen = (struct iris_screen *)pscreen; + static char buf[128]; const char *chipset; switch (screen->pci_id) { @@ -72,13 +90,24 @@ iris_get_name(struct pipe_screen *pscreen) chipset = "Unknown Intel Chipset"; break; } - return &chipset[9]; + + snprintf(buf, sizeof(buf), "Mesa %s", chipset); + return buf; +} + +static uint64_t +get_aperture_size(int fd) +{ + struct drm_i915_gem_get_aperture aperture = {}; + gen_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture); + return aperture.aper_size; } static int iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) { struct iris_screen *screen = (struct iris_screen *)pscreen; + const struct gen_device_info *devinfo = &screen->devinfo; switch (param) { case PIPE_CAP_NPOT_TEXTURES: @@ -89,7 +118,9 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: case PIPE_CAP_BLEND_EQUATION_SEPARATE: - case PIPE_CAP_SM3: + case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: + case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: + case PIPE_CAP_VERTEX_SHADER_SATURATE: case PIPE_CAP_PRIMITIVE_RESTART: case PIPE_CAP_INDEP_BLEND_ENABLE: case PIPE_CAP_INDEP_BLEND_FUNC: @@ -97,7 +128,6 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_DEPTH_CLIP_DISABLE: - case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: @@ -113,14 +143,19 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: - case PIPE_CAP_QUERY_PIPELINE_STATISTICS: + case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_SAMPLE_SHADING: + case PIPE_CAP_FORCE_PERSAMPLE_INTERP: case PIPE_CAP_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: + case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_ACCELERATED: case PIPE_CAP_UMA: case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: @@ -130,81 +165,79 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DOUBLES: case PIPE_CAP_INT64: case PIPE_CAP_INT64_DIVMOD: - case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: + case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT: case PIPE_CAP_CULL_DISTANCE: case PIPE_CAP_PACKED_UNIFORMS: - case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: case PIPE_CAP_TEXTURE_FLOAT_LINEAR: case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: case PIPE_CAP_POLYGON_OFFSET_CLAMP: + case PIPE_CAP_QUERY_SO_OVERFLOW: + case PIPE_CAP_QUERY_BUFFER_OBJECT: + case PIPE_CAP_TGSI_TEX_TXF_LZ: + case PIPE_CAP_TGSI_TXQS: + case PIPE_CAP_TGSI_CLOCK: + case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: + case PIPE_CAP_CLEAR_TEXTURE: + case PIPE_CAP_TGSI_VOTE: + case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: + case PIPE_CAP_TEXTURE_GATHER_SM5: + case PIPE_CAP_TGSI_ARRAY_COMPONENTS: + case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS: + case PIPE_CAP_LOAD_CONSTBUF: + case PIPE_CAP_NIR_COMPACT_ARRAYS: + case PIPE_CAP_DRAW_PARAMETERS: + case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: + case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: + case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES: + case PIPE_CAP_INVALIDATE_BUFFER: + case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: + case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED: + case PIPE_CAP_TEXTURE_SHADOW_LOD: + case PIPE_CAP_SHADER_SAMPLES_IDENTICAL: return true; - - case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: - case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: - case PIPE_CAP_VERTEX_COLOR_CLAMPED: - case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: - case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: - case PIPE_CAP_FAKE_SW_MSAA: - case PIPE_CAP_VERTEXID_NOBASE: - case PIPE_CAP_FENCE_SIGNAL: - case PIPE_CAP_CONSTBUF0_FLAGS: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: - case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: - case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: - case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - case PIPE_CAP_GENERATE_MIPMAP: - case PIPE_CAP_FORCE_PERSAMPLE_INTERP: - case PIPE_CAP_TEXTURE_GATHER_OFFSETS: - return false; - - case PIPE_CAP_TEXTURE_MIRROR_CLAMP: - /* Intel GPUs don't support PIPE_TEX_WRAP_MIRROR_CLAMP or - * PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER. - */ - return false; - + case PIPE_CAP_FBFETCH: + /* TODO: Support non-coherent FB fetch on Broadwell */ + return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0; + case PIPE_CAP_FBFETCH_COHERENT: + case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE: + case PIPE_CAP_POST_DEPTH_COVERAGE: + case PIPE_CAP_SHADER_STENCIL_EXPORT: + case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: + case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK: + case PIPE_CAP_ATOMIC_FLOAT_MINMAX: + return devinfo->gen >= 9; case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: return 1; case PIPE_CAP_MAX_RENDER_TARGETS: return BRW_MAX_DRAW_BUFFERS; - case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_2D_SIZE: + return 16384; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: - return 15; /* 16384x16384 */ + return IRIS_MAX_MIPLEVELS; /* 16384x16384 */ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: return 12; /* 2048x2048 */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: return 4; case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: return 2048; - case PIPE_CAP_MIN_TEXEL_OFFSET: - return -8; - case PIPE_CAP_MAX_TEXEL_OFFSET: - return 7; case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS; case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: return BRW_MAX_SOL_BINDINGS; case PIPE_CAP_GLSL_FEATURE_LEVEL: - return 460; case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: - return 140; + return 460; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: /* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */ return 32; + case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: + return IRIS_MAP_BUFFER_ALIGNMENT; case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: /* Choose a cacheline (64 bytes) so that we can safely have the CPU and * GPU writing the same SSBO on non-coherent systems (Atom CPUs). With @@ -214,96 +247,86 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param) * cacheline. */ return 64; - case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: - return 64; // XXX: ? + case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: + return 1 << 27; case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: - return 16; + return 16; // XXX: u_screen says 256 is the minimum value... case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: - return true; // XXX: ????? + return true; case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: - return 1 << 27; /* 128MB */ + return IRIS_MAX_TEXTURE_BUFFER_SIZE; case PIPE_CAP_MAX_VIEWPORTS: return 16; - case PIPE_CAP_ENDIANNESS: - return PIPE_ENDIAN_LITTLE; case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES: return 256; case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS: return 1024; + case PIPE_CAP_MAX_GS_INVOCATIONS: + return 32; case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: return 4; - case PIPE_CAP_TEXTURE_GATHER_SM5: - return 1; case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: return -32; case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: return 31; - case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: case PIPE_CAP_MAX_VERTEX_STREAMS: return 4; case PIPE_CAP_VENDOR_ID: return 0x8086; case PIPE_CAP_DEVICE_ID: return screen->pci_id; - case PIPE_CAP_VIDEO_MEMORY: - return 0xffffffff; // XXX: bogus - case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: - return 2048; + case PIPE_CAP_VIDEO_MEMORY: { + /* Once a batch uses more than 75% of the maximum mappable size, we + * assume that there's some fragmentation, and we start doing extra + * flushing, etc. That's the big cliff apps will care about. + */ + const unsigned gpu_mappable_megabytes = + (screen->aperture_bytes * 3 / 4) / (1024 * 1024); + + const long system_memory_pages = sysconf(_SC_PHYS_PAGES); + const long system_page_size = sysconf(_SC_PAGE_SIZE); + + if (system_memory_pages <= 0 || system_page_size <= 0) + return -1; + + const uint64_t system_memory_bytes = + (uint64_t) system_memory_pages * (uint64_t) system_page_size; + + const unsigned system_memory_megabytes = + (unsigned) (system_memory_bytes / (1024 * 1024)); + + return MIN2(system_memory_megabytes, gpu_mappable_megabytes); + } case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: + case PIPE_CAP_MAX_VARYINGS: return 32; - case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: - case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - case PIPE_CAP_DEPTH_BOUNDS_TEST: - case PIPE_CAP_TGSI_TXQS: - case PIPE_CAP_SHAREABLE_SHADERS: - case PIPE_CAP_CLEAR_TEXTURE: - case PIPE_CAP_DRAW_PARAMETERS: - case PIPE_CAP_TGSI_PACK_HALF_FLOAT: - case PIPE_CAP_MULTI_DRAW_INDIRECT: - case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: - case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: - case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: - case PIPE_CAP_INVALIDATE_BUFFER: - case PIPE_CAP_STRING_MARKER: - case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: - case PIPE_CAP_QUERY_BUFFER_OBJECT: - case PIPE_CAP_QUERY_MEMORY_INFO: + /* AMD_pinned_memory assumes the flexibility of using client memory + * for any buffer (incl. vertex buffers) which rules out the prospect + * of using snooped buffers, as using snooped buffers without + * cogniscience is likely to be detrimental to performance and require + * extensive checking in the driver for correctness, e.g. to prevent + * illegal snoop <-> snoop transfers. + */ + return devinfo->has_llc; + + case PIPE_CAP_CONTEXT_PRIORITY_MASK: + return PIPE_CONTEXT_PRIORITY_LOW | + PIPE_CONTEXT_PRIORITY_MEDIUM | + PIPE_CONTEXT_PRIORITY_HIGH; + + // XXX: don't hardcode 00:00:02.0 PCI here case PIPE_CAP_PCI_GROUP: + return 0; case PIPE_CAP_PCI_BUS: + return 0; case PIPE_CAP_PCI_DEVICE: + return 2; case PIPE_CAP_PCI_FUNCTION: - case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: - case PIPE_CAP_TGSI_VOTE: - case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: - case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: - case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: - case PIPE_CAP_TGSI_ARRAY_COMPONENTS: - case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: - case PIPE_CAP_NATIVE_FENCE_FD: - case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: - case PIPE_CAP_TGSI_FS_FBFETCH: - case PIPE_CAP_TGSI_MUL_ZERO_WINS: - case PIPE_CAP_TGSI_TEX_TXF_LZ: - case PIPE_CAP_TGSI_CLOCK: - case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: - case PIPE_CAP_TGSI_BALLOT: - case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: - case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: - case PIPE_CAP_POST_DEPTH_COVERAGE: - case PIPE_CAP_BINDLESS_TEXTURE: - case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: - case PIPE_CAP_QUERY_SO_OVERFLOW: - case PIPE_CAP_MEMOBJ: - case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: - case PIPE_CAP_TILE_RASTER_ORDER: - case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: - case PIPE_CAP_CONTEXT_PRIORITY_MASK: - // XXX: TODO: fill these out - break; + return 0; + + default: + return u_pipe_screen_get_param_defaults(pscreen, param); } return 0; } @@ -338,8 +361,6 @@ iris_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type p_stage, enum pipe_shader_cap param) { - struct iris_screen *screen = (struct iris_screen *)pscreen; - struct brw_compiler *compiler = screen->compiler; gl_shader_stage stage = stage_from_pipe(p_stage); /* this is probably not totally correct.. but it's a start: */ @@ -367,13 +388,14 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: return 0; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput; case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput; case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: - return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp; case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: - return 1; + /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects, + * which we don't want. Our compiler backend will check brw_compiler's + * options and call nir_lower_indirect_derefs appropriately anyway. + */ + return true; case PIPE_SHADER_CAP_SUBROUTINES: return 0; case PIPE_SHADER_CAP_INTEGERS: @@ -394,17 +416,17 @@ iris_get_shader_param(struct pipe_screen *pscreen, case PIPE_SHADER_CAP_PREFERRED_IR: return PIPE_SHADER_IR_NIR; case PIPE_SHADER_CAP_SUPPORTED_IRS: - return 0; - case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: - return 32; + return 1 << PIPE_SHADER_IR_NIR; + case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: + return 1; case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: - case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED: + case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: return 0; default: unreachable("unknown shader param"); @@ -417,14 +439,79 @@ iris_get_compute_param(struct pipe_screen *pscreen, enum pipe_compute_cap param, void *ret) { - /* TODO: compute shaders */ - return 0; + struct iris_screen *screen = (struct iris_screen *)pscreen; + const struct gen_device_info *devinfo = &screen->devinfo; + + const unsigned max_threads = MIN2(64, devinfo->max_cs_threads); + const uint32_t max_invocations = 32 * max_threads; + +#define RET(x) do { \ + if (ret) \ + memcpy(ret, x, sizeof(x)); \ + return sizeof(x); \ +} while (0) + + switch (param) { + case PIPE_COMPUTE_CAP_ADDRESS_BITS: + RET((uint32_t []){ 32 }); + + case PIPE_COMPUTE_CAP_IR_TARGET: + if (ret) + strcpy(ret, "gen"); + return 4; + + case PIPE_COMPUTE_CAP_GRID_DIMENSION: + RET((uint64_t []) { 3 }); + + case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: + RET(((uint64_t []) { 65535, 65535, 65535 })); + + case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: + /* MaxComputeWorkGroupSize[0..2] */ + RET(((uint64_t []) {max_invocations, max_invocations, max_invocations})); + + case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: + /* MaxComputeWorkGroupInvocations */ + RET((uint64_t []) { max_invocations }); + + case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: + /* MaxComputeSharedMemorySize */ + RET((uint64_t []) { 64 * 1024 }); + + case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED: + RET((uint32_t []) { 1 }); + + case PIPE_COMPUTE_CAP_SUBGROUP_SIZE: + RET((uint32_t []) { BRW_SUBGROUP_SIZE }); + + case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE: + case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY: + case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: + case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: + case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: + case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: + case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK: + // XXX: I think these are for Clover... + return 0; + + default: + unreachable("unknown compute param"); + } } static uint64_t iris_get_timestamp(struct pipe_screen *pscreen) { - return 0; + struct iris_screen *screen = (struct iris_screen *) pscreen; + const unsigned TIMESTAMP = 0x2358; + uint64_t result; + + iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result); + + result = gen_device_info_timebase_scale(&screen->devinfo, result); + result &= (1ull << TIMESTAMP_BITS) - 1; + + return result; } static void @@ -432,25 +519,12 @@ iris_destroy_screen(struct pipe_screen *pscreen) { struct iris_screen *screen = (struct iris_screen *) pscreen; iris_bo_unreference(screen->workaround_bo); + u_transfer_helper_destroy(pscreen->transfer_helper); + iris_bufmgr_destroy(screen->bufmgr); + disk_cache_destroy(screen->disk_cache); ralloc_free(screen); } -static void -iris_fence_reference(struct pipe_screen *screen, - struct pipe_fence_handle **ptr, - struct pipe_fence_handle *fence) -{ -} - -static boolean -iris_fence_finish(struct pipe_screen *screen, - struct pipe_context *ctx, - struct pipe_fence_handle *fence, - uint64_t timeout) -{ - return true; -} - static void iris_query_memory_info(struct pipe_screen *pscreen, struct pipe_memory_info *info) @@ -469,6 +543,13 @@ iris_get_compiler_options(struct pipe_screen *pscreen, return screen->compiler->glsl_compiler_options[stage].NirOptions; } +static struct disk_cache * +iris_get_disk_shader_cache(struct pipe_screen *pscreen) +{ + struct iris_screen *screen = (struct iris_screen *) pscreen; + return screen->disk_cache; +} + static int iris_getparam(struct iris_screen *screen, int param, int *value) { @@ -480,13 +561,6 @@ iris_getparam(struct iris_screen *screen, int param, int *value) return 0; } -static bool -iris_getparam_boolean(struct iris_screen *screen, int param) -{ - int value = 0; - return (iris_getparam(screen, param, &value) == 0) && value; -} - static int iris_getparam_integer(struct iris_screen *screen, int param) { @@ -519,27 +593,43 @@ iris_shader_perf_log(void *data, const char *fmt, ...) struct pipe_debug_callback *dbg = data; unsigned id = 0; va_list args; + va_start(args, fmt); - if (!dbg->debug_message) - return; + if (unlikely(INTEL_DEBUG & DEBUG_PERF)) { + va_list args_copy; + va_copy(args_copy, args); + vfprintf(stderr, fmt, args_copy); + va_end(args_copy); + } + + if (dbg->debug_message) { + dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); + } - va_start(args, fmt); - dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args); va_end(args); } struct pipe_screen * -iris_screen_create(int fd) +iris_screen_create(int fd, const struct pipe_screen_config *config) { struct iris_screen *screen = rzalloc(NULL, struct iris_screen); if (!screen) return NULL; screen->fd = fd; - screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID); - if (!gen_get_device_info(screen->pci_id, &screen->devinfo)) + if (!gen_get_device_info_from_fd(fd, &screen->devinfo)) return NULL; + screen->pci_id = screen->devinfo.chipset_id; + screen->no_hw = screen->devinfo.no_hw; + + if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview) + return NULL; + + screen->aperture_bytes = get_aperture_size(fd); + + if (getenv("INTEL_NO_HW") != NULL) + screen->no_hw = true; screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd); if (!screen->bufmgr) @@ -552,18 +642,31 @@ iris_screen_create(int fd) brw_process_intel_debug_variable(); - bool hw_has_swizzling = false; // XXX: detect? - isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling); + screen->driconf.dual_color_blend_by_location = + driQueryOptionb(config->options, "dual_color_blend_by_location"); + + screen->precompile = env_var_as_boolean("shader_precompile", true); + + isl_device_init(&screen->isl_dev, &screen->devinfo, false); screen->compiler = brw_compiler_create(screen, &screen->devinfo); screen->compiler->shader_debug_log = iris_shader_debug_log; screen->compiler->shader_perf_log = iris_shader_perf_log; + screen->compiler->supports_pull_constants = false; + screen->compiler->supports_shader_constants = true; + + iris_disk_cache_init(screen); slab_create_parent(&screen->transfer_pool, sizeof(struct iris_transfer), 64); + screen->subslice_total = + iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL); + assert(screen->subslice_total >= 1); + struct pipe_screen *pscreen = &screen->base; + iris_init_screen_fence_functions(pscreen); iris_init_screen_resource_functions(pscreen); pscreen->destroy = iris_destroy_screen; @@ -575,13 +678,14 @@ iris_screen_create(int fd) pscreen->get_compute_param = iris_get_compute_param; pscreen->get_paramf = iris_get_paramf; pscreen->get_compiler_options = iris_get_compiler_options; + pscreen->get_disk_shader_cache = iris_get_disk_shader_cache; pscreen->is_format_supported = iris_is_format_supported; pscreen->context_create = iris_create_context; pscreen->flush_frontbuffer = iris_flush_frontbuffer; pscreen->get_timestamp = iris_get_timestamp; - pscreen->fence_reference = iris_fence_reference; - pscreen->fence_finish = iris_fence_finish; pscreen->query_memory_info = iris_query_memory_info; + pscreen->get_driver_query_group_info = iris_get_monitor_group_info; + pscreen->get_driver_query_info = iris_get_monitor_info; return pscreen; }