X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fnouveau%2Fnvc0%2Fnvc0_vbo.c;h=7d6be9382d1848f7815b923777ff5dce94ab5b25;hb=a110a8090d656152827a1828098624a17f6d7fb7;hp=032b3c125cf8b6a72d3f0c7de64d9ce9bcfd9eeb;hpb=ff8895ba5606372f368917b97b8c4380bb822234;p=mesa.git diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c index 032b3c125cf..7d6be9382d1 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c @@ -80,7 +80,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe, enum pipe_format fmt = ve->src_format; so->element[i].pipe = elements[i]; - so->element[i].state = nvc0_format_table[fmt].vtx; + so->element[i].state = nvc0_vertex_format[fmt].vtx; if (!so->element[i].state) { switch (util_format_get_nr_components(fmt)) { @@ -93,7 +93,7 @@ nvc0_vertex_state_create(struct pipe_context *pipe, FREE(so); return NULL; } - so->element[i].state = nvc0_format_table[fmt].vtx; + so->element[i].state = nvc0_vertex_format[fmt].vtx; so->need_conversion = true; pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK, "Converting vertex element %d, no hw format %s", @@ -176,8 +176,8 @@ nvc0_set_constant_vertex_attrib(struct nvc0_context *nvc0, const unsigned a) uint32_t mode; const struct util_format_description *desc; void *dst; - const void *src = (const uint8_t *)vb->user_buffer + ve->src_offset; - assert(!vb->buffer); + const void *src = (const uint8_t *)vb->buffer.user + ve->src_offset; + assert(vb->is_user_buffer); desc = util_format_description(ve->src_format); @@ -222,7 +222,7 @@ static inline void nvc0_release_user_vbufs(struct nvc0_context *nvc0) { if (nvc0->vbo_user) { - nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX_TMP); + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX_TMP); nouveau_scratch_done(&nvc0->base); } } @@ -254,10 +254,10 @@ nvc0_update_user_vbufs(struct nvc0_context *nvc0) struct nouveau_bo *bo; const uint32_t bo_flags = NOUVEAU_BO_RD | NOUVEAU_BO_GART; written |= 1 << b; - address[b] = nouveau_scratch_data(&nvc0->base, vb->user_buffer, + address[b] = nouveau_scratch_data(&nvc0->base, vb->buffer.user, base, size, &bo); if (bo) - BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo); + BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo); NOUVEAU_DRV_STAT(&nvc0->screen->base, user_buffer_upload_bytes, size); } @@ -289,10 +289,10 @@ nvc0_update_user_vbufs_shared(struct nvc0_context *nvc0) nvc0_user_vbuf_range(nvc0, b, &base, &size); - address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].user_buffer, + address = nouveau_scratch_data(&nvc0->base, nvc0->vtxbuf[b].buffer.user, base, size, &bo); if (bo) - BCTX_REFN_bo(nvc0->bufctx_3d, VTX_TMP, bo_flags, bo); + BCTX_REFN_bo(nvc0->bufctx_3d, 3D_VTX_TMP, bo_flags, bo); BEGIN_1IC0(push, NVC0_3D(MACRO_VERTEX_ARRAY_SELECT), 5); PUSH_DATA (push, b); @@ -346,9 +346,9 @@ nvc0_validate_vertex_buffers(struct nvc0_context *nvc0) /* address/value set in nvc0_update_user_vbufs */ continue; } - res = nv04_resource(vb->buffer); + res = nv04_resource(vb->buffer.resource); offset = ve->pipe.src_offset + vb->buffer_offset; - limit = vb->buffer->width0 - 1; + limit = vb->buffer.resource->width0 - 1; if (unlikely(ve->pipe.instance_divisor)) { BEGIN_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(i)), 4); @@ -368,7 +368,7 @@ nvc0_validate_vertex_buffers(struct nvc0_context *nvc0) if (!(refd & (1 << b))) { refd |= 1 << b; - BCTX_REFN(nvc0->bufctx_3d, VTX, res, RD); + BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, res, RD); } } if (nvc0->vbo_user) @@ -395,12 +395,12 @@ nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0) } /* address/value set in nvc0_update_user_vbufs_shared */ continue; - } else if (!vb->buffer) { + } else if (!vb->buffer.resource) { /* there can be holes in the vertex buffer lists */ IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FETCH(b)), 0); continue; } - buf = nv04_resource(vb->buffer); + buf = nv04_resource(vb->buffer.resource); offset = vb->buffer_offset; limit = buf->base.width0 - 1; @@ -412,7 +412,7 @@ nvc0_validate_vertex_buffers_shared(struct nvc0_context *nvc0) PUSH_DATAh(push, buf->address + limit); PUSH_DATA (push, buf->address + limit); - BCTX_REFN(nvc0->bufctx_3d, VTX, buf, RD); + BCTX_REFN(nvc0->bufctx_3d, 3D_VTX, buf, RD); } /* If there are more elements than buffers, we might not have unset * fetching on the later elements. @@ -435,18 +435,20 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0) uint8_t vbo_mode; bool update_vertex; - nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_VTX); + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_VTX); assert(vertex); if (unlikely(vertex->need_conversion) || unlikely(nvc0->vertprog->vp.edgeflag < PIPE_MAX_ATTRIBS)) { vbo_mode = 3; + } else if (nvc0->vbo_user & ~nvc0->constant_vbos) { + vbo_mode = nvc0->vbo_push_hint ? 1 : 0; } else { - vbo_mode = (nvc0->vbo_user && nvc0->vbo_push_hint) ? 1 : 0; + vbo_mode = 0; } const_vbos = vbo_mode ? 0 : nvc0->constant_vbos; - update_vertex = (nvc0->dirty & NVC0_NEW_VERTEX) || + update_vertex = (nvc0->dirty_3d & NVC0_NEW_3D_VERTEX) || (const_vbos != nvc0->state.constant_vbos) || (vbo_mode != nvc0->state.vbo_mode); @@ -520,26 +522,6 @@ nvc0_vertex_arrays_validate(struct nvc0_context *nvc0) nvc0_validate_vertex_buffers(nvc0); } -void -nvc0_idxbuf_validate(struct nvc0_context *nvc0) -{ - struct nouveau_pushbuf *push = nvc0->base.pushbuf; - struct nv04_resource *buf = nv04_resource(nvc0->idxbuf.buffer); - - assert(buf); - assert(nouveau_resource_mapped_by_gpu(&buf->base)); - - PUSH_SPACE(push, 6); - BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5); - PUSH_DATAh(push, buf->address + nvc0->idxbuf.offset); - PUSH_DATA (push, buf->address + nvc0->idxbuf.offset); - PUSH_DATAh(push, buf->address + buf->base.width0 - 1); - PUSH_DATA (push, buf->address + buf->base.width0 - 1); - PUSH_DATA (push, nvc0->idxbuf.index_size >> 1); - - BCTX_REFN(nvc0->bufctx_3d, IDX, buf, RD); -} - #define NVC0_PRIM_GL_CASE(n) \ case PIPE_PRIM_##n: return NVC0_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n @@ -586,7 +568,7 @@ nvc0_draw_arrays(struct nvc0_context *nvc0, unsigned prim; if (nvc0->state.index_bias) { - /* index_bias is implied 0 if !info->indexed (really ?) */ + /* index_bias is implied 0 if !info->index_size (really ?) */ /* TODO: can we deactivate it for the VERTEX_BUFFER_FIRST command ? */ PUSH_SPACE(push, 2); IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0); @@ -709,12 +691,13 @@ nvc0_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, static void nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten, + const struct pipe_draw_info *info, unsigned mode, unsigned start, unsigned count, - unsigned instance_count, int32_t index_bias) + unsigned instance_count, int32_t index_bias, + unsigned index_size) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; unsigned prim; - const unsigned index_size = nvc0->idxbuf.index_size; prim = nvc0_prim_gl(mode); @@ -727,7 +710,7 @@ nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten, nvc0->state.index_bias = index_bias; } - if (nvc0->idxbuf.buffer) { + if (!info->has_user_indices) { PUSH_SPACE(push, 1); IMMED_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), prim); do { @@ -743,7 +726,7 @@ nvc0_draw_elements(struct nvc0_context *nvc0, bool shorten, } while (instance_count); IMMED_NVC0(push, NVC0_3D(VERTEX_END_GL), 0); } else { - const void *data = nvc0->idxbuf.user_buffer; + const void *data = info->index.user; while (instance_count--) { PUSH_SPACE(push, 2); @@ -797,7 +780,7 @@ nvc0_draw_stream_output(struct nvc0_context *nvc0, } while (num_instances--) { - nouveau_pushbuf_space(push, 9, 0, 1); + nouveau_pushbuf_space(push, 16, 0, 1); BEGIN_NVC0(push, NVC0_3D(VERTEX_BEGIN_GL), 1); PUSH_DATA (push, mode); BEGIN_NVC0(push, NVC0_3D(DRAW_TFB_BASE), 1); @@ -816,10 +799,11 @@ static void nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) { struct nouveau_pushbuf *push = nvc0->base.pushbuf; - struct nv04_resource *buf = nv04_resource(info->indirect); - struct nv04_resource *buf_count = nv04_resource(info->indirect_params); - unsigned size, macro, count = info->indirect_count, drawid = info->drawid; - uint32_t offset = buf->offset + info->indirect_offset; + struct nv04_resource *buf = nv04_resource(info->indirect->buffer); + struct nv04_resource *buf_count = nv04_resource(info->indirect->indirect_draw_count); + unsigned size, macro, count = info->indirect->draw_count, drawid = info->drawid; + uint32_t offset = buf->offset + info->indirect->offset; + struct nvc0_screen *screen = nvc0->screen; PUSH_SPACE(push, 7); @@ -832,13 +816,15 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) /* Queue things up to let the macros write params to the driver constbuf */ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); - PUSH_DATA (push, 512); - PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9)); - PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9)); - - if (info->indexed) { - assert(nvc0->idxbuf.buffer); - assert(nouveau_resource_mapped_by_gpu(nvc0->idxbuf.buffer)); + PUSH_DATA (push, NVC0_CB_AUX_SIZE); + PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0)); + PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0)); + BEGIN_NVC0(push, NVC0_3D(CB_POS), 1); + PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO); + + if (info->index_size) { + assert(!info->has_user_indices); + assert(nouveau_resource_mapped_by_gpu(info->index.resource)); size = 5; if (buf_count) macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT; @@ -846,7 +832,7 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) macro = NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT; } else { if (nvc0->state.index_bias) { - /* index_bias is implied 0 if !info->indexed (really ?) */ + /* index_bias is implied 0 if !info->index_size (really ?) */ IMMED_NVC0(push, NVC0_3D(VB_ELEMENT_BASE), 0); IMMED_NVC0(push, NVC0_3D(VERTEX_ID_BASE), 0); nvc0->state.index_bias = 0; @@ -865,7 +851,7 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) */ while (count) { unsigned draws = count, pushes, i; - if (info->indirect_stride == size * 4) { + if (info->indirect->stride == size * 4) { draws = MIN2(draws, (NV04_PFIFO_MAX_PACKET_LEN - 4) / size); pushes = 1; } else { @@ -885,20 +871,20 @@ nvc0_draw_indirect(struct nvc0_context *nvc0, const struct pipe_draw_info *info) if (buf_count) { nouveau_pushbuf_data(push, buf_count->bo, - buf_count->offset + info->indirect_params_offset, + buf_count->offset + info->indirect->indirect_draw_count_offset, NVC0_IB_ENTRY_1_NO_PREFETCH | 4); } if (pushes == 1) { nouveau_pushbuf_data(push, buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4 * draws)); - offset += draws * info->indirect_stride; + offset += draws * info->indirect->stride; } else { for (i = 0; i < pushes; i++) { nouveau_pushbuf_data(push, buf->bo, offset, NVC0_IB_ENTRY_1_NO_PREFETCH | (size * 4)); - offset += info->indirect_stride; + offset += info->indirect->stride; } } count -= draws; @@ -932,6 +918,8 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) { struct nvc0_context *nvc0 = nvc0_context(pipe); struct nouveau_pushbuf *push = nvc0->base.pushbuf; + struct nvc0_screen *screen = nvc0->screen; + unsigned vram_domain = NV_VRAM_DOMAIN(&screen->base); int s; /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */ @@ -944,15 +932,16 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) * if index count is larger and we expect repeated vertices, suggest upload. */ nvc0->vbo_push_hint = - info->indexed && (nvc0->vb_elt_limit >= (info->count * 2)); + !info->indirect && info->index_size && + (nvc0->vb_elt_limit >= (info->count * 2)); /* Check whether we want to switch vertex-submission mode. */ - if (nvc0->vbo_user && !(nvc0->dirty & (NVC0_NEW_ARRAYS | NVC0_NEW_VERTEX))) { + if (nvc0->vbo_user && !(nvc0->dirty_3d & (NVC0_NEW_3D_ARRAYS | NVC0_NEW_3D_VERTEX))) { if (nvc0->vbo_push_hint != !!nvc0->state.vbo_mode) if (nvc0->state.vbo_mode != 3) - nvc0->dirty |= NVC0_NEW_ARRAYS; + nvc0->dirty_3d |= NVC0_NEW_3D_ARRAYS; - if (!(nvc0->dirty & NVC0_NEW_ARRAYS) && nvc0->state.vbo_mode == 0) { + if (!(nvc0->dirty_3d & NVC0_NEW_3D_ARRAYS) && nvc0->state.vbo_mode == 0) { if (nvc0->vertex->shared_slots) nvc0_update_user_vbufs_shared(nvc0); else @@ -967,21 +956,57 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices); } - nvc0_state_validate(nvc0, ~0); + if (info->index_size && !info->has_user_indices) { + struct nv04_resource *buf = nv04_resource(info->index.resource); + + assert(buf); + assert(nouveau_resource_mapped_by_gpu(&buf->base)); + + PUSH_SPACE(push, 6); + BEGIN_NVC0(push, NVC0_3D(INDEX_ARRAY_START_HIGH), 5); + PUSH_DATAh(push, buf->address); + PUSH_DATA (push, buf->address); + PUSH_DATAh(push, buf->address + buf->base.width0 - 1); + PUSH_DATA (push, buf->address + buf->base.width0 - 1); + PUSH_DATA (push, info->index_size >> 1); + + BCTX_REFN(nvc0->bufctx_3d, 3D_IDX, buf, RD); + } + + list_for_each_entry(struct nvc0_resident, resident, &nvc0->tex_head, list) { + nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf, + resident->flags); + } + + list_for_each_entry(struct nvc0_resident, resident, &nvc0->img_head, list) { + nvc0_add_resident(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS, resident->buf, + resident->flags); + } + + BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT, vram_domain | NOUVEAU_BO_RD, + screen->text); - if (nvc0->vertprog->vp.need_draw_parameters) { + nvc0_state_validate_3d(nvc0, ~0); + + if (nvc0->vertprog->vp.need_draw_parameters && !info->indirect) { PUSH_SPACE(push, 9); BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); - PUSH_DATA (push, 512); - PUSH_DATAh(push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9)); - PUSH_DATA (push, nvc0->screen->uniform_bo->offset + (5 << 16) + (0 << 9)); - if (!info->indirect) { - BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3); - PUSH_DATA (push, 256 + 128); - PUSH_DATA (push, info->index_bias); - PUSH_DATA (push, info->start_instance); - PUSH_DATA (push, info->drawid); - } + PUSH_DATA (push, NVC0_CB_AUX_SIZE); + PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0)); + PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(0)); + BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 3); + PUSH_DATA (push, NVC0_CB_AUX_DRAW_INFO); + PUSH_DATA (push, info->index_bias); + PUSH_DATA (push, info->start_instance); + PUSH_DATA (push, info->drawid); + } + + if (nvc0->screen->base.class_3d < NVE4_3D_CLASS && + nvc0->seamless_cube_map != nvc0->state.seamless_cube_map) { + nvc0->state.seamless_cube_map = nvc0->seamless_cube_map; + PUSH_SPACE(push, 1); + IMMED_NVC0(push, NVC0_3D(TEX_MISC), + nvc0->seamless_cube_map ? NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0); } push->kick_notify = nvc0_draw_vbo_kick_notify; @@ -1015,10 +1040,11 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) } if (nvc0->state.vbo_mode) { - nvc0_push_vbo(nvc0, info); - push->kick_notify = nvc0_default_kick_notify; - nouveau_pushbuf_bufctx(push, NULL); - return; + if (info->indirect) + nvc0_push_vbo_indirect(nvc0, info); + else + nvc0_push_vbo(nvc0, info); + goto cleanup; } /* space for base instance, flush, and prim restart */ @@ -1033,8 +1059,8 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) nvc0->base.vbo_dirty |= !!nvc0->vtxbufs_coherent; - if (!nvc0->base.vbo_dirty && nvc0->idxbuf.buffer && - nvc0->idxbuf.buffer->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) + if (!nvc0->base.vbo_dirty && info->index_size && !info->has_user_indices && + info->index.resource->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT) nvc0->base.vbo_dirty = true; nvc0_update_prim_restart(nvc0, info->primitive_restart, info->restart_index); @@ -1051,23 +1077,29 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (unlikely(info->count_from_stream_output)) { nvc0_draw_stream_output(nvc0, info); } else - if (info->indexed) { + if (info->index_size) { bool shorten = info->max_index <= 65535; if (info->primitive_restart && info->restart_index > 65535) shorten = false; - nvc0_draw_elements(nvc0, shorten, + nvc0_draw_elements(nvc0, shorten, info, info->mode, info->start, info->count, - info->instance_count, info->index_bias); + info->instance_count, info->index_bias, info->index_size); } else { nvc0_draw_arrays(nvc0, info->mode, info->start, info->count, info->instance_count); } + +cleanup: push->kick_notify = nvc0_default_kick_notify; nvc0_release_user_vbufs(nvc0); nouveau_pushbuf_bufctx(push, NULL); + + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT); + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_IDX); + nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_BINDLESS); }