X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fmidgard%2Fmidgard_compile.c;h=1e09e46218c5100252e7e1017f57e3c08a6b6b1f;hb=7ad6516f3b70e46683bedbe2dc22623d87e13525;hp=edf7eb0b16aecebc7f32cdd55199e36e7c338e8f;hpb=bbc050b82e7a64848078f993b229a79161c1e95e;p=mesa.git diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c index edf7eb0b16a..1e09e46218c 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c @@ -54,11 +54,14 @@ static const struct debug_named_value debug_options[] = { {"msgs", MIDGARD_DBG_MSGS, "Print debug messages"}, {"shaders", MIDGARD_DBG_SHADERS, "Dump shaders in NIR and MIR"}, + {"shaderdb", MIDGARD_DBG_SHADERDB, "Prints shader-db statistics"}, DEBUG_NAMED_VALUE_END }; DEBUG_GET_ONCE_FLAGS_OPTION(midgard_debug, "MIDGARD_MESA_DEBUG", debug_options, 0) +unsigned SHADER_DB_COUNT = 0; + int midgard_debug = 0; #define DBG(fmt, ...) \ @@ -88,6 +91,7 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor) static midgard_instruction m_##name(unsigned ssa, unsigned address) { \ midgard_instruction i = { \ .type = TAG_LOAD_STORE_4, \ + .mask = 0xF, \ .ssa_args = { \ .rname = ssa, \ .uname = -1, \ @@ -95,7 +99,6 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor) }, \ .load_store = { \ .op = midgard_op_##name, \ - .mask = 0xF, \ .swizzle = SWIZZLE_XYZW, \ .address = address \ } \ @@ -111,7 +114,8 @@ midgard_block_add_successor(midgard_block *block, midgard_block *successor) * the corresponding Midgard source */ static midgard_vector_alu_src -vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count) +vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count, + bool half, bool sext) { if (!src) return blank_alu_src; @@ -131,14 +135,21 @@ vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count) midgard_vector_alu_src alu_src = { .rep_low = 0, .rep_high = 0, - .half = 0, /* TODO */ + .half = half, .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle) }; if (is_int) { - /* TODO: sign-extend/zero-extend */ alu_src.mod = midgard_int_normal; + /* Sign/zero-extend if needed */ + + if (half) { + alu_src.mod = sext ? + midgard_int_sign_extend + : midgard_int_zero_extend; + } + /* These should have been lowered away */ assert(!(src->abs || src->negate)); } else { @@ -396,6 +407,8 @@ midgard_nir_lower_fdot2(nir_shader *shader) return progress; } +/* Flushes undefined values to zero */ + static void optimise_nir(nir_shader *nir) { @@ -456,6 +469,8 @@ optimise_nir(nir_shader *nir) } NIR_PASS(progress, nir, nir_opt_undef); + NIR_PASS(progress, nir, nir_undef_to_zero); + NIR_PASS(progress, nir, nir_opt_loop_unroll, nir_var_shader_in | nir_var_shader_out | @@ -588,6 +603,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co /* We need to set the conditional as close as possible */ .precede_break = true, .unit = for_branch ? UNIT_SMUL : UNIT_SADD, + .mask = 1 << COMPONENT_W, .ssa_args = { .src0 = condition, @@ -600,7 +616,6 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co .outmod = midgard_outmod_int_wrap, .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, - .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(alu_src), .src2 = vector_alu_srco_unsigned(alu_src) }, @@ -629,6 +644,7 @@ emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp) midgard_instruction ins = { .type = TAG_ALU_4, .precede_break = true, + .mask = mask_of(nr_comp), .ssa_args = { .src0 = condition, .src1 = condition, @@ -639,7 +655,6 @@ emit_condition_mixed(compiler_context *ctx, nir_alu_src *src, unsigned nr_comp) .outmod = midgard_outmod_int_wrap, .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, - .mask = expand_writemask(mask_of(nr_comp)), .src1 = vector_alu_srco_unsigned(alu_src), .src2 = vector_alu_srco_unsigned(alu_src) }, @@ -660,6 +675,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) midgard_instruction ins = { .type = TAG_ALU_4, + .mask = 1 << COMPONENT_W, .ssa_args = { .src0 = SSA_UNUSED_1, .src1 = offset, @@ -670,7 +686,6 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) .outmod = midgard_outmod_int_wrap, .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, - .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(zero_alu_src), .src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx) }, @@ -682,12 +697,14 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) #define ALU_CASE(nir, _op) \ case nir_op_##nir: \ op = midgard_alu_op_##_op; \ + assert(src_bitsize == dst_bitsize); \ break; #define ALU_CASE_BCAST(nir, _op, count) \ case nir_op_##nir: \ op = midgard_alu_op_##_op; \ broadcast_swizzle = count; \ + assert(src_bitsize == dst_bitsize); \ break; static bool nir_is_fzero_constant(nir_src src) @@ -703,13 +720,35 @@ nir_is_fzero_constant(nir_src src) return true; } +/* Analyze the sizes of the inputs to determine which reg mode. Ops needed + * special treatment override this anyway. */ + +static midgard_reg_mode +reg_mode_for_nir(nir_alu_instr *instr) +{ + unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); + + switch (src_bitsize) { + case 8: + return midgard_reg_mode_8; + case 16: + return midgard_reg_mode_16; + case 32: + return midgard_reg_mode_32; + case 64: + return midgard_reg_mode_64; + default: + unreachable("Invalid bit size"); + } +} + static void emit_alu(compiler_context *ctx, nir_alu_instr *instr) { bool is_ssa = instr->dest.dest.is_ssa; unsigned dest = nir_dest_index(ctx, &instr->dest.dest); - unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components : instr->dest.dest.reg.reg->num_components; + unsigned nr_components = nir_dest_num_components(instr->dest.dest); unsigned nr_inputs = nir_op_infos[instr->op].num_inputs; /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are @@ -728,6 +767,24 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) unsigned broadcast_swizzle = 0; + /* What register mode should we operate in? */ + midgard_reg_mode reg_mode = + reg_mode_for_nir(instr); + + /* Do we need a destination override? Used for inline + * type conversion */ + + midgard_dest_override dest_override = + midgard_dest_override_none; + + /* Should we use a smaller respective source and sign-extend? */ + + bool half_1 = false, sext_1 = false; + bool half_2 = false, sext_2 = false; + + unsigned src_bitsize = nir_src_bit_size(instr->src[0].src); + unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest); + switch (instr->op) { ALU_CASE(fadd, fadd); ALU_CASE(fmul, fmul); @@ -791,6 +848,11 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) ALU_CASE(i2f32, i2f_rtz); ALU_CASE(u2f32, u2f_rtz); + ALU_CASE(f2i16, f2i_rtz); + ALU_CASE(f2u16, f2u_rtz); + ALU_CASE(i2f16, i2f_rtz); + ALU_CASE(u2f16, u2f_rtz); + ALU_CASE(fsin, fsin); ALU_CASE(fcos, fcos); @@ -824,6 +886,57 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) ALU_CASE(fneg, fmov); ALU_CASE(fsat, fmov); + /* For size conversion, we use a move. Ideally though we would squash + * these ops together; maybe that has to happen after in NIR as part of + * propagation...? An earlier algebraic pass ensured we step down by + * only / exactly one size. If stepping down, we use a dest override to + * reduce the size; if stepping up, we use a larger-sized move with a + * half source and a sign/zero-extension modifier */ + + case nir_op_i2i8: + case nir_op_i2i16: + case nir_op_i2i32: + /* If we end up upscale, we'll need a sign-extend on the + * operand (the second argument) */ + + sext_2 = true; + case nir_op_u2u8: + case nir_op_u2u16: + case nir_op_u2u32: { + op = midgard_alu_op_imov; + + if (dst_bitsize == (src_bitsize * 2)) { + /* Converting up */ + half_2 = true; + + /* Use a greater register mode */ + reg_mode++; + } else if (src_bitsize == (dst_bitsize * 2)) { + /* Converting down */ + dest_override = midgard_dest_override_lower; + } + + break; + } + + case nir_op_f2f16: { + assert(src_bitsize == 32); + + op = midgard_alu_op_fmov; + dest_override = midgard_dest_override_lower; + break; + } + + case nir_op_f2f32: { + assert(src_bitsize == 16); + + op = midgard_alu_op_fmov; + half_2 = true; + reg_mode++; + break; + } + + /* For greater-or-equal, we lower to less-or-equal and flip the * arguments */ @@ -956,23 +1069,22 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) bool is_int = midgard_is_integer_op(op); + ins.mask = mask_of(nr_components); + midgard_vector_alu alu = { .op = op, - .reg_mode = midgard_reg_mode_32, - .dest_override = midgard_dest_override_none, + .reg_mode = reg_mode, + .dest_override = dest_override, .outmod = outmod, - /* Writemask only valid for non-SSA NIR */ - .mask = expand_writemask(mask_of(nr_components)), - - .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle)), - .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle)), + .src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, sext_1)), + .src2 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[1], is_int, broadcast_swizzle, half_2, sext_2)), }; /* Apply writemask if non-SSA, keeping in mind that we can't write to components that don't exist */ if (!is_ssa) - alu.mask &= expand_writemask(instr->dest.write_mask); + ins.mask &= instr->dest.write_mask; ins.alu = alu; @@ -1017,21 +1129,22 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) uint8_t original_swizzle[4]; memcpy(original_swizzle, nirmods[0]->swizzle, sizeof(nirmods[0]->swizzle)); + unsigned orig_mask = ins.mask; for (int i = 0; i < nr_components; ++i) { /* Mask the associated component, dropping the * instruction if needed */ - ins.alu.mask = (0x3) << (2 * i); - ins.alu.mask &= alu.mask; + ins.mask = 1 << i; + ins.mask &= orig_mask; - if (!ins.alu.mask) + if (!ins.mask) continue; for (int j = 0; j < 4; ++j) nirmods[0]->swizzle[j] = original_swizzle[i]; /* Pull from the correct component */ - ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle)); + ins.alu.src1 = vector_alu_srco_unsigned(vector_alu_modifiers(nirmods[0], is_int, broadcast_swizzle, half_1, false)); emit_mir_instruction(ctx, ins); } } else { @@ -1091,13 +1204,13 @@ emit_varying_read( compiler_context *ctx, unsigned dest, unsigned offset, unsigned nr_comp, unsigned component, - nir_src *indirect_offset) + nir_src *indirect_offset, nir_alu_type type) { /* XXX: Half-floats? */ /* TODO: swizzle, mask */ midgard_instruction ins = m_ld_vary_32(dest, offset); - ins.load_store.mask = mask_of(nr_comp); + ins.mask = mask_of(nr_comp); ins.load_store.swizzle = SWIZZLE_XYZW >> (2 * component); midgard_varying_parameter p = { @@ -1119,6 +1232,23 @@ emit_varying_read( ins.load_store.unknown = 0x1e9e; /* xxx: what is this? */ } + /* Use the type appropriate load */ + switch (type) { + case nir_type_uint: + case nir_type_bool: + ins.load_store.op = midgard_op_ld_vary_32u; + break; + case nir_type_int: + ins.load_store.op = midgard_op_ld_vary_32i; + break; + case nir_type_float: + ins.load_store.op = midgard_op_ld_vary_32; + break; + default: + unreachable("Attempted to load unknown type"); + break; + } + emit_mir_instruction(ctx, ins); } @@ -1137,79 +1267,6 @@ emit_sysval_read(compiler_context *ctx, nir_instr *instr) emit_ubo_read(ctx, dest, uniform, NULL, 0); } -/* Reads RGBA8888 value from the tilebuffer and converts to a RGBA32F register, - * using scalar ops functional on earlier Midgard generations. Newer Midgard - * generations have faster vectorized reads. This operation is for blend - * shaders in particular; reading the tilebuffer from the fragment shader - * remains an open problem. */ - -static void -emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg) -{ - midgard_instruction ins = m_ld_color_buffer_8(reg, 0); - ins.load_store.swizzle = 0; /* xxxx */ - - /* Read each component sequentially */ - - for (unsigned c = 0; c < 4; ++c) { - ins.load_store.mask = (1 << c); - ins.load_store.unknown = c; - emit_mir_instruction(ctx, ins); - } - - /* vadd.u2f hr2, zext(hr2), #0 */ - - midgard_vector_alu_src alu_src = blank_alu_src; - alu_src.mod = midgard_int_zero_extend; - alu_src.half = true; - - midgard_instruction u2f = { - .type = TAG_ALU_4, - .ssa_args = { - .src0 = reg, - .src1 = SSA_UNUSED_0, - .dest = reg, - .inline_constant = true - }, - .alu = { - .op = midgard_alu_op_u2f_rtz, - .reg_mode = midgard_reg_mode_16, - .dest_override = midgard_dest_override_none, - .mask = 0xF, - .src1 = vector_alu_srco_unsigned(alu_src), - .src2 = vector_alu_srco_unsigned(blank_alu_src), - } - }; - - emit_mir_instruction(ctx, u2f); - - /* vmul.fmul.sat r1, hr2, #0.00392151 */ - - alu_src.mod = 0; - - midgard_instruction fmul = { - .type = TAG_ALU_4, - .inline_constant = _mesa_float_to_half(1.0 / 255.0), - .ssa_args = { - .src0 = reg, - .dest = reg, - .src1 = SSA_UNUSED_0, - .inline_constant = true - }, - .alu = { - .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_32, - .dest_override = midgard_dest_override_none, - .outmod = midgard_outmod_sat, - .mask = 0xFF, - .src1 = vector_alu_srco_unsigned(alu_src), - .src2 = vector_alu_srco_unsigned(blank_alu_src), - } - }; - - emit_mir_instruction(ctx, fmul); -} - static void emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) { @@ -1238,7 +1295,9 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) bool is_ubo = instr->intrinsic == nir_intrinsic_load_ubo; /* Get the base type of the intrinsic */ - nir_alu_type t = nir_intrinsic_type(instr); + /* TODO: Infer type? Does it matter? */ + nir_alu_type t = + is_ubo ? nir_type_uint : nir_intrinsic_type(instr); t = nir_alu_type_get_base_type(t); if (!is_ubo) { @@ -1280,7 +1339,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) uint32_t uindex = nir_src_as_uint(index) + 1; emit_ubo_read(ctx, reg, offset / 16, NULL, uindex); } else if (ctx->stage == MESA_SHADER_FRAGMENT && !ctx->is_blend) { - emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL); + emit_varying_read(ctx, reg, offset, nr_comp, component, !direct ? &instr->src[0] : NULL, t); } else if (ctx->is_blend) { /* For blend shaders, load the input color, which is * preloaded to r0 */ @@ -1290,13 +1349,15 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) } else if (ctx->stage == MESA_SHADER_VERTEX) { midgard_instruction ins = m_ld_attr_32(reg, offset); ins.load_store.unknown = 0x1E1E; /* XXX: What is this? */ - ins.load_store.mask = mask_of(nr_comp); + ins.mask = mask_of(nr_comp); /* Use the type appropriate load */ switch (t) { - case nir_type_int: case nir_type_uint: case nir_type_bool: + ins.load_store.op = midgard_op_ld_attr_32u; + break; + case nir_type_int: ins.load_store.op = midgard_op_ld_attr_32i; break; case nir_type_float: @@ -1316,18 +1377,14 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) break; } - case nir_intrinsic_load_output: - assert(nir_src_is_const(instr->src[0])); - reg = nir_dest_index(ctx, &instr->dest); + /* Reads 128-bit value raw off the tilebuffer during blending, tasty */ - if (ctx->is_blend) { - /* TODO: MRT */ - emit_fb_read_blend_scalar(ctx, reg); - } else { - DBG("Unknown output load\n"); - assert(0); - } + case nir_intrinsic_load_raw_output_pan: + reg = nir_dest_index(ctx, &instr->dest); + assert(ctx->is_blend); + midgard_instruction ins = m_ld_color_buffer_8(reg, 0); + emit_mir_instruction(ctx, ins); break; case nir_intrinsic_load_blend_const_color_rgba: { @@ -1395,6 +1452,17 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) break; + /* Special case of store_output for lowered blend shaders */ + case nir_intrinsic_store_raw_output_pan: + assert (ctx->stage == MESA_SHADER_FRAGMENT); + reg = nir_src_index(ctx, &instr->src[0]); + + midgard_instruction move = v_mov(reg, blank_alu_src, SSA_FIXED_REGISTER(0)); + emit_mir_instruction(ctx, move); + ctx->fragment_output = reg; + + break; + case nir_intrinsic_load_alpha_ref_float: assert(instr->dest.is_ssa); @@ -1513,6 +1581,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, /* No helper to build texture words -- we do it all here */ midgard_instruction ins = { .type = TAG_TEXTURE_4, + .mask = 0xF, .texture = { .op = midgard_texop, .format = midgard_tex_format(instr->sampler_dim), @@ -1521,7 +1590,6 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, /* TODO: Regalloc it in */ .swizzle = SWIZZLE_XYZW, - .mask = 0xF, /* TODO: half */ .in_reg_full = 1, @@ -1555,7 +1623,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, midgard_instruction st = m_st_cubemap_coords(reg, 0); st.load_store.unknown = 0x24; /* XXX: What is this? */ - st.load_store.mask = 0x3; /* xy */ + st.mask = 0x3; /* xy */ st.load_store.swizzle = alu_src.swizzle; emit_mir_instruction(ctx, st); @@ -1564,7 +1632,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, ins.texture.in_reg_swizzle = alu_src.swizzle = swizzle_of(nr_comp); midgard_instruction mov = v_mov(index, alu_src, reg); - mov.alu.mask = expand_writemask(mask_of(nr_comp)); + mov.mask = mask_of(nr_comp); emit_mir_instruction(ctx, mov); if (midgard_texop == TEXTURE_OP_TEXEL_FETCH) { @@ -1581,7 +1649,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, zero.ssa_args.inline_constant = true; zero.ssa_args.src1 = SSA_FIXED_REGISTER(REGISTER_CONSTANT); zero.has_constants = true; - zero.alu.mask = ~mov.alu.mask; + zero.mask = ~mov.mask; emit_mir_instruction(ctx, zero); ins.texture.in_reg_swizzle = SWIZZLE_XYZZ; @@ -1612,7 +1680,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, alu_src.swizzle = SWIZZLE_XXXX; midgard_instruction mov = v_mov(index, alu_src, reg); - mov.alu.mask = expand_writemask(1 << COMPONENT_W); + mov.mask = 1 << COMPONENT_W; emit_mir_instruction(ctx, mov); ins.texture.lod_register = true; @@ -1644,12 +1712,7 @@ emit_texop_native(compiler_context *ctx, nir_tex_instr *instr, emit_mir_instruction(ctx, ins); - /* Simultaneously alias the destination and emit a move for it. The move will be eliminated if possible */ - int o_reg = REGISTER_TEXTURE_BASE + out_reg, o_index = nir_dest_index(ctx, &instr->dest); - alias_ssa(ctx, o_index, SSA_FIXED_REGISTER(o_reg)); - ctx->texture_index[reg] = o_index; - midgard_instruction ins2 = v_mov(SSA_FIXED_REGISTER(o_reg), blank_alu_src, o_index); emit_mir_instruction(ctx, ins2); @@ -1819,6 +1882,13 @@ embedded_to_inline_constant(compiler_context *ctx) /* Blend constants must not be inlined by definition */ if (ins->has_blend_constant) continue; + /* We can inline 32-bit (sometimes) or 16-bit (usually) */ + bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16; + bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32; + + if (!(is_16 || is_32)) + continue; + /* src1 cannot be an inline constant due to encoding * restrictions. So, if possible we try to flip the arguments * in that case */ @@ -1869,7 +1939,7 @@ embedded_to_inline_constant(compiler_context *ctx) /* Scale constant appropriately, if we can legally */ uint16_t scaled_constant = 0; - if (midgard_is_integer_op(op)) { + if (midgard_is_integer_op(op) || is_16) { unsigned int *iconstants = (unsigned int *) ins->constants; scaled_constant = (uint16_t) iconstants[component]; @@ -1908,7 +1978,7 @@ embedded_to_inline_constant(compiler_context *ctx) uint32_t value = cons[component]; bool is_vector = false; - unsigned mask = effective_writemask(&ins->alu); + unsigned mask = effective_writemask(&ins->alu, ins->mask); for (int c = 1; c < 4; ++c) { /* We only care if this component is actually used */ @@ -2018,6 +2088,12 @@ mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask) /* abs or neg */ if (!is_int && src.mod) return true; + /* Other int mods don't matter in isolation */ + if (is_int && src.mod == midgard_int_shift) return true; + + /* size-conversion */ + if (src.half) return true; + /* swizzle */ for (unsigned c = 0; c < 4; ++c) { if (!(mask & (1 << c))) continue; @@ -2030,13 +2106,12 @@ mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask) static bool mir_nontrivial_source2_mod(midgard_instruction *ins) { - unsigned mask = squeeze_writemask(ins->alu.mask); bool is_int = midgard_is_integer_op(ins->alu.op); midgard_vector_alu_src src2 = vector_alu_from_unsigned(ins->alu.src2); - return mir_nontrivial_mod(src2, is_int, mask); + return mir_nontrivial_mod(src2, is_int, ins->mask); } static bool @@ -2045,6 +2120,10 @@ mir_nontrivial_outmod(midgard_instruction *ins) bool is_int = midgard_is_integer_op(ins->alu.op); unsigned mod = ins->alu.outmod; + /* Type conversion is a sort of outmod */ + if (ins->alu.dest_override != midgard_dest_override_none) + return true; + if (is_int) return mod != midgard_outmod_int_wrap; else @@ -2148,55 +2227,6 @@ midgard_opt_pos_propagate(compiler_context *ctx, midgard_block *block) return progress; } -static bool -midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block) -{ - bool progress = false; - - mir_foreach_instr_in_block_safe(block, ins) { - if (ins->type != TAG_ALU_4) continue; - if (!OP_IS_MOVE(ins->alu.op)) continue; - - unsigned from = ins->ssa_args.src1; - unsigned to = ins->ssa_args.dest; - - /* Make sure it's simple enough for us to handle */ - - if (from >= SSA_FIXED_MINIMUM) continue; - if (from >= ctx->func->impl->ssa_alloc) continue; - if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue; - if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue; - - bool eliminated = false; - - mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) { - /* The texture registers are not SSA so be careful. - * Conservatively, just stop if we hit a texture op - * (even if it may not write) to where we are */ - - if (v->type != TAG_ALU_4) - break; - - if (v->ssa_args.dest == from) { - /* We don't want to track partial writes ... */ - if (v->alu.mask == 0xF) { - v->ssa_args.dest = to; - eliminated = true; - } - - break; - } - } - - if (eliminated) - mir_remove_instruction(ins); - - progress |= eliminated; - } - - return progress; -} - /* The following passes reorder MIR instructions to enable better scheduling */ static void @@ -2296,67 +2326,6 @@ emit_fragment_epilogue(compiler_context *ctx) EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always); } -/* For the blend epilogue, we need to convert the blended fragment vec4 (stored - * in r0) to a RGBA8888 value by scaling and type converting. We then output it - * with the int8 analogue to the fragment epilogue */ - -static void -emit_blend_epilogue(compiler_context *ctx) -{ - /* vmul.fmul.none.fulllow hr48, r0, #255 */ - - midgard_instruction scale = { - .type = TAG_ALU_4, - .unit = UNIT_VMUL, - .inline_constant = _mesa_float_to_half(255.0), - .ssa_args = { - .src0 = SSA_FIXED_REGISTER(0), - .src1 = SSA_UNUSED_0, - .dest = SSA_FIXED_REGISTER(24), - .inline_constant = true - }, - .alu = { - .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_32, - .dest_override = midgard_dest_override_lower, - .mask = 0xFF, - .src1 = vector_alu_srco_unsigned(blank_alu_src), - .src2 = vector_alu_srco_unsigned(blank_alu_src), - } - }; - - emit_mir_instruction(ctx, scale); - - /* vadd.f2u_rte.pos.low hr0, hr48, #0 */ - - midgard_vector_alu_src alu_src = blank_alu_src; - alu_src.half = true; - - midgard_instruction f2u_rte = { - .type = TAG_ALU_4, - .ssa_args = { - .src0 = SSA_FIXED_REGISTER(24), - .src1 = SSA_UNUSED_0, - .dest = SSA_FIXED_REGISTER(0), - .inline_constant = true - }, - .alu = { - .op = midgard_alu_op_f2u_rte, - .reg_mode = midgard_reg_mode_16, - .dest_override = midgard_dest_override_lower, - .outmod = midgard_outmod_pos, - .mask = 0xF, - .src1 = vector_alu_srco_unsigned(alu_src), - .src2 = vector_alu_srco_unsigned(blank_alu_src), - } - }; - - emit_mir_instruction(ctx, f2u_rte); - - EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 0, midgard_condition_always); - EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, -1, midgard_condition_always); -} - static midgard_block * emit_block(compiler_context *ctx, nir_block *block) { @@ -2393,10 +2362,7 @@ emit_block(compiler_context *ctx, nir_block *block) /* Append fragment shader epilogue (value writeout) */ if (ctx->stage == MESA_SHADER_FRAGMENT) { if (block == nir_impl_last_block(ctx->func->impl)) { - if (ctx->is_blend) - emit_blend_epilogue(ctx); - else - emit_fragment_epilogue(ctx); + emit_fragment_epilogue(ctx); } } @@ -2513,6 +2479,9 @@ emit_loop(struct compiler_context *ctx, nir_loop *nloop) /* Now that we've finished emitting the loop, free up the depth again * so we play nice with recursion amid nested loops */ --ctx->current_loop_depth; + + /* Dump loop stats */ + ++ctx->loop_count; } static midgard_block * @@ -2587,7 +2556,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl .stage = nir->info.stage, .is_blend = is_blend, - .blend_constant_offset = -1, + .blend_constant_offset = 0, .alpha_ref = program->alpha_ref }; @@ -2686,7 +2655,6 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl mir_foreach_block(ctx, block) { progress |= midgard_opt_pos_propagate(ctx, block); progress |= midgard_opt_copy_prop(ctx, block); - progress |= midgard_opt_copy_prop_tex(ctx, block); progress |= midgard_opt_dead_code_eliminate(ctx, block); } } while (progress); @@ -2890,5 +2858,42 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl if (midgard_debug & MIDGARD_DBG_SHADERS) disassemble_midgard(program->compiled.data, program->compiled.size); + if (midgard_debug & MIDGARD_DBG_SHADERDB) { + unsigned nr_bundles = 0, nr_ins = 0; + + /* Count instructions and bundles */ + + mir_foreach_instr_global(ctx, ins) { + nr_ins++; + } + + mir_foreach_block(ctx, block) { + nr_bundles += util_dynarray_num_elements( + &block->bundles, midgard_bundle); + } + + /* Calculate thread count. There are certain cutoffs by + * register count for thread count */ + + unsigned nr_registers = program->work_register_count; + + unsigned nr_threads = + (nr_registers <= 4) ? 4 : + (nr_registers <= 8) ? 2 : + 1; + + /* Dump stats */ + + fprintf(stderr, "shader%d - %s shader: " + "%u inst, %u bundles, " + "%u registers, %u threads, %u loops\n", + SHADER_DB_COUNT++, + gl_shader_stage_name(ctx->stage), + nr_ins, nr_bundles, + nr_registers, nr_threads, + ctx->loop_count); + } + + return 0; }