X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fmidgard%2Fmidgard_compile.c;h=9c7928decf67bd1c7b6f1a667d8e99eb5587a93f;hb=d41cdef2a591930ad848b27f936aafcafc93b308;hp=5b5a44013a2c78ee504e1b52313e8090514d24ea;hpb=b53b4573c3f0571253672e44ce7d6310d9f987bf;p=mesa.git diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c b/src/gallium/drivers/panfrost/midgard/midgard_compile.c index 5b5a44013a2..9c7928decf6 100644 --- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c +++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c @@ -316,7 +316,7 @@ v_fmov(unsigned src, midgard_vector_alu_src mod, unsigned dest) }, .alu = { .op = midgard_alu_op_fmov, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(zero_alu_src), @@ -715,6 +715,58 @@ midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr *alu) nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(sum)); } +/* Lower csel with mixed condition channels to mulitple csel instructions. For + * context, the csel ops on Midgard are vector in *outputs*, but not in + * *conditions*. So, if the condition is e.g. yyyy, a single op can select a + * vec4. But if the condition is e.g. xyzw, four ops are needed as the ISA + * can't cope with the divergent channels.*/ + +static void +midgard_nir_lower_mixed_csel_body(nir_builder *b, nir_alu_instr *alu) +{ + if (alu->op != nir_op_bcsel) + return; + + b->cursor = nir_before_instr(&alu->instr); + + /* Must be run before registering */ + assert(alu->dest.dest.is_ssa); + + /* Check for mixed condition */ + + unsigned comp = alu->src[0].swizzle[0]; + unsigned nr_components = alu->dest.dest.ssa.num_components; + + bool mixed = false; + + for (unsigned c = 1; c < nr_components; ++c) + mixed |= (alu->src[0].swizzle[c] != comp); + + if (!mixed) + return; + + /* We're mixed, so lower */ + + assert(nr_components <= 4); + nir_ssa_def *results[4]; + + nir_ssa_def *cond = nir_ssa_for_alu_src(b, alu, 0); + nir_ssa_def *choice0 = nir_ssa_for_alu_src(b, alu, 1); + nir_ssa_def *choice1 = nir_ssa_for_alu_src(b, alu, 2); + + for (unsigned c = 0; c < nr_components; ++c) { + results[c] = nir_bcsel(b, + nir_channel(b, cond, c), + nir_channel(b, choice0, c), + nir_channel(b, choice1, c)); + } + + /* Replace with our scalarized version */ + + nir_ssa_def *result = nir_vec(b, results, nr_components); + nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(result)); +} + static int midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr) { @@ -799,13 +851,48 @@ midgard_nir_lower_fdot2(nir_shader *shader) return progress; } +static bool +midgard_nir_lower_mixed_csel(nir_shader *shader) +{ + bool progress = false; + + nir_foreach_function(function, shader) { + if (!function->impl) continue; + + nir_builder _b; + nir_builder *b = &_b; + nir_builder_init(b, function->impl); + + nir_foreach_block(block, function->impl) { + nir_foreach_instr_safe(instr, block) { + if (instr->type != nir_instr_type_alu) continue; + + nir_alu_instr *alu = nir_instr_as_alu(instr); + midgard_nir_lower_mixed_csel_body(b, alu); + + progress |= true; + } + } + + nir_metadata_preserve(function->impl, nir_metadata_block_index | nir_metadata_dominance); + + } + + return progress; +} + static void optimise_nir(nir_shader *nir) { bool progress; + unsigned lower_flrp = + (nir->options->lower_flrp16 ? 16 : 0) | + (nir->options->lower_flrp32 ? 32 : 0) | + (nir->options->lower_flrp64 ? 64 : 0); NIR_PASS(progress, nir, nir_lower_regs_to_ssa); NIR_PASS(progress, nir, midgard_nir_lower_fdot2); + NIR_PASS(progress, nir, midgard_nir_lower_mixed_csel); nir_lower_tex_options lower_tex_options = { .lower_rect = true @@ -826,6 +913,27 @@ optimise_nir(nir_shader *nir) NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true); NIR_PASS(progress, nir, nir_opt_algebraic); NIR_PASS(progress, nir, nir_opt_constant_folding); + + if (lower_flrp != 0) { + bool lower_flrp_progress; + NIR_PASS(lower_flrp_progress, + nir, + nir_lower_flrp, + lower_flrp, + false /* always_precise */, + nir->options->lower_ffma); + if (lower_flrp_progress) { + NIR_PASS(progress, nir, + nir_opt_constant_folding); + progress = true; + } + + /* Nothing should rematerialize any flrps, so we only + * need to do this lowering once. + */ + lower_flrp = 0; + } + NIR_PASS(progress, nir, nir_opt_undef); NIR_PASS(progress, nir, nir_opt_loop_unroll, nir_var_shader_in | @@ -1038,7 +1146,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool for_branch, unsigned co }, .alu = { .op = midgard_alu_op_iand, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(alu_src), @@ -1066,7 +1174,7 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src) }, .alu = { .op = midgard_alu_op_imov, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .mask = (0x3 << 6), /* w */ .src1 = vector_alu_srco_unsigned(zero_alu_src), @@ -1134,9 +1242,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) ALU_CASE(isub, isub); ALU_CASE(imul, imul); ALU_CASE(iabs, iabs); - - /* XXX: Use fmov, not imov, since imov was causing major - * issues with texture precision? XXX research */ ALU_CASE(imov, imov); ALU_CASE(feq32, feq); @@ -1184,7 +1289,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) ALU_CASE(iand, iand); ALU_CASE(ior, ior); ALU_CASE(ixor, ixor); - ALU_CASE(inot, inot); + ALU_CASE(inot, inand); ALU_CASE(ishl, ishl); ALU_CASE(ishr, iasr); ALU_CASE(ushr, ilsr); @@ -1227,29 +1332,53 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) break; } + /* For a few special csel cases not handled by NIR, we can opt to + * bitwise. Otherwise, we emit the condition and do a real csel */ + case nir_op_b32csel: { - op = midgard_alu_op_fcsel; + if (nir_is_fzero_constant(instr->src[2].src)) { + /* (b ? v : 0) = (b & v) */ + op = midgard_alu_op_iand; + nr_inputs = 2; + } else if (nir_is_fzero_constant(instr->src[1].src)) { + /* (b ? 0 : v) = (!b ? v : 0) = (~b & v) = (v & ~b) */ + op = midgard_alu_op_iandnot; + nr_inputs = 2; + instr->src[1] = instr->src[0]; + instr->src[0] = instr->src[2]; + } else { + /* Midgard features both fcsel and icsel, depending on + * the type of the arguments/output. However, as long + * as we're careful we can _always_ use icsel and + * _never_ need fcsel, since the latter does additional + * floating-point-specific processing whereas the + * former just moves bits on the wire. It's not obvious + * why these are separate opcodes, save for the ability + * to do things like sat/pos/abs/neg for free */ + + op = midgard_alu_op_icsel; - /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */ - nr_inputs = 2; + /* csel works as a two-arg in Midgard, since the condition is hardcoded in r31.w */ + nr_inputs = 2; - /* Figure out which component the condition is in */ + /* Figure out which component the condition is in */ - unsigned comp = instr->src[0].swizzle[0]; + unsigned comp = instr->src[0].swizzle[0]; - /* Make sure NIR isn't throwing a mixed condition at us */ + /* Make sure NIR isn't throwing a mixed condition at us */ - for (unsigned c = 1; c < nr_components; ++c) - assert(instr->src[0].swizzle[c] == comp); + for (unsigned c = 1; c < nr_components; ++c) + assert(instr->src[0].swizzle[c] == comp); - /* Emit the condition into r31.w */ - emit_condition(ctx, &instr->src[0].src, false, comp); + /* Emit the condition into r31.w */ + emit_condition(ctx, &instr->src[0].src, false, comp); - /* The condition is the first argument; move the other - * arguments up one to be a binary instruction for - * Midgard */ + /* The condition is the first argument; move the other + * arguments up one to be a binary instruction for + * Midgard */ - memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src)); + memmove(instr->src, instr->src + 1, 2 * sizeof(nir_alu_src)); + } break; } @@ -1316,7 +1445,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) midgard_vector_alu alu = { .op = op, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .outmod = outmod, @@ -1361,6 +1490,10 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr) ins.has_constants = true; ins.constants[0] = 0.0f; ins.alu.src2 = vector_alu_srco_unsigned(blank_alu_src_xxxx); + } else if (instr->op == nir_op_inot) { + /* ~b = ~(b & b), so duplicate the source */ + ins.ssa_args.src1 = ins.ssa_args.src0; + ins.alu.src2 = ins.alu.src1; } if ((opcode_props & UNITS_ALL) == UNIT_VLUT) { @@ -1560,7 +1693,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) }, .alu = { .op = midgard_alu_op_u2f, - .reg_mode = midgard_reg_mode_half, + .reg_mode = midgard_reg_mode_16, .dest_override = midgard_dest_override_none, .mask = 0xF, .src1 = vector_alu_srco_unsigned(alu_src), @@ -1585,7 +1718,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr) }, .alu = { .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_none, .outmod = midgard_outmod_sat, .mask = 0xFF, @@ -1773,8 +1906,6 @@ emit_tex(compiler_context *ctx, nir_tex_instr *instr) emit_mir_instruction(ctx, ins); } - //midgard_pin_output(ctx, index, REGISTER_TEXTURE_BASE + in_reg); - break; } @@ -1908,6 +2039,7 @@ dealias_register(compiler_context *ctx, struct ra_graph *g, int reg, int maxreg) if (reg >= 0) { assert(reg < maxreg); + assert(g); int r = ra_get_node_reg(g, reg); ctx->work_registers = MAX2(ctx->work_registers, r); return r; @@ -2007,7 +2139,68 @@ is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction * return succ; } +/* Once registers have been decided via register allocation + * (allocate_registers), we need to rewrite the MIR to use registers instead of + * SSA */ + static void +install_registers(compiler_context *ctx, struct ra_graph *g) +{ + mir_foreach_block(ctx, block) { + mir_foreach_instr_in_block(block, ins) { + if (ins->compact_branch) continue; + + ssa_args args = ins->ssa_args; + + switch (ins->type) { + case TAG_ALU_4: + ins->registers.src1_reg = dealias_register(ctx, g, args.src0, ctx->temp_count); + + ins->registers.src2_imm = args.inline_constant; + + if (args.inline_constant) { + /* Encode inline 16-bit constant as a vector by default */ + + ins->registers.src2_reg = ins->inline_constant >> 11; + + int lower_11 = ins->inline_constant & ((1 << 12) - 1); + + uint16_t imm = ((lower_11 >> 8) & 0x7) | ((lower_11 & 0xFF) << 3); + ins->alu.src2 = imm << 2; + } else { + ins->registers.src2_reg = dealias_register(ctx, g, args.src1, ctx->temp_count); + } + + ins->registers.out_reg = dealias_register(ctx, g, args.dest, ctx->temp_count); + + break; + + case TAG_LOAD_STORE_4: { + if (OP_IS_STORE_VARY(ins->load_store.op)) { + /* TODO: use ssa_args for store_vary */ + ins->load_store.reg = 0; + } else { + bool has_dest = args.dest >= 0; + int ssa_arg = has_dest ? args.dest : args.src0; + + ins->load_store.reg = dealias_register(ctx, g, ssa_arg, ctx->temp_count); + } + + break; + } + + default: + break; + } + } + } + +} + +/* This routine performs the actual register allocation. It should be succeeded + * by install_registers */ + +static struct ra_graph * allocate_registers(compiler_context *ctx) { /* First, initialize the RA */ @@ -2044,6 +2237,11 @@ allocate_registers(compiler_context *ctx) print_mir_block(block); } + /* No register allocation to do with no SSA */ + + if (!ctx->temp_count) + return NULL; + /* Let's actually do register allocation */ int nodes = ctx->temp_count; struct ra_graph *g = ra_alloc_interference_graph(regs, nodes); @@ -2092,6 +2290,13 @@ allocate_registers(compiler_context *ctx) mir_foreach_instr_in_block(block, ins) { if (ins->compact_branch) continue; + /* Dest is < 0 for store_vary instructions, which break + * the usual SSA conventions. Liveness analysis doesn't + * make sense on these instructions, so skip them to + * avoid memory corruption */ + + if (ins->ssa_args.dest < 0) continue; + if (ins->ssa_args.dest < SSA_FIXED_MINIMUM) { /* If this destination is not yet live, it is now since we just wrote it */ @@ -2153,54 +2358,7 @@ allocate_registers(compiler_context *ctx) free(live_start); free(live_end); - mir_foreach_block(ctx, block) { - mir_foreach_instr_in_block(block, ins) { - if (ins->compact_branch) continue; - - ssa_args args = ins->ssa_args; - - switch (ins->type) { - case TAG_ALU_4: - ins->registers.src1_reg = dealias_register(ctx, g, args.src0, nodes); - - ins->registers.src2_imm = args.inline_constant; - - if (args.inline_constant) { - /* Encode inline 16-bit constant as a vector by default */ - - ins->registers.src2_reg = ins->inline_constant >> 11; - - int lower_11 = ins->inline_constant & ((1 << 12) - 1); - - uint16_t imm = ((lower_11 >> 8) & 0x7) | ((lower_11 & 0xFF) << 3); - ins->alu.src2 = imm << 2; - } else { - ins->registers.src2_reg = dealias_register(ctx, g, args.src1, nodes); - } - - ins->registers.out_reg = dealias_register(ctx, g, args.dest, nodes); - - break; - - case TAG_LOAD_STORE_4: { - if (OP_IS_STORE_VARY(ins->load_store.op)) { - /* TODO: use ssa_args for store_vary */ - ins->load_store.reg = 0; - } else { - bool has_dest = args.dest >= 0; - int ssa_arg = has_dest ? args.dest : args.src0; - - ins->load_store.reg = dealias_register(ctx, g, ssa_arg, nodes); - } - - break; - } - - default: - break; - } - } - } + return g; } /* Midgard IR only knows vector ALU types, but we sometimes need to actually @@ -2780,7 +2938,9 @@ schedule_block(compiler_context *ctx, midgard_block *block) static void schedule_program(compiler_context *ctx) { - allocate_registers(ctx); + /* We run RA prior to scheduling */ + struct ra_graph *g = allocate_registers(ctx); + install_registers(ctx, g); mir_foreach_block(ctx, block) { schedule_block(ctx, block); @@ -3033,7 +3193,20 @@ embedded_to_inline_constant(compiler_context *ctx) if (scaled_constant != iconstants[component]) continue; } else { - scaled_constant = _mesa_float_to_half((float) ins->constants[component]); + float original = (float) ins->constants[component]; + scaled_constant = _mesa_float_to_half(original); + + /* Check for loss of precision. If this is + * mediump, we don't care, but for a highp + * shader, we need to pay attention. NIR + * doesn't yet tell us which mode we're in! + * Practically this prevents most constants + * from being inlined, sadly. */ + + float fp32 = _mesa_half_to_float(scaled_constant); + + if (fp32 != original) + continue; } /* We don't know how to handle these with a constant */ @@ -3123,36 +3296,6 @@ midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block) return progress; } -/* Combines the two outmods if possible. Returns whether the combination was - * successful */ - -static bool -midgard_combine_outmod(midgard_outmod *main, midgard_outmod overlay) -{ - if (overlay == midgard_outmod_none) - return true; - - if (*main == overlay) - return true; - - if (*main == midgard_outmod_none) { - *main = overlay; - return true; - } - - if (*main == midgard_outmod_pos && overlay == midgard_outmod_sat) { - *main = midgard_outmod_sat; - return true; - } - - if (overlay == midgard_outmod_pos && *main == midgard_outmod_sat) { - *main = midgard_outmod_sat; - return true; - } - - return false; -} - static bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block) { @@ -3172,9 +3315,7 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block) if (to >= ctx->func->impl->ssa_alloc) continue; if (from >= ctx->func->impl->ssa_alloc) continue; - /* Also, if the move has source side effects, we're not sure - * what to do. Destination side effects we can handle, though. - */ + /* Also, if the move has side effects, we're helpless */ midgard_vector_alu_src src = vector_alu_from_unsigned(ins->alu.src2); @@ -3182,29 +3323,98 @@ midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block) bool is_int = midgard_is_integer_op(ins->alu.op); if (mir_nontrivial_mod(src, is_int, mask)) continue; + if (ins->alu.outmod != midgard_outmod_none) continue; + + mir_foreach_instr_in_block_from(block, v, mir_next_op(ins)) { + if (v->ssa_args.src0 == to) { + v->ssa_args.src0 = from; + progress = true; + } + + if (v->ssa_args.src1 == to && !v->ssa_args.inline_constant) { + v->ssa_args.src1 = from; + progress = true; + } + } + } + + return progress; +} + +static bool +midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block) +{ + bool progress = false; + + mir_foreach_instr_in_block_safe(block, ins) { + if (ins->type != TAG_ALU_4) continue; + if (!OP_IS_MOVE(ins->alu.op)) continue; + + unsigned from = ins->ssa_args.src1; + unsigned to = ins->ssa_args.dest; + + /* Make sure it's simple enough for us to handle */ + + if (from >= SSA_FIXED_MINIMUM) continue; + if (from >= ctx->func->impl->ssa_alloc) continue; + if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue; + if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) continue; + + bool eliminated = false; mir_foreach_instr_in_block_from_rev(block, v, mir_prev_op(ins)) { - if (v->ssa_args.dest == from) { - if (v->type == TAG_ALU_4) { - midgard_outmod final = v->alu.outmod; + /* The texture registers are not SSA so be careful. + * Conservatively, just stop if we hit a texture op + * (even if it may not write) to where we are */ - if (!midgard_combine_outmod(&final, ins->alu.outmod)) - continue; + if (v->type != TAG_ALU_4) + break; - v->alu.outmod = final; + if (v->ssa_args.dest == from) { + /* We don't want to track partial writes ... */ + if (v->alu.mask == 0xF) { + v->ssa_args.dest = to; + eliminated = true; } - v->ssa_args.dest = to; - progress = true; + break; } } - mir_remove_instruction(ins); + if (eliminated) + mir_remove_instruction(ins); + + progress |= eliminated; } return progress; } +/* We don't really understand the imov/fmov split, so always use fmov (but let + * it be imov in the IR so we don't do unsafe floating point "optimizations" + * and break things */ + +static void +midgard_imov_workaround(compiler_context *ctx, midgard_block *block) +{ + mir_foreach_instr_in_block_safe(block, ins) { + if (ins->type != TAG_ALU_4) continue; + if (ins->alu.op != midgard_alu_op_imov) continue; + + ins->alu.op = midgard_alu_op_fmov; + ins->alu.outmod = midgard_outmod_none; + + /* Remove flags that don't make sense */ + + midgard_vector_alu_src s = + vector_alu_from_unsigned(ins->alu.src2); + + s.mod = 0; + + ins->alu.src2 = vector_alu_srco_unsigned(s); + } +} + /* The following passes reorder MIR instructions to enable better scheduling */ static void @@ -3359,7 +3569,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_fmul, - .reg_mode = midgard_reg_mode_full, + .reg_mode = midgard_reg_mode_32, .dest_override = midgard_dest_override_lower, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(blank_alu_src), @@ -3384,7 +3594,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_f2u8, - .reg_mode = midgard_reg_mode_half, + .reg_mode = midgard_reg_mode_16, .dest_override = midgard_dest_override_lower, .outmod = midgard_outmod_pos, .mask = 0xF, @@ -3406,7 +3616,7 @@ emit_blend_epilogue(compiler_context *ctx) }, .alu = { .op = midgard_alu_op_imov, - .reg_mode = midgard_reg_mode_quarter, + .reg_mode = midgard_reg_mode_8, .dest_override = midgard_dest_override_none, .mask = 0xFF, .src1 = vector_alu_srco_unsigned(blank_alu_src), @@ -3456,6 +3666,7 @@ emit_block(compiler_context *ctx, nir_block *block) midgard_emit_store(ctx, this_block); midgard_pair_load_store(ctx, this_block); + midgard_imov_workaround(ctx, this_block); /* Append fragment shader epilogue (value writeout) */ if (ctx->stage == MESA_SHADER_FRAGMENT) { @@ -3754,6 +3965,7 @@ midgard_compile_shader_nir(nir_shader *nir, midgard_program *program, bool is_bl mir_foreach_block(ctx, block) { progress |= midgard_opt_copy_prop(ctx, block); + progress |= midgard_opt_copy_prop_tex(ctx, block); progress |= midgard_opt_dead_code_eliminate(ctx, block); } } while (progress);