X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=9f5ad3a0599f8941c7c4735e62de0303e8d18d10;hb=90cc8156289e5b58934ec3c428d9a0471ce551fb;hp=d820f4c94517ee91b6406dc5d58cd2c6799e2d44;hpb=ec58cda5da0b7d43b5ff71db4f4f3b85629e6739;p=mesa.git diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index d820f4c9451..9f5ad3a0599 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -51,46 +51,26 @@ panfrost_bo_access_for_stage(enum pipe_shader_type stage) PAN_BO_ACCESS_VERTEX_TILER; } -static void -panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *postfix) +mali_ptr +panfrost_vt_emit_shared_memory(struct panfrost_batch *batch) { - struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); + struct panfrost_device *dev = pan_device(batch->ctx->base.screen); - unsigned shift = panfrost_get_stack_shift(batch->stack_size); struct mali_shared_memory shared = { - .stack_shift = shift, - .scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu, .shared_workgroup_count = ~0, }; - postfix->shared_memory = panfrost_pool_upload(&batch->pool, &shared, sizeof(shared)); -} -static void -panfrost_vt_attach_framebuffer(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch); -} + if (batch->stack_size) { + struct panfrost_bo *stack = + panfrost_batch_get_scratchpad(batch, batch->stack_size, + dev->thread_tls_alloc, + dev->core_count); -static void -panfrost_vt_update_rasterizer(struct panfrost_context *ctx, - struct mali_vertex_tiler_prefix *prefix, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_rasterizer *rasterizer = ctx->rasterizer; + shared.stack_shift = panfrost_get_stack_shift(batch->stack_size); + shared.scratchpad = stack->gpu; + } - postfix->gl_enables |= 0x7; - SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP, - rasterizer && rasterizer->base.front_ccw); - SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT)); - SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK)); - SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST, - rasterizer && rasterizer->base.flatshade_first); + return panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); } void @@ -101,11 +81,7 @@ panfrost_vt_update_primitive_size(struct panfrost_context *ctx, struct panfrost_rasterizer *rasterizer = ctx->rasterizer; if (!panfrost_writes_point_size(ctx)) { - bool points = prefix->draw_mode == MALI_DRAW_MODE_POINTS; - float val = 0.0f; - - if (rasterizer) - val = points ? + float val = (prefix->draw_mode == MALI_DRAW_MODE_POINTS) ? rasterizer->base.point_size : rasterizer->base.line_width; @@ -113,51 +89,7 @@ panfrost_vt_update_primitive_size(struct panfrost_context *ctx, } } -static void -panfrost_vt_update_occlusion_query(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *postfix) -{ - SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query); - if (ctx->occlusion_query) { - postfix->occlusion_counter = ctx->occlusion_query->bo->gpu; - panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo, - PAN_BO_ACCESS_SHARED | - PAN_BO_ACCESS_RW | - PAN_BO_ACCESS_FRAGMENT); - } else { - postfix->occlusion_counter = 0; - } -} - -void -panfrost_vt_init(struct panfrost_context *ctx, - enum pipe_shader_type stage, - struct mali_vertex_tiler_prefix *prefix, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_device *device = pan_device(ctx->base.screen); - - if (!ctx->shader[stage]) - return; - - memset(prefix, 0, sizeof(*prefix)); - memset(postfix, 0, sizeof(*postfix)); - - if (device->quirks & IS_BIFROST) { - postfix->gl_enables = 0x2; - panfrost_vt_emit_shared_memory(ctx, postfix); - } else { - postfix->gl_enables = 0x6; - panfrost_vt_attach_framebuffer(ctx, postfix); - } - - if (stage == PIPE_SHADER_FRAGMENT) { - panfrost_vt_update_occlusion_query(ctx, postfix); - panfrost_vt_update_rasterizer(ctx, prefix, postfix); - } -} - -static unsigned +unsigned panfrost_translate_index_size(unsigned size) { switch (size) { @@ -181,7 +113,7 @@ panfrost_translate_index_size(unsigned size) * these operations together because there are natural optimizations which * require them to be together. */ -static mali_ptr +mali_ptr panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, const struct pipe_draw_info *info, unsigned *min_index, unsigned *max_index) @@ -215,9 +147,13 @@ panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, } else { /* Otherwise, we need to upload to transient memory */ const uint8_t *ibuf8 = (const uint8_t *) info->index.user; - out = panfrost_pool_upload(&batch->pool, ibuf8 + offset, - info->count * - info->index_size); + struct panfrost_transfer T = + panfrost_pool_alloc_aligned(&batch->pool, + info->count * info->index_size, + info->index_size); + + memcpy(T.cpu, ibuf8 + offset, info->count * info->index_size); + out = T.gpu; } if (needs_indices) { @@ -233,122 +169,6 @@ panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, return out; } -void -panfrost_vt_set_draw_info(struct panfrost_context *ctx, - const struct pipe_draw_info *info, - enum mali_draw_mode draw_mode, - struct mali_vertex_tiler_postfix *vertex_postfix, - struct mali_vertex_tiler_prefix *tiler_prefix, - struct mali_vertex_tiler_postfix *tiler_postfix, - unsigned *vertex_count, - unsigned *padded_count) -{ - tiler_prefix->draw_mode = draw_mode; - - unsigned draw_flags = 0; - - if (panfrost_writes_point_size(ctx)) - draw_flags |= MALI_DRAW_VARYING_SIZE; - - if (info->primitive_restart) - draw_flags |= MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX; - - /* These doesn't make much sense */ - - draw_flags |= 0x3000; - - if (info->index_size) { - unsigned min_index = 0, max_index = 0; - - tiler_prefix->indices = panfrost_get_index_buffer_bounded(ctx, - info, - &min_index, - &max_index); - - /* Use the corresponding values */ - *vertex_count = max_index - min_index + 1; - tiler_postfix->offset_start = vertex_postfix->offset_start = min_index + info->index_bias; - tiler_prefix->offset_bias_correction = -min_index; - tiler_prefix->index_count = MALI_POSITIVE(info->count); - draw_flags |= panfrost_translate_index_size(info->index_size); - } else { - tiler_prefix->indices = 0; - *vertex_count = ctx->vertex_count; - tiler_postfix->offset_start = vertex_postfix->offset_start = info->start; - tiler_prefix->offset_bias_correction = 0; - tiler_prefix->index_count = MALI_POSITIVE(ctx->vertex_count); - } - - tiler_prefix->unknown_draw = draw_flags; - - /* Encode the padded vertex count */ - - if (info->instance_count > 1) { - *padded_count = panfrost_padded_vertex_count(*vertex_count); - - unsigned shift = __builtin_ctz(ctx->padded_count); - unsigned k = ctx->padded_count >> (shift + 1); - - tiler_postfix->instance_shift = vertex_postfix->instance_shift = shift; - tiler_postfix->instance_odd = vertex_postfix->instance_odd = k; - } else { - *padded_count = *vertex_count; - - /* Reset instancing state */ - tiler_postfix->instance_shift = vertex_postfix->instance_shift = 0; - tiler_postfix->instance_odd = vertex_postfix->instance_odd = 0; - } -} - -static void -panfrost_shader_meta_init(struct panfrost_context *ctx, - enum pipe_shader_type st, - struct mali_shader_meta *meta) -{ - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); - - memset(meta, 0, sizeof(*meta)); - meta->shader = (ss->bo ? ss->bo->gpu : 0) | ss->first_tag; - meta->attribute_count = ss->attribute_count; - meta->varying_count = ss->varying_count; - meta->texture_count = ctx->sampler_view_count[st]; - meta->sampler_count = ctx->sampler_count[st]; - - if (dev->quirks & IS_BIFROST) { - if (st == PIPE_SHADER_VERTEX) - meta->bifrost1.unk1 = 0x800000; - else { - /* First clause ATEST |= 0x4000000. - * Less than 32 regs |= 0x200 */ - meta->bifrost1.unk1 = 0x950020; - } - - meta->bifrost1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - if (st == PIPE_SHADER_VERTEX) - meta->bifrost2.preload_regs = 0xC0; - else { - meta->bifrost2.preload_regs = 0x1; - SET_BIT(meta->bifrost2.preload_regs, 0x10, ss->reads_frag_coord); - } - - meta->bifrost2.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - } else { - meta->midgard1.uniform_count = MIN2(ss->uniform_count, - ss->uniform_cutoff); - meta->midgard1.work_count = ss->work_reg_count; - - /* TODO: This is not conformant on ES3 */ - meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; - - meta->midgard1.flags_lo = 0x20; - meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); - - SET_BIT(meta->midgard1.flags_hi, MALI_WRITES_GLOBAL, ss->writes_global); - } -} - static unsigned translate_tex_wrap(enum pipe_tex_wrap w) { @@ -448,91 +268,6 @@ void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, } } -static void -panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - if (!ctx->rasterizer) { - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, true); - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, false); - fragmeta->depth_units = 0.0f; - fragmeta->depth_factor = 0.0f; - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, true); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, true); - return; - } - - struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; - - bool msaa = rast->multisample; - - /* TODO: Sample size */ - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - - /* EXT_shader_framebuffer_fetch requires the shader to be run - * per-sample when outputs are read. */ - bool per_sample = ctx->min_samples > 1 || fs->outputs_read; - SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); - - fragmeta->depth_units = rast->offset_units * 2.0f; - fragmeta->depth_factor = rast->offset_scale; - - /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); -} - -static void -panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta) -{ - const struct panfrost_zsa_state *so = ctx->depth_stencil; - int zfunc = PIPE_FUNC_ALWAYS; - - if (!so) { - /* If stenciling is disabled, the state is irrelevant */ - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false); - } else { - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - so->base.stencil[0].enabled); - - fragmeta->stencil_mask_front = so->stencil_mask_front; - fragmeta->stencil_mask_back = so->stencil_mask_back; - - /* Bottom bits for stencil ref, exactly one word */ - fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; - - /* If back-stencil is not enabled, use the front values */ - - if (so->base.stencil[1].enabled) - fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; - else - fragmeta->stencil_back = fragmeta->stencil_front; - - if (so->base.depth.enabled) - zfunc = so->base.depth.func; - - /* Depth state (TODO: Refactor) */ - - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - so->base.depth.writemask); - } - - fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc)); -} - static bool panfrost_fs_required( struct panfrost_shader_state *fs, @@ -555,130 +290,50 @@ panfrost_fs_required( } static void -panfrost_frag_meta_blend_update(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts) +panfrost_emit_blend(struct panfrost_batch *batch, void *rts, + struct panfrost_blend_final *blend) { - struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + const struct panfrost_device *dev = pan_device(batch->ctx->base.screen); + struct panfrost_shader_state *fs = panfrost_get_shader_state(batch->ctx, PIPE_SHADER_FRAGMENT); + unsigned rt_count = batch->key.nr_cbufs; - SET_BIT(fragmeta->unknown2_4, MALI_NO_DITHER, - (dev->quirks & MIDGARD_SFBD) && ctx->blend && - !ctx->blend->base.dither); + struct bifrost_blend_rt *brts = rts; - SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, - ctx->blend->base.alpha_to_coverage); + /* Disable blending for depth-only */ - /* Get blending setup */ - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); - - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - unsigned shader_offset = 0; - struct panfrost_bo *shader_bo = NULL; - - for (unsigned c = 0; c < rt_count; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, - &shader_offset); - - /* Disable shader execution if we can */ - if (dev->quirks & MIDGARD_SHADERLESS - && !panfrost_fs_required(fs, blend, rt_count)) { - fragmeta->shader = 0; - fragmeta->attribute_count = 0; - fragmeta->varying_count = 0; - fragmeta->texture_count = 0; - fragmeta->sampler_count = 0; - - /* This feature is not known to work on Bifrost */ - fragmeta->midgard1.work_count = 1; - fragmeta->midgard1.uniform_count = 0; - fragmeta->midgard1.uniform_buffer_count = 0; - } - - /* If there is a blend shader, work registers are shared. We impose 8 - * work registers as a limit for blend shaders. Should be lower XXX */ - - if (!(dev->quirks & IS_BIFROST)) { - for (unsigned c = 0; c < rt_count; ++c) { - if (blend[c].is_shader) { - fragmeta->midgard1.work_count = - MAX2(fragmeta->midgard1.work_count, 8); + if (rt_count == 0) { + if (dev->quirks & IS_BIFROST) { + memset(brts, 0, sizeof(*brts)); + brts[0].unk2 = 0x3; + } else { + pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) { + cfg.equation = 0xf0122122; /* Replace */ } } } - /* Even on MFBD, the shader descriptor gets blend shaders. It's *also* - * copied to the blend_meta appended (by convention), but this is the - * field actually read by the hardware. (Or maybe both are read...?). - * Specify the last RTi with a blend shader. */ - - fragmeta->blend.shader = 0; - - for (signed rt = (rt_count - 1); rt >= 0; --rt) { - if (!blend[rt].is_shader) - continue; - - fragmeta->blend.shader = blend[rt].shader.gpu | - blend[rt].shader.first_tag; - break; - } - - if (dev->quirks & MIDGARD_SFBD) { - /* When only a single render target platform is used, the blend - * information is inside the shader meta itself. We additionally - * need to signal CAN_DISCARD for nontrivial blend modes (so - * we're able to read back the destination buffer) */ - - SET_BIT(fragmeta->unknown2_3, MALI_HAS_BLEND_SHADER, - blend[0].is_shader); - - if (!blend[0].is_shader) { - fragmeta->blend.equation = *blend[0].equation.equation; - fragmeta->blend.constant = blend[0].equation.constant; - } - - SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, - !blend[0].no_blending || fs->can_discard); - - batch->draws |= PIPE_CLEAR_COLOR0; - return; - } - - if (dev->quirks & IS_BIFROST) { - bool no_blend = true; - - for (unsigned i = 0; i < rt_count; ++i) - no_blend &= (blend[i].no_blending | blend[i].no_colour); - - SET_BIT(fragmeta->bifrost1.unk1, MALI_BIFROST_EARLY_Z, - !fs->can_discard && !fs->writes_depth && no_blend); - } - - /* Additional blend descriptor tacked on for jobs using MFBD */ - for (unsigned i = 0; i < rt_count; ++i) { - unsigned flags = 0; + struct mali_blend_flags_packed flags = {}; + + pan_pack(&flags, BLEND_FLAGS, cfg) { + if (blend[i].no_colour) { + cfg.enable = false; + break; + } - if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) { - flags = 0x200; batch->draws |= (PIPE_CLEAR_COLOR0 << i); - bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) && - (ctx->pipe_framebuffer.cbufs[i]) && - util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); + cfg.srgb = util_format_is_srgb(batch->key.cbufs[i]->format); + cfg.load_destination = blend[i].load_dest; + cfg.dither_disable = !batch->ctx->blend->base.dither; - SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); - SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); - SET_BIT(flags, MALI_BLEND_SRGB, is_srgb); - SET_BIT(flags, MALI_BLEND_NO_DITHER, !ctx->blend->base.dither); + if (!(dev->quirks & IS_BIFROST)) + cfg.midgard_blend_shader = blend[i].is_shader; } if (dev->quirks & IS_BIFROST) { - struct bifrost_blend_rt *brts = rts; - - brts[i].flags = flags; + memset(brts + i, 0, sizeof(brts[i])); + brts[i].flags = flags.opaque[0]; if (blend[i].is_shader) { /* The blend shader's address needs to be at @@ -689,12 +344,12 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, (fs->bo->gpu & (0xffffffffull << 32))); brts[i].shader = blend[i].shader.gpu; brts[i].unk2 = 0x0; - } else if (ctx->pipe_framebuffer.nr_cbufs > i) { - enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; + } else { + enum pipe_format format = batch->key.cbufs[i]->format; const struct util_format_description *format_desc; format_desc = util_format_description(format); - brts[i].equation = *blend[i].equation.equation; + brts[i].equation = blend[i].equation.equation; /* TODO: this is a bit more complicated */ brts[i].constant = blend[i].equation.constant; @@ -705,162 +360,258 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, * mode (equivalent to rgb_mode = alpha_mode = * x122, colour mask = 0xF). 0x1a allows * blending. */ - brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; + brts[i].unk2 = blend[i].opaque ? 0x19 : 0x1a; - brts[i].shader_type = fs->blend_types[i]; - } else { - /* Dummy attachment for depth-only */ - brts[i].unk2 = 0x3; brts[i].shader_type = fs->blend_types[i]; } } else { - struct midgard_blend_rt *mrts = rts; - mrts[i].flags = flags; - - if (blend[i].is_shader) { - mrts[i].blend.shader = blend[i].shader.gpu | blend[i].shader.first_tag; - } else { - mrts[i].blend.equation = *blend[i].equation.equation; - mrts[i].blend.constant = blend[i].equation.constant; + pan_pack(rts, MIDGARD_BLEND_OPAQUE, cfg) { + cfg.flags = flags; + + if (blend[i].is_shader) { + cfg.shader = blend[i].shader.gpu | blend[i].shader.first_tag; + } else { + cfg.equation = blend[i].equation.equation.opaque[0]; + cfg.constant = blend[i].equation.constant; + } } + + rts += MALI_MIDGARD_BLEND_LENGTH; } } } static void -panfrost_frag_shader_meta_init(struct panfrost_context *ctx, - struct mali_shader_meta *fragmeta, - void *rts) +panfrost_emit_frag_shader(struct panfrost_context *ctx, + struct mali_state_packed *fragmeta, + struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); - struct panfrost_shader_state *fs; + struct panfrost_shader_state *fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; + const struct panfrost_zsa_state *zsa = ctx->depth_stencil; + unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; + bool alpha_to_coverage = ctx->blend->base.alpha_to_coverage; + + /* Built up here */ + struct mali_shader_packed shader = fs->shader; + struct mali_preload_packed preload = fs->preload; + uint32_t properties; + struct mali_multisample_misc_packed multisample_misc; + struct mali_stencil_mask_misc_packed stencil_mask_misc; + union midgard_blend sfbd_blend = { 0 }; + + if (!panfrost_fs_required(fs, blend, rt_count)) { + if (dev->quirks & IS_BIFROST) { + pan_pack(&shader, SHADER, cfg) {} - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { + cfg.unknown = 0x950020; /* XXX */ + cfg.early_z_enable = true; + } - bool msaa = ctx->rasterizer && ctx->rasterizer->base.multisample; - fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; + preload.opaque[0] = 0; + } else { + pan_pack(&shader, SHADER, cfg) { + cfg.shader = 0x1; + } - fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; - fragmeta->unknown2_4 = 0x4e0; + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { + cfg.work_register_count = 1; + cfg.depth_source = MALI_DEPTH_SOURCE_FIXED_FUNCTION; + cfg.early_z_enable = true; + } + } + } else if (dev->quirks & IS_BIFROST) { + bool no_blend = true; - /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this - * is required (independent of 32-bit/64-bit descriptors), or why it's - * not used on later GPU revisions. Otherwise, all shader jobs fault on - * these earlier chips (perhaps this is a chicken bit of some kind). - * More investigation is needed. */ + for (unsigned i = 0; i < rt_count; ++i) + no_blend &= (!blend[i].load_dest | blend[i].no_colour); - SET_BIT(fragmeta->unknown2_4, 0x10, dev->quirks & MIDGARD_SFBD); + pan_pack(&properties, BIFROST_PROPERTIES, cfg) { + cfg.early_z_enable = !fs->can_discard && !fs->writes_depth && no_blend; + } - if (dev->quirks & IS_BIFROST) { - /* TODO */ + /* Combine with prepacked properties */ + properties |= fs->properties.opaque[0]; } else { - /* Depending on whether it's legal to in the given shader, we try to - * enable early-z testing. TODO: respect e-z force */ + /* Reasons to disable early-Z from a shader perspective */ + bool late_z = fs->can_discard || fs->writes_global || + fs->writes_depth || fs->writes_stencil; + + /* If either depth or stencil is enabled, discard matters */ + bool zs_enabled = + (zsa->base.depth.enabled && zsa->base.depth.func != PIPE_FUNC_ALWAYS) || + zsa->base.stencil[0].enabled; + + bool has_blend_shader = false; + + for (unsigned c = 0; c < rt_count; ++c) + has_blend_shader |= blend[c].is_shader; + + pan_pack(&properties, MIDGARD_PROPERTIES, cfg) { + /* TODO: Reduce this limit? */ + if (has_blend_shader) + cfg.work_register_count = MAX2(fs->work_reg_count, 8); + else + cfg.work_register_count = fs->work_reg_count; + + cfg.early_z_enable = !(late_z || alpha_to_coverage); + cfg.reads_tilebuffer = fs->outputs_read || (!zs_enabled && fs->can_discard); + cfg.reads_depth_stencil = zs_enabled && fs->can_discard; + } + + properties |= fs->properties.opaque[0]; + } - SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, - !fs->can_discard && !fs->writes_global && - !fs->writes_depth && !fs->writes_stencil && - !ctx->blend->base.alpha_to_coverage); + pan_pack(&multisample_misc, MULTISAMPLE_MISC, cfg) { + bool msaa = rast->multisample; + cfg.multisample_enable = msaa; + cfg.sample_mask = (msaa ? ctx->sample_mask : ~0) & 0xFFFF; - /* Add the writes Z/S flags if needed. */ - SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); - SET_BIT(fragmeta->midgard1.flags_hi, MALI_WRITES_S, fs->writes_stencil); + /* EXT_shader_framebuffer_fetch requires per-sample */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + cfg.evaluate_per_sample = msaa && per_sample; - /* Any time texturing is used, derivatives are implicitly calculated, - * so we need to enable helper invocations */ + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_load_destination = blend[0].load_dest; + cfg.sfbd_blend_shader = blend[0].is_shader; + } - SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, - fs->helper_invocations); + cfg.depth_function = zsa->base.depth.enabled ? + panfrost_translate_compare_func(zsa->base.depth.func) : + MALI_FUNC_ALWAYS; - /* If discard is enabled, which bit we set to convey this - * depends on if depth/stencil is used for the draw or not. - * Just one of depth OR stencil is enough to trigger this. */ + cfg.depth_write_mask = zsa->base.depth.writemask; + cfg.near_discard = rast->depth_clip_near; + cfg.far_discard = rast->depth_clip_far; + cfg.unknown_2 = true; + } - const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; - bool zs_enabled = fs->writes_depth || fs->writes_stencil; + pan_pack(&stencil_mask_misc, STENCIL_MASK_MISC, cfg) { + cfg.stencil_mask_front = zsa->stencil_mask_front; + cfg.stencil_mask_back = zsa->stencil_mask_back; + cfg.stencil_enable = zsa->base.stencil[0].enabled; + cfg.alpha_to_coverage = alpha_to_coverage; - if (zsa) { - zs_enabled |= (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS); - zs_enabled |= zsa->stencil[0].enabled; + if (dev->quirks & MIDGARD_SFBD) { + cfg.sfbd_write_enable = !blend[0].no_colour; + cfg.sfbd_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[0]->format); + cfg.sfbd_dither_disable = !ctx->blend->base.dither; } - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, - fs->outputs_read || (!zs_enabled && fs->can_discard)); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); + cfg.unknown_1 = 0x7; + cfg.depth_range_1 = cfg.depth_range_2 = rast->offset_tri; + cfg.single_sampled_lines = !rast->multisample; } - panfrost_frag_meta_rasterizer_update(ctx, fragmeta); - panfrost_frag_meta_zsa_update(ctx, fragmeta); - panfrost_frag_meta_blend_update(ctx, fragmeta, rts); -} + if (dev->quirks & MIDGARD_SFBD) { + if (blend[0].is_shader) { + sfbd_blend.shader = blend[0].shader.gpu | + blend[0].shader.first_tag; + } else { + sfbd_blend.equation = blend[0].equation.equation; + sfbd_blend.constant = blend[0].equation.constant; + } + } else if (!(dev->quirks & IS_BIFROST)) { + /* Bug where MRT-capable hw apparently reads the last blend + * shader from here instead of the usual location? */ -void -panfrost_emit_shader_meta(struct panfrost_batch *batch, - enum pipe_shader_type st, - struct mali_vertex_tiler_postfix *postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, st); + for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { + if (!blend[rt].is_shader) + continue; - if (!ss) { - postfix->shader = 0; - return; + sfbd_blend.shader = blend[rt].shader.gpu | + blend[rt].shader.first_tag; + break; + } } - struct mali_shader_meta meta; + pan_pack(fragmeta, STATE_OPAQUE, cfg) { + cfg.shader = fs->shader; + cfg.properties = properties; + cfg.depth_units = rast->offset_units * 2.0f; + cfg.depth_factor = rast->offset_scale; + cfg.multisample_misc = multisample_misc; + cfg.stencil_mask_misc = stencil_mask_misc; - panfrost_shader_meta_init(ctx, st, &meta); + cfg.stencil_front = zsa->stencil_front; + cfg.stencil_back = zsa->stencil_back; + + /* Bottom bits for stencil ref, exactly one word */ + bool back_enab = zsa->base.stencil[1].enabled; + cfg.stencil_front.opaque[0] |= ctx->stencil_ref.ref_value[0]; + cfg.stencil_back.opaque[0] |= ctx->stencil_ref.ref_value[back_enab ? 1 : 0]; + + if (dev->quirks & IS_BIFROST) + cfg.preload = preload; + else + memcpy(&cfg.sfbd_blend, &sfbd_blend, sizeof(sfbd_blend)); + } +} + +mali_ptr +panfrost_emit_compute_shader_meta(struct panfrost_batch *batch, enum pipe_shader_type stage) +{ + struct panfrost_shader_state *ss = panfrost_get_shader_state(batch->ctx, stage); - /* Add the shader BO to the batch. */ panfrost_batch_add_bo(batch, ss->bo, PAN_BO_ACCESS_PRIVATE | PAN_BO_ACCESS_READ | - panfrost_bo_access_for_stage(st)); + PAN_BO_ACCESS_VERTEX_TILER); - mali_ptr shader_ptr; + panfrost_batch_add_bo(batch, pan_resource(ss->upload.rsrc)->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_VERTEX_TILER); - if (st == PIPE_SHADER_FRAGMENT) { - struct panfrost_device *dev = pan_device(ctx->base.screen); - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); - size_t desc_size = sizeof(meta); - void *rts = NULL; - struct panfrost_transfer xfer; - unsigned rt_size; + return pan_resource(ss->upload.rsrc)->bo->gpu + ss->upload.offset; +} - if (dev->quirks & MIDGARD_SFBD) - rt_size = 0; - else if (dev->quirks & IS_BIFROST) - rt_size = sizeof(struct bifrost_blend_rt); - else - rt_size = sizeof(struct midgard_blend_rt); +mali_ptr +panfrost_emit_frag_shader_meta(struct panfrost_batch *batch) +{ + struct panfrost_context *ctx = batch->ctx; + struct panfrost_shader_state *ss = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - desc_size += rt_size * rt_count; + /* Add the shader BO to the batch. */ + panfrost_batch_add_bo(batch, ss->bo, + PAN_BO_ACCESS_PRIVATE | + PAN_BO_ACCESS_READ | + PAN_BO_ACCESS_FRAGMENT); - if (rt_size) - rts = rzalloc_size(ctx, rt_size * rt_count); + struct panfrost_device *dev = pan_device(ctx->base.screen); + unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); + struct panfrost_transfer xfer; + unsigned rt_size; - panfrost_frag_shader_meta_init(ctx, &meta, rts); + if (dev->quirks & MIDGARD_SFBD) + rt_size = 0; + else if (dev->quirks & IS_BIFROST) + rt_size = sizeof(struct bifrost_blend_rt); + else + rt_size = sizeof(struct midgard_blend_rt); - xfer = panfrost_pool_alloc(&batch->pool, desc_size); + unsigned desc_size = MALI_STATE_LENGTH + rt_size * rt_count; + xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, MALI_STATE_LENGTH); - memcpy(xfer.cpu, &meta, sizeof(meta)); - memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - if (rt_size) - ralloc_free(rts); + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); - shader_ptr = xfer.gpu; - } else { - shader_ptr = panfrost_pool_upload(&batch->pool, &meta, - sizeof(meta)); - } + panfrost_emit_frag_shader(ctx, (struct mali_state_packed *) xfer.cpu, blend); - postfix->shader = shader_ptr; + if (!(dev->quirks & MIDGARD_SFBD)) + panfrost_emit_blend(batch, xfer.cpu + MALI_STATE_LENGTH, blend); + else + batch->draws |= PIPE_CLEAR_COLOR0; + + return xfer.gpu; } -void -panfrost_emit_viewport(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *tiler_postfix) +mali_ptr +panfrost_emit_viewport(struct panfrost_batch *batch) { struct panfrost_context *ctx = batch->ctx; const struct pipe_viewport_state *vp = &ctx->pipe_viewport; @@ -886,7 +637,7 @@ panfrost_emit_viewport(struct panfrost_batch *batch, unsigned miny = MIN2(fb->height, vp_miny); unsigned maxy = MIN2(fb->height, vp_maxy); - if (ss && rast && rast->scissor) { + if (ss && rast->scissor) { minx = MAX2(ss->minx, minx); miny = MAX2(ss->miny, miny); maxx = MIN2(ss->maxx, maxx); @@ -905,8 +656,8 @@ panfrost_emit_viewport(struct panfrost_batch *batch, cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY; } - tiler_postfix->viewport = T.gpu; panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy); + return T.gpu; } static mali_ptr @@ -928,10 +679,10 @@ panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ return rsrc->bo->gpu + cb->buffer_offset; } else if (cb->user_buffer) { - return panfrost_pool_upload(&batch->pool, + return panfrost_pool_upload_aligned(&batch->pool, cb->user_buffer + cb->buffer_offset, - cb->buffer_size); + cb->buffer_size, 16); } else { unreachable("No constant buffer"); } @@ -1111,16 +862,16 @@ panfrost_map_constant_buffer_cpu(struct panfrost_constant_buffer *buf, unreachable("No constant buffer"); } -void +mali_ptr panfrost_emit_const_buf(struct panfrost_batch *batch, enum pipe_shader_type stage, - struct mali_vertex_tiler_postfix *postfix) + mali_ptr *push_constants) { struct panfrost_context *ctx = batch->ctx; struct panfrost_shader_variants *all = ctx->shader[stage]; if (!all) - return; + return 0; struct panfrost_constant_buffer *buf = &ctx->constant_buffer[stage]; @@ -1133,8 +884,8 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, size_t sys_size = sizeof(float) * 4 * ss->sysval_count; size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0; size_t size = sys_size + uniform_size; - struct panfrost_transfer transfer = panfrost_pool_alloc(&batch->pool, - size); + struct panfrost_transfer transfer = + panfrost_pool_alloc_aligned(&batch->pool, size, 16); /* Upload sysvals requested by the shader */ panfrost_upload_sysvals(batch, transfer.cpu, ss, stage); @@ -1146,20 +897,23 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, } /* Next up, attach UBOs. UBO #0 is the uniforms we just - * uploaded */ + * uploaded, so it's always included. The count is the highest UBO + * addressable -- gaps are included. */ - unsigned ubo_count = panfrost_ubo_count(ctx, stage); - assert(ubo_count >= 1); + unsigned ubo_count = 32 - __builtin_clz(buf->enabled_mask | 1); size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; - struct panfrost_transfer ubos = panfrost_pool_alloc(&batch->pool, sz); + struct panfrost_transfer ubos = + panfrost_pool_alloc_aligned(&batch->pool, sz, + MALI_UNIFORM_BUFFER_LENGTH); + uint64_t *ubo_ptr = (uint64_t *) ubos.cpu; /* Upload uniforms as a UBO */ - if (ss->uniform_count) { + if (size) { pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { - cfg.entries = ss->uniform_count; + cfg.entries = DIV_ROUND_UP(size, 16); cfg.pointer = transfer.gpu; } } else { @@ -1185,40 +939,41 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, } } - postfix->uniforms = transfer.gpu; - postfix->uniform_buffers = ubos.gpu; + *push_constants = transfer.gpu; buf->dirty_mask = 0; + return ubos.gpu; } -void +mali_ptr panfrost_emit_shared_memory(struct panfrost_batch *batch, - const struct pipe_grid_info *info, - struct midgard_payload_vertex_tiler *vtp) + const struct pipe_grid_info *info) { struct panfrost_context *ctx = batch->ctx; + struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE]; struct panfrost_shader_state *ss = &all->variants[all->active_variant]; unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size, 128)); - unsigned shared_size = single_size * info->grid[0] * info->grid[1] * - info->grid[2] * 4; + + unsigned log2_instances = + util_logbase2_ceil(info->grid[0]) + + util_logbase2_ceil(info->grid[1]) + + util_logbase2_ceil(info->grid[2]); + + unsigned shared_size = single_size * (1 << log2_instances) * dev->core_count; struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch, shared_size, 1); struct mali_shared_memory shared = { .shared_memory = bo->gpu, - .shared_workgroup_count = - util_logbase2_ceil(info->grid[0]) + - util_logbase2_ceil(info->grid[1]) + - util_logbase2_ceil(info->grid[2]), - .shared_unk1 = 0x2, - .shared_shift = util_logbase2(single_size) - 1 + .shared_workgroup_count = log2_instances, + .shared_shift = util_logbase2(single_size) + 1 }; - vtp->postfix.shared_memory = panfrost_pool_upload(&batch->pool, &shared, - sizeof(shared)); + return panfrost_pool_upload_aligned(&batch->pool, &shared, + sizeof(shared), 64); } static mali_ptr @@ -1257,21 +1012,21 @@ panfrost_update_sampler_view(struct panfrost_sampler_view *view, } } -void +mali_ptr panfrost_emit_texture_descriptors(struct panfrost_batch *batch, - enum pipe_shader_type stage, - struct mali_vertex_tiler_postfix *postfix) + enum pipe_shader_type stage) { struct panfrost_context *ctx = batch->ctx; struct panfrost_device *device = pan_device(ctx->base.screen); if (!ctx->sampler_view_count[stage]) - return; + return 0; if (device->quirks & IS_BIFROST) { - struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, MALI_BIFROST_TEXTURE_LENGTH * - ctx->sampler_view_count[stage]); + ctx->sampler_view_count[stage], + MALI_BIFROST_TEXTURE_LENGTH); struct mali_bifrost_texture_packed *out = (struct mali_bifrost_texture_packed *) T.cpu; @@ -1295,7 +1050,7 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, panfrost_bo_access_for_stage(stage)); } - postfix->textures = T.gpu; + return T.gpu; } else { uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; @@ -1307,53 +1062,53 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, trampolines[i] = panfrost_get_tex_desc(batch, stage, view); } - postfix->textures = panfrost_pool_upload(&batch->pool, - trampolines, - sizeof(uint64_t) * - ctx->sampler_view_count[stage]); + return panfrost_pool_upload_aligned(&batch->pool, trampolines, + sizeof(uint64_t) * + ctx->sampler_view_count[stage], + sizeof(uint64_t)); } } -void +mali_ptr panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, - enum pipe_shader_type stage, - struct mali_vertex_tiler_postfix *postfix) + enum pipe_shader_type stage) { struct panfrost_context *ctx = batch->ctx; if (!ctx->sampler_count[stage]) - return; + return 0; size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); size_t sz = desc_size * ctx->sampler_count[stage]; - struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, sz); + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, sz, desc_size); struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu; for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) out[i] = ctx->samplers[stage][i]->hw; - postfix->sampler_descriptor = T.gpu; + return T.gpu; } -void +mali_ptr panfrost_emit_vertex_data(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *vertex_postfix) + mali_ptr *buffers) { struct panfrost_context *ctx = batch->ctx; struct panfrost_vertex_state *so = ctx->vertex; + struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); - unsigned instance_shift = vertex_postfix->instance_shift; - unsigned instance_odd = vertex_postfix->instance_odd; - - /* Worst case: everything is NPOT */ + /* Worst case: everything is NPOT, which is only possible if instancing + * is enabled. Otherwise single record is gauranteed */ + struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count * + (ctx->instance_count > 1 ? 2 : 1), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); - struct panfrost_transfer S = panfrost_pool_alloc(&batch->pool, - MALI_ATTRIBUTE_LENGTH * PIPE_MAX_ATTRIBS * 2); - - struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, - MALI_ATTRIBUTE_LENGTH * (PAN_INSTANCE_ID + 1)); + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_LENGTH * vs->attribute_count, + MALI_ATTRIBUTE_LENGTH); struct mali_attribute_buffer_packed *bufs = (struct mali_attribute_buffer_packed *) S.cpu; @@ -1413,14 +1168,14 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, if (!divisor || ctx->instance_count <= 1) { pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { - if (ctx->instance_count > 1) + if (ctx->instance_count > 1) { cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS; + cfg.divisor = ctx->padded_count; + } cfg.pointer = addr; cfg.stride = stride; cfg.size = size; - cfg.divisor_r = instance_shift; - cfg.divisor_p = instance_odd; } } else if (util_is_power_of_two_or_zero(hw_divisor)) { pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { @@ -1460,18 +1215,20 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, /* Add special gl_VertexID/gl_InstanceID buffers */ - panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); + if (unlikely(vs->attribute_count >= PAN_VERTEX_ID)) { + panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); - pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { - cfg.buffer_index = k++; - cfg.format = so->formats[PAN_VERTEX_ID]; - } + pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_VERTEX_ID]; + } - panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); + panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); - pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { - cfg.buffer_index = k++; - cfg.format = so->formats[PAN_INSTANCE_ID]; + pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_INSTANCE_ID]; + } } /* Attribute addresses require 64-byte alignment, so let: @@ -1483,8 +1240,6 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, * addressing modes and now base is 64 aligned. */ - unsigned start = vertex_postfix->offset_start; - for (unsigned i = 0; i < so->num_elements; ++i) { unsigned vbi = so->pipe[i].vertex_buffer_index; struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; @@ -1501,8 +1256,8 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, /* Also, somewhat obscurely per-instance data needs to be * offset in response to a delayed start in an indexed draw */ - if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) - src_offset -= buf->stride * start; + if (so->pipe[i].instance_divisor && ctx->instance_count > 1) + src_offset -= buf->stride * ctx->offset_start; pan_pack(out + i, ATTRIBUTE, cfg) { cfg.buffer_index = attrib_to_buffer[i]; @@ -1511,8 +1266,8 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, } } - vertex_postfix->attributes = S.gpu; - vertex_postfix->attribute_meta = T.gpu; + *buffers = S.gpu; + return T.gpu; } static mali_ptr @@ -1521,7 +1276,7 @@ panfrost_emit_varyings(struct panfrost_batch *batch, unsigned stride, unsigned count) { unsigned size = stride * count; - mali_ptr ptr = panfrost_pool_alloc(&batch->pool, size).gpu; + mali_ptr ptr = panfrost_pool_alloc_aligned(&batch->invisible_pool, size, 64).gpu; pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { cfg.stride = stride; @@ -1939,9 +1694,11 @@ pan_emit_special_input(struct mali_attribute_buffer_packed *out, void panfrost_emit_varying_descriptor(struct panfrost_batch *batch, unsigned vertex_count, - struct mali_vertex_tiler_postfix *vertex_postfix, - struct mali_vertex_tiler_postfix *tiler_postfix, - union midgard_primitive_size *primitive_size) + mali_ptr *vs_attribs, + mali_ptr *fs_attribs, + mali_ptr *buffers, + mali_ptr *position, + mali_ptr *psiz) { /* Load the shaders */ struct panfrost_context *ctx = batch->ctx; @@ -1956,9 +1713,8 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, vs_size = MALI_ATTRIBUTE_LENGTH * vs->varying_count; fs_size = MALI_ATTRIBUTE_LENGTH * fs->varying_count; - struct panfrost_transfer trans = panfrost_pool_alloc(&batch->pool, - vs_size + - fs_size); + struct panfrost_transfer trans = panfrost_pool_alloc_aligned( + &batch->pool, vs_size + fs_size, MALI_ATTRIBUTE_LENGTH); struct pipe_stream_output_info *so = &vs->stream_output; unsigned present = pan_varying_present(vs, fs, dev->quirks); @@ -2004,8 +1760,9 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, } unsigned xfb_base = pan_xfb_base(present); - struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, - MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets)); + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); struct mali_attribute_buffer_packed *varyings = (struct mali_attribute_buffer_packed *) T.cpu; @@ -2027,12 +1784,12 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, gen_stride, vertex_count); /* fp32 vec4 gl_Position */ - tiler_postfix->position_varying = panfrost_emit_varyings(batch, + *position = panfrost_emit_varyings(batch, &varyings[pan_varying_index(present, PAN_VARY_POSITION)], sizeof(float) * 4, vertex_count); if (present & (1 << PAN_VARY_PSIZ)) { - primitive_size->pointer = panfrost_emit_varyings(batch, + *psiz = panfrost_emit_varyings(batch, &varyings[pan_varying_index(present, PAN_VARY_PSIZ)], 2, vertex_count); } @@ -2041,19 +1798,17 @@ panfrost_emit_varying_descriptor(struct panfrost_batch *batch, pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING); pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD); - vertex_postfix->varyings = T.gpu; - tiler_postfix->varyings = T.gpu; - - vertex_postfix->varying_meta = trans.gpu; - tiler_postfix->varying_meta = trans.gpu + vs_size; + *buffers = T.gpu; + *vs_attribs = trans.gpu; + *fs_attribs = trans.gpu + vs_size; } void panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, struct mali_vertex_tiler_prefix *vertex_prefix, - struct mali_vertex_tiler_postfix *vertex_postfix, + struct mali_draw_packed *vertex_draw, struct mali_vertex_tiler_prefix *tiler_prefix, - struct mali_vertex_tiler_postfix *tiler_postfix, + struct mali_draw_packed *tiler_draw, union midgard_primitive_size *primitive_size) { struct panfrost_context *ctx = batch->ctx; @@ -2068,24 +1823,24 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, if (device->quirks & IS_BIFROST) { bifrost_vertex.prefix = *vertex_prefix; - bifrost_vertex.postfix = *vertex_postfix; + memcpy(&bifrost_vertex.postfix, vertex_draw, MALI_DRAW_LENGTH); vp = &bifrost_vertex; vp_size = sizeof(bifrost_vertex); bifrost_tiler.prefix = *tiler_prefix; bifrost_tiler.tiler.primitive_size = *primitive_size; bifrost_tiler.tiler.tiler_meta = panfrost_batch_get_tiler_meta(batch, ~0); - bifrost_tiler.postfix = *tiler_postfix; + memcpy(&bifrost_tiler.postfix, tiler_draw, MALI_DRAW_LENGTH); tp = &bifrost_tiler; tp_size = sizeof(bifrost_tiler); } else { midgard_vertex.prefix = *vertex_prefix; - midgard_vertex.postfix = *vertex_postfix; + memcpy(&midgard_vertex.postfix, vertex_draw, MALI_DRAW_LENGTH); vp = &midgard_vertex; vp_size = sizeof(midgard_vertex); midgard_tiler.prefix = *tiler_prefix; - midgard_tiler.postfix = *tiler_postfix; + memcpy(&midgard_tiler.postfix, tiler_draw, MALI_DRAW_LENGTH); midgard_tiler.primitive_size = *primitive_size; tp = &midgard_tiler; tp_size = sizeof(midgard_tiler); @@ -2103,13 +1858,10 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, /* If rasterizer discard is enable, only submit the vertex */ - bool rasterizer_discard = ctx->rasterizer && - ctx->rasterizer->base.rasterizer_discard; - unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, vp, vp_size, false); - if (rasterizer_discard) + if (ctx->rasterizer->base.rasterizer_discard) return; panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size, @@ -2171,5 +1923,5 @@ panfrost_emit_sample_locations(struct panfrost_batch *batch) 0, 0, }; - return panfrost_pool_upload(&batch->pool, locations, 96 * sizeof(uint16_t)); + return panfrost_pool_upload_aligned(&batch->pool, locations, 96 * sizeof(uint16_t), 64); }