X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_cmdstream.c;h=bc9158b03af6b026b79709eac2de53cef317bc8e;hb=cfef6de429d40785a306ef2a2db7092c4ce0388a;hp=14d013f08c9873067c49e9be374548d9cc39bd4f;hpb=20f6c7a9134062b6e16f7a5bd16c197cc2055e9b;p=mesa.git diff --git a/src/gallium/drivers/panfrost/pan_cmdstream.c b/src/gallium/drivers/panfrost/pan_cmdstream.c index 14d013f08c9..bc9158b03af 100644 --- a/src/gallium/drivers/panfrost/pan_cmdstream.c +++ b/src/gallium/drivers/panfrost/pan_cmdstream.c @@ -28,7 +28,7 @@ #include "panfrost-quirks.h" -#include "pan_allocate.h" +#include "pan_pool.h" #include "pan_bo.h" #include "pan_cmdstream.h" #include "pan_context.h" @@ -58,55 +58,45 @@ panfrost_vt_emit_shared_memory(struct panfrost_context *ctx, struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - unsigned shift = panfrost_get_stack_shift(batch->stack_size); struct mali_shared_memory shared = { - .stack_shift = shift, - .scratchpad = panfrost_batch_get_scratchpad(batch, shift, dev->thread_tls_alloc, dev->core_count)->gpu, .shared_workgroup_count = ~0, }; - postfix->shared_memory = panfrost_upload_transient(batch, &shared, sizeof(shared)); + + if (batch->stack_size) { + struct panfrost_bo *stack = + panfrost_batch_get_scratchpad(batch, batch->stack_size, + dev->thread_tls_alloc, + dev->core_count); + + shared.stack_shift = panfrost_get_stack_shift(batch->stack_size); + shared.scratchpad = stack->gpu; + } + + postfix->shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, sizeof(shared), 64); } static void panfrost_vt_attach_framebuffer(struct panfrost_context *ctx, struct mali_vertex_tiler_postfix *postfix) { - struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - - /* If we haven't, reserve space for the framebuffer */ - - if (!batch->framebuffer.gpu) { - unsigned size = (dev->quirks & MIDGARD_SFBD) ? - sizeof(struct mali_single_framebuffer) : - sizeof(struct mali_framebuffer); - - batch->framebuffer = panfrost_allocate_transient(batch, size); - - /* Tag the pointer */ - if (!(dev->quirks & MIDGARD_SFBD)) - batch->framebuffer.gpu |= MALI_MFBD; - } - - postfix->shared_memory = batch->framebuffer.gpu; + postfix->shared_memory = panfrost_batch_reserve_framebuffer(batch); } static void -panfrost_vt_update_rasterizer(struct panfrost_context *ctx, +panfrost_vt_update_rasterizer(struct panfrost_rasterizer *rasterizer, struct mali_vertex_tiler_prefix *prefix, struct mali_vertex_tiler_postfix *postfix) { - struct panfrost_rasterizer *rasterizer = ctx->rasterizer; - postfix->gl_enables |= 0x7; SET_BIT(postfix->gl_enables, MALI_FRONT_CCW_TOP, - rasterizer && rasterizer->base.front_ccw); + rasterizer->base.front_ccw); SET_BIT(postfix->gl_enables, MALI_CULL_FACE_FRONT, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_FRONT)); + (rasterizer->base.cull_face & PIPE_FACE_FRONT)); SET_BIT(postfix->gl_enables, MALI_CULL_FACE_BACK, - rasterizer && (rasterizer->base.cull_face & PIPE_FACE_BACK)); + (rasterizer->base.cull_face & PIPE_FACE_BACK)); SET_BIT(prefix->unknown_draw, MALI_DRAW_FLATSHADE_FIRST, - rasterizer && rasterizer->base.flatshade_first); + rasterizer->base.flatshade_first); } void @@ -117,11 +107,7 @@ panfrost_vt_update_primitive_size(struct panfrost_context *ctx, struct panfrost_rasterizer *rasterizer = ctx->rasterizer; if (!panfrost_writes_point_size(ctx)) { - bool points = prefix->draw_mode == MALI_POINTS; - float val = 0.0f; - - if (rasterizer) - val = points ? + float val = (prefix->draw_mode == MALI_DRAW_MODE_POINTS) ? rasterizer->base.point_size : rasterizer->base.line_width; @@ -134,10 +120,15 @@ panfrost_vt_update_occlusion_query(struct panfrost_context *ctx, struct mali_vertex_tiler_postfix *postfix) { SET_BIT(postfix->gl_enables, MALI_OCCLUSION_QUERY, ctx->occlusion_query); - if (ctx->occlusion_query) + if (ctx->occlusion_query) { postfix->occlusion_counter = ctx->occlusion_query->bo->gpu; - else + panfrost_batch_add_bo(ctx->batch, ctx->occlusion_query->bo, + PAN_BO_ACCESS_SHARED | + PAN_BO_ACCESS_RW | + PAN_BO_ACCESS_FRAGMENT); + } else { postfix->occlusion_counter = 0; + } } void @@ -164,7 +155,7 @@ panfrost_vt_init(struct panfrost_context *ctx, if (stage == PIPE_SHADER_FRAGMENT) { panfrost_vt_update_occlusion_query(ctx, postfix); - panfrost_vt_update_rasterizer(ctx, prefix, postfix); + panfrost_vt_update_rasterizer(ctx->rasterizer, prefix, postfix); } } @@ -226,9 +217,13 @@ panfrost_get_index_buffer_bounded(struct panfrost_context *ctx, } else { /* Otherwise, we need to upload to transient memory */ const uint8_t *ibuf8 = (const uint8_t *) info->index.user; - out = panfrost_upload_transient(batch, ibuf8 + offset, - info->count * - info->index_size); + struct panfrost_transfer T = + panfrost_pool_alloc_aligned(&batch->pool, + info->count * info->index_size, + info->index_size); + + memcpy(T.cpu, ibuf8 + offset, info->count * info->index_size); + out = T.gpu; } if (needs_indices) { @@ -353,277 +348,172 @@ panfrost_shader_meta_init(struct panfrost_context *ctx, /* TODO: This is not conformant on ES3 */ meta->midgard1.flags_hi = MALI_SUPPRESS_INF_NAN; - meta->midgard1.flags_lo = 0x220; + meta->midgard1.flags_lo = 0x20; meta->midgard1.uniform_buffer_count = panfrost_ubo_count(ctx, st); + + SET_BIT(meta->midgard1.flags_lo, MALI_WRITES_GLOBAL, ss->writes_global); } } static unsigned -panfrost_translate_compare_func(enum pipe_compare_func in) +translate_tex_wrap(enum pipe_tex_wrap w) { - switch (in) { - case PIPE_FUNC_NEVER: - return MALI_FUNC_NEVER; - - case PIPE_FUNC_LESS: - return MALI_FUNC_LESS; - - case PIPE_FUNC_EQUAL: - return MALI_FUNC_EQUAL; - - case PIPE_FUNC_LEQUAL: - return MALI_FUNC_LEQUAL; - - case PIPE_FUNC_GREATER: - return MALI_FUNC_GREATER; - - case PIPE_FUNC_NOTEQUAL: - return MALI_FUNC_NOTEQUAL; - - case PIPE_FUNC_GEQUAL: - return MALI_FUNC_GEQUAL; - - case PIPE_FUNC_ALWAYS: - return MALI_FUNC_ALWAYS; - - default: - unreachable("Invalid func"); + switch (w) { + case PIPE_TEX_WRAP_REPEAT: return MALI_WRAP_MODE_REPEAT; + case PIPE_TEX_WRAP_CLAMP: return MALI_WRAP_MODE_CLAMP; + case PIPE_TEX_WRAP_CLAMP_TO_EDGE: return MALI_WRAP_MODE_CLAMP_TO_EDGE; + case PIPE_TEX_WRAP_CLAMP_TO_BORDER: return MALI_WRAP_MODE_CLAMP_TO_BORDER; + case PIPE_TEX_WRAP_MIRROR_REPEAT: return MALI_WRAP_MODE_MIRRORED_REPEAT; + case PIPE_TEX_WRAP_MIRROR_CLAMP: return MALI_WRAP_MODE_MIRRORED_CLAMP; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_EDGE; + case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: return MALI_WRAP_MODE_MIRRORED_CLAMP_TO_BORDER; + default: unreachable("Invalid wrap"); } } -static unsigned -panfrost_translate_stencil_op(enum pipe_stencil_op in) -{ - switch (in) { - case PIPE_STENCIL_OP_KEEP: - return MALI_STENCIL_KEEP; - - case PIPE_STENCIL_OP_ZERO: - return MALI_STENCIL_ZERO; - - case PIPE_STENCIL_OP_REPLACE: - return MALI_STENCIL_REPLACE; - - case PIPE_STENCIL_OP_INCR: - return MALI_STENCIL_INCR; - - case PIPE_STENCIL_OP_DECR: - return MALI_STENCIL_DECR; +/* The hardware compares in the wrong order order, so we have to flip before + * encoding. Yes, really. */ - case PIPE_STENCIL_OP_INCR_WRAP: - return MALI_STENCIL_INCR_WRAP; - - case PIPE_STENCIL_OP_DECR_WRAP: - return MALI_STENCIL_DECR_WRAP; +static enum mali_func +panfrost_sampler_compare_func(const struct pipe_sampler_state *cso) +{ + if (!cso->compare_mode) + return MALI_FUNC_NEVER; - case PIPE_STENCIL_OP_INVERT: - return MALI_STENCIL_INVERT; + enum mali_func f = panfrost_translate_compare_func(cso->compare_func); + return panfrost_flip_compare_func(f); +} - default: - unreachable("Invalid stencil op"); +static enum mali_mipmap_mode +pan_pipe_to_mipmode(enum pipe_tex_mipfilter f) +{ + switch (f) { + case PIPE_TEX_MIPFILTER_NEAREST: return MALI_MIPMAP_MODE_NEAREST; + case PIPE_TEX_MIPFILTER_LINEAR: return MALI_MIPMAP_MODE_TRILINEAR; + case PIPE_TEX_MIPFILTER_NONE: return MALI_MIPMAP_MODE_NONE; + default: unreachable("Invalid"); } } -static unsigned -translate_tex_wrap(enum pipe_tex_wrap w) +void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, + struct mali_midgard_sampler_packed *hw) { - switch (w) { - case PIPE_TEX_WRAP_REPEAT: - return MALI_WRAP_REPEAT; - - case PIPE_TEX_WRAP_CLAMP: - return MALI_WRAP_CLAMP; + pan_pack(hw, MIDGARD_SAMPLER, cfg) { + cfg.magnify_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; + cfg.minify_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; + cfg.mipmap_mode = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR) ? + MALI_MIPMAP_MODE_TRILINEAR : MALI_MIPMAP_MODE_NEAREST; + cfg.normalized_coordinates = cso->normalized_coords; - case PIPE_TEX_WRAP_CLAMP_TO_EDGE: - return MALI_WRAP_CLAMP_TO_EDGE; + cfg.lod_bias = FIXED_16(cso->lod_bias, true); - case PIPE_TEX_WRAP_CLAMP_TO_BORDER: - return MALI_WRAP_CLAMP_TO_BORDER; + cfg.minimum_lod = FIXED_16(cso->min_lod, false); - case PIPE_TEX_WRAP_MIRROR_REPEAT: - return MALI_WRAP_MIRRORED_REPEAT; + /* If necessary, we disable mipmapping in the sampler descriptor by + * clamping the LOD as tight as possible (from 0 to epsilon, + * essentially -- remember these are fixed point numbers, so + * epsilon=1/256) */ - case PIPE_TEX_WRAP_MIRROR_CLAMP: - return MALI_WRAP_MIRRORED_CLAMP; + cfg.maximum_lod = (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) ? + cfg.minimum_lod + 1 : + FIXED_16(cso->max_lod, false); - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: - return MALI_WRAP_MIRRORED_CLAMP_TO_EDGE; + cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); + cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); + cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); - case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: - return MALI_WRAP_MIRRORED_CLAMP_TO_BORDER; + cfg.compare_function = panfrost_sampler_compare_func(cso); + cfg.seamless_cube_map = cso->seamless_cube_map; - default: - unreachable("Invalid wrap"); + cfg.border_color_r = cso->border_color.f[0]; + cfg.border_color_g = cso->border_color.f[1]; + cfg.border_color_b = cso->border_color.f[2]; + cfg.border_color_a = cso->border_color.f[3]; } } -void panfrost_sampler_desc_init(const struct pipe_sampler_state *cso, - struct mali_sampler_descriptor *hw) -{ - unsigned func = panfrost_translate_compare_func(cso->compare_func); - bool min_nearest = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST; - bool mag_nearest = cso->mag_img_filter == PIPE_TEX_FILTER_NEAREST; - bool mip_linear = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR; - unsigned min_filter = min_nearest ? MALI_SAMP_MIN_NEAREST : 0; - unsigned mag_filter = mag_nearest ? MALI_SAMP_MAG_NEAREST : 0; - unsigned mip_filter = mip_linear ? - (MALI_SAMP_MIP_LINEAR_1 | MALI_SAMP_MIP_LINEAR_2) : 0; - unsigned normalized = cso->normalized_coords ? MALI_SAMP_NORM_COORDS : 0; - - *hw = (struct mali_sampler_descriptor) { - .filter_mode = min_filter | mag_filter | mip_filter | - normalized, - .wrap_s = translate_tex_wrap(cso->wrap_s), - .wrap_t = translate_tex_wrap(cso->wrap_t), - .wrap_r = translate_tex_wrap(cso->wrap_r), - .compare_func = panfrost_flip_compare_func(func), - .border_color = { - cso->border_color.f[0], - cso->border_color.f[1], - cso->border_color.f[2], - cso->border_color.f[3] - }, - .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */ - .max_lod = FIXED_16(cso->max_lod, false), - .lod_bias = FIXED_16(cso->lod_bias, true), /* can be negative */ - .seamless_cube_map = cso->seamless_cube_map, - }; - - /* If necessary, we disable mipmapping in the sampler descriptor by - * clamping the LOD as tight as possible (from 0 to epsilon, - * essentially -- remember these are fixed point numbers, so - * epsilon=1/256) */ - - if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) - hw->max_lod = hw->min_lod + 1; -} - void panfrost_sampler_desc_init_bifrost(const struct pipe_sampler_state *cso, - struct bifrost_sampler_descriptor *hw) + struct mali_bifrost_sampler_packed *hw) { - *hw = (struct bifrost_sampler_descriptor) { - .unk1 = 0x1, - .wrap_s = translate_tex_wrap(cso->wrap_s), - .wrap_t = translate_tex_wrap(cso->wrap_t), - .wrap_r = translate_tex_wrap(cso->wrap_r), - .unk8 = 0x8, - .min_filter = cso->min_img_filter == PIPE_TEX_FILTER_NEAREST, - .norm_coords = cso->normalized_coords, - .mip_filter = cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR, - .mag_filter = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR, - .min_lod = FIXED_16(cso->min_lod, false), /* clamp at 0 */ - .max_lod = FIXED_16(cso->max_lod, false), - }; - - /* If necessary, we disable mipmapping in the sampler descriptor by - * clamping the LOD as tight as possible (from 0 to epsilon, - * essentially -- remember these are fixed point numbers, so - * epsilon=1/256) */ - - if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_NONE) - hw->max_lod = hw->min_lod + 1; -} - -static void -panfrost_make_stencil_state(const struct pipe_stencil_state *in, - struct mali_stencil_test *out) -{ - out->ref = 0; /* Gallium gets it from elsewhere */ - - out->mask = in->valuemask; - out->func = panfrost_translate_compare_func(in->func); - out->sfail = panfrost_translate_stencil_op(in->fail_op); - out->dpfail = panfrost_translate_stencil_op(in->zfail_op); - out->dppass = panfrost_translate_stencil_op(in->zpass_op); + pan_pack(hw, BIFROST_SAMPLER, cfg) { + cfg.magnify_linear = cso->mag_img_filter == PIPE_TEX_FILTER_LINEAR; + cfg.minify_linear = cso->min_img_filter == PIPE_TEX_FILTER_LINEAR; + cfg.mipmap_mode = pan_pipe_to_mipmode(cso->min_mip_filter); + cfg.normalized_coordinates = cso->normalized_coords; + + cfg.lod_bias = FIXED_16(cso->lod_bias, true); + cfg.minimum_lod = FIXED_16(cso->min_lod, false); + cfg.maximum_lod = FIXED_16(cso->max_lod, false); + + cfg.wrap_mode_s = translate_tex_wrap(cso->wrap_s); + cfg.wrap_mode_t = translate_tex_wrap(cso->wrap_t); + cfg.wrap_mode_r = translate_tex_wrap(cso->wrap_r); + + cfg.compare_function = panfrost_sampler_compare_func(cso); + cfg.seamless_cube_map = cso->seamless_cube_map; + } } static void panfrost_frag_meta_rasterizer_update(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta) { - if (!ctx->rasterizer) { - SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, true); - SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, false); - fragmeta->depth_units = 0.0f; - fragmeta->depth_factor = 0.0f; - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, false); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, false); - return; - } + struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; - bool msaa = ctx->rasterizer->base.multisample; + bool msaa = rast->multisample; /* TODO: Sample size */ SET_BIT(fragmeta->unknown2_3, MALI_HAS_MSAA, msaa); SET_BIT(fragmeta->unknown2_4, MALI_NO_MSAA, !msaa); - fragmeta->depth_units = ctx->rasterizer->base.offset_units * 2.0f; - fragmeta->depth_factor = ctx->rasterizer->base.offset_scale; + + struct panfrost_shader_state *fs; + fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + + /* EXT_shader_framebuffer_fetch requires the shader to be run + * per-sample when outputs are read. */ + bool per_sample = ctx->min_samples > 1 || fs->outputs_read; + SET_BIT(fragmeta->unknown2_3, MALI_PER_SAMPLE, msaa && per_sample); + + fragmeta->depth_units = rast->offset_units * 2.0f; + fragmeta->depth_factor = rast->offset_scale; /* XXX: Which bit is which? Does this maybe allow offseting not-tri? */ - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, - ctx->rasterizer->base.offset_tri); - SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, - ctx->rasterizer->base.offset_tri); + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_A, rast->offset_tri); + SET_BIT(fragmeta->unknown2_4, MALI_DEPTH_RANGE_B, rast->offset_tri); + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_NEAR, rast->depth_clip_near); + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_CLIP_FAR, rast->depth_clip_far); } static void panfrost_frag_meta_zsa_update(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta) { - const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil; - int zfunc = PIPE_FUNC_ALWAYS; - - if (!zsa) { - struct pipe_stencil_state default_stencil = { - .enabled = 0, - .func = PIPE_FUNC_ALWAYS, - .fail_op = MALI_STENCIL_KEEP, - .zfail_op = MALI_STENCIL_KEEP, - .zpass_op = MALI_STENCIL_KEEP, - .writemask = 0xFF, - .valuemask = 0xFF - }; - - panfrost_make_stencil_state(&default_stencil, - &fragmeta->stencil_front); - fragmeta->stencil_mask_front = default_stencil.writemask; - fragmeta->stencil_back = fragmeta->stencil_front; - fragmeta->stencil_mask_back = default_stencil.writemask; - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, false); - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, false); - } else { - SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, - zsa->stencil[0].enabled); - panfrost_make_stencil_state(&zsa->stencil[0], - &fragmeta->stencil_front); - fragmeta->stencil_mask_front = zsa->stencil[0].writemask; - fragmeta->stencil_front.ref = ctx->stencil_ref.ref_value[0]; - - /* If back-stencil is not enabled, use the front values */ - - if (zsa->stencil[1].enabled) { - panfrost_make_stencil_state(&zsa->stencil[1], - &fragmeta->stencil_back); - fragmeta->stencil_mask_back = zsa->stencil[1].writemask; - fragmeta->stencil_back.ref = ctx->stencil_ref.ref_value[1]; - } else { - fragmeta->stencil_back = fragmeta->stencil_front; - fragmeta->stencil_mask_back = fragmeta->stencil_mask_front; - fragmeta->stencil_back.ref = fragmeta->stencil_front.ref; - } + const struct panfrost_zsa_state *so = ctx->depth_stencil; - if (zsa->depth.enabled) - zfunc = zsa->depth.func; + SET_BIT(fragmeta->unknown2_4, MALI_STENCIL_TEST, + so->base.stencil[0].enabled); - /* Depth state (TODO: Refactor) */ + fragmeta->stencil_mask_front = so->stencil_mask_front; + fragmeta->stencil_mask_back = so->stencil_mask_back; - SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, - zsa->depth.writemask); - } + /* Bottom bits for stencil ref, exactly one word */ + fragmeta->stencil_front.opaque[0] = so->stencil_front.opaque[0] | ctx->stencil_ref.ref_value[0]; + + /* If back-stencil is not enabled, use the front values */ + + if (so->base.stencil[1].enabled) + fragmeta->stencil_back.opaque[0] = so->stencil_back.opaque[0] | ctx->stencil_ref.ref_value[1]; + else + fragmeta->stencil_back = fragmeta->stencil_front; + + SET_BIT(fragmeta->unknown2_3, MALI_DEPTH_WRITEMASK, + so->base.depth.writemask); fragmeta->unknown2_3 &= ~MALI_DEPTH_FUNC_MASK; - fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func(zfunc)); + fragmeta->unknown2_3 |= MALI_DEPTH_FUNC(panfrost_translate_compare_func( + so->base.depth.enabled ? so->base.depth.func : PIPE_FUNC_ALWAYS)); } static bool @@ -650,8 +540,10 @@ panfrost_fs_required( static void panfrost_frag_meta_blend_update(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta, - void *rts) + void *rts, + struct panfrost_blend_final *blend) { + struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); const struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_state *fs; fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); @@ -660,16 +552,11 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, (dev->quirks & MIDGARD_SFBD) && ctx->blend && !ctx->blend->base.dither); - /* Get blending setup */ - unsigned rt_count = MAX2(ctx->pipe_framebuffer.nr_cbufs, 1); - - struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - unsigned shader_offset = 0; - struct panfrost_bo *shader_bo = NULL; + SET_BIT(fragmeta->unknown2_4, MALI_ALPHA_TO_COVERAGE, + ctx->blend->base.alpha_to_coverage); - for (unsigned c = 0; c < rt_count; ++c) - blend[c] = panfrost_get_blend_for_context(ctx, c, &shader_bo, - &shader_offset); + /* Get blending setup */ + unsigned rt_count = ctx->pipe_framebuffer.nr_cbufs; /* Disable shader execution if we can */ if (dev->quirks & MIDGARD_SHADERLESS @@ -705,7 +592,7 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, fragmeta->blend.shader = 0; - for (signed rt = (rt_count - 1); rt >= 0; --rt) { + for (signed rt = ((signed) rt_count - 1); rt >= 0; --rt) { if (!blend[rt].is_shader) continue; @@ -730,6 +617,8 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, SET_BIT(fragmeta->unknown2_3, MALI_CAN_DISCARD, !blend[0].no_blending || fs->can_discard); + + batch->draws |= PIPE_CLEAR_COLOR0; return; } @@ -745,15 +634,22 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, /* Additional blend descriptor tacked on for jobs using MFBD */ + struct bifrost_blend_rt *brts = rts; + struct midgard_blend_rt *mrts = rts; + + /* Disable blending for depth-only on Bifrost */ + + if (rt_count == 0 && dev->quirks & IS_BIFROST) + brts[0].unk2 = 0x3; + for (unsigned i = 0; i < rt_count; ++i) { unsigned flags = 0; - if (ctx->pipe_framebuffer.nr_cbufs > i && !blend[i].no_colour) { + if (!blend[i].no_colour) { flags = 0x200; + batch->draws |= (PIPE_CLEAR_COLOR0 << i); - bool is_srgb = (ctx->pipe_framebuffer.nr_cbufs > i) && - (ctx->pipe_framebuffer.cbufs[i]) && - util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); + bool is_srgb = util_format_is_srgb(ctx->pipe_framebuffer.cbufs[i]->format); SET_BIT(flags, MALI_BLEND_MRT_SHADER, blend[i].is_shader); SET_BIT(flags, MALI_BLEND_LOAD_TIB, !blend[i].no_blending); @@ -762,8 +658,6 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, } if (dev->quirks & IS_BIFROST) { - struct bifrost_blend_rt *brts = rts; - brts[i].flags = flags; if (blend[i].is_shader) { @@ -775,7 +669,7 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, (fs->bo->gpu & (0xffffffffull << 32))); brts[i].shader = blend[i].shader.gpu; brts[i].unk2 = 0x0; - } else if (ctx->pipe_framebuffer.nr_cbufs > i) { + } else { enum pipe_format format = ctx->pipe_framebuffer.cbufs[i]->format; const struct util_format_description *format_desc; format_desc = util_format_description(format); @@ -793,14 +687,9 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, * blending. */ brts[i].unk2 = blend[i].no_blending ? 0x19 : 0x1a; - brts[i].shader_type = fs->blend_types[i]; - } else { - /* Dummy attachment for depth-only */ - brts[i].unk2 = 0x3; brts[i].shader_type = fs->blend_types[i]; } } else { - struct midgard_blend_rt *mrts = rts; mrts[i].flags = flags; if (blend[i].is_shader) { @@ -816,15 +705,18 @@ panfrost_frag_meta_blend_update(struct panfrost_context *ctx, static void panfrost_frag_shader_meta_init(struct panfrost_context *ctx, struct mali_shader_meta *fragmeta, - void *rts) + void *rts, + struct panfrost_blend_final *blend) { const struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_state *fs; fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - fragmeta->alpha_coverage = ~MALI_ALPHA_COVERAGE(0.000000); - fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x3010; + bool msaa = ctx->rasterizer->base.multisample; + fragmeta->coverage_mask = msaa ? ctx->sample_mask : ~0; + + fragmeta->unknown2_3 = MALI_DEPTH_FUNC(MALI_FUNC_ALWAYS) | 0x10; fragmeta->unknown2_4 = 0x4e0; /* unknown2_4 has 0x10 bit set on T6XX and T720. We don't know why this @@ -839,10 +731,12 @@ panfrost_frag_shader_meta_init(struct panfrost_context *ctx, /* TODO */ } else { /* Depending on whether it's legal to in the given shader, we try to - * enable early-z testing (or forward-pixel kill?) */ + * enable early-z testing. TODO: respect e-z force */ SET_BIT(fragmeta->midgard1.flags_lo, MALI_EARLY_Z, - !fs->can_discard && !fs->writes_depth); + !fs->can_discard && !fs->writes_global && + !fs->writes_depth && !fs->writes_stencil && + !ctx->blend->base.alpha_to_coverage); /* Add the writes Z/S flags if needed. */ SET_BIT(fragmeta->midgard1.flags_lo, MALI_WRITES_Z, fs->writes_depth); @@ -854,18 +748,24 @@ panfrost_frag_shader_meta_init(struct panfrost_context *ctx, SET_BIT(fragmeta->midgard1.flags_lo, MALI_HELPER_INVOCATIONS, fs->helper_invocations); - const struct pipe_depth_stencil_alpha_state *zsa = ctx->depth_stencil; + /* If discard is enabled, which bit we set to convey this + * depends on if depth/stencil is used for the draw or not. + * Just one of depth OR stencil is enough to trigger this. */ - bool depth_enabled = fs->writes_depth || - (zsa && zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS); + const struct pipe_depth_stencil_alpha_state *zsa = &ctx->depth_stencil->base; + bool zs_enabled = + fs->writes_depth || fs->writes_stencil || + (zsa->depth.enabled && zsa->depth.func != PIPE_FUNC_ALWAYS) || + zsa->stencil[0].enabled; - SET_BIT(fragmeta->midgard1.flags_lo, 0x400, !depth_enabled && fs->can_discard); - SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, depth_enabled && fs->can_discard); + SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_TILEBUFFER, + fs->outputs_read || (!zs_enabled && fs->can_discard)); + SET_BIT(fragmeta->midgard1.flags_lo, MALI_READS_ZS, zs_enabled && fs->can_discard); } panfrost_frag_meta_rasterizer_update(ctx, fragmeta); panfrost_frag_meta_zsa_update(ctx, fragmeta); - panfrost_frag_meta_blend_update(ctx, fragmeta, rts); + panfrost_frag_meta_blend_update(ctx, fragmeta, rts, blend); } void @@ -913,9 +813,14 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, if (rt_size) rts = rzalloc_size(ctx, rt_size * rt_count); - panfrost_frag_shader_meta_init(ctx, &meta, rts); + struct panfrost_blend_final blend[PIPE_MAX_COLOR_BUFS]; - xfer = panfrost_allocate_transient(batch, desc_size); + for (unsigned c = 0; c < ctx->pipe_framebuffer.nr_cbufs; ++c) + blend[c] = panfrost_get_blend_for_context(ctx, c); + + panfrost_frag_shader_meta_init(ctx, &meta, rts, blend); + + xfer = panfrost_pool_alloc_aligned(&batch->pool, desc_size, sizeof(meta)); memcpy(xfer.cpu, &meta, sizeof(meta)); memcpy(xfer.cpu + sizeof(meta), rts, rt_size * rt_count); @@ -925,127 +830,62 @@ panfrost_emit_shader_meta(struct panfrost_batch *batch, shader_ptr = xfer.gpu; } else { - shader_ptr = panfrost_upload_transient(batch, &meta, + shader_ptr = panfrost_pool_upload(&batch->pool, &meta, sizeof(meta)); } postfix->shader = shader_ptr; } -static void -panfrost_mali_viewport_init(struct panfrost_context *ctx, - struct mali_viewport *mvp) +void +panfrost_emit_viewport(struct panfrost_batch *batch, + struct mali_vertex_tiler_postfix *tiler_postfix) { + struct panfrost_context *ctx = batch->ctx; const struct pipe_viewport_state *vp = &ctx->pipe_viewport; - - /* Clip bounds are encoded as floats. The viewport itself is encoded as - * (somewhat) asymmetric ints. */ - const struct pipe_scissor_state *ss = &ctx->scissor; + const struct pipe_rasterizer_state *rast = &ctx->rasterizer->base; + const struct pipe_framebuffer_state *fb = &ctx->pipe_framebuffer; - memset(mvp, 0, sizeof(*mvp)); - - /* By default, do no viewport clipping, i.e. clip to (-inf, inf) in - * each direction. Clipping to the viewport in theory should work, but - * in practice causes issues when we're not explicitly trying to - * scissor */ - - *mvp = (struct mali_viewport) { - .clip_minx = -INFINITY, - .clip_miny = -INFINITY, - .clip_maxx = INFINITY, - .clip_maxy = INFINITY, - }; - - /* Always scissor to the viewport by default. */ + /* Derive min/max from translate/scale. Note since |x| >= 0 by + * definition, we have that -|x| <= |x| hence translate - |scale| <= + * translate + |scale|, so the ordering is correct here. */ float vp_minx = (int) (vp->translate[0] - fabsf(vp->scale[0])); float vp_maxx = (int) (vp->translate[0] + fabsf(vp->scale[0])); - float vp_miny = (int) (vp->translate[1] - fabsf(vp->scale[1])); float vp_maxy = (int) (vp->translate[1] + fabsf(vp->scale[1])); - float minz = (vp->translate[2] - fabsf(vp->scale[2])); float maxz = (vp->translate[2] + fabsf(vp->scale[2])); - /* Apply the scissor test */ + /* Scissor to the intersection of viewport and to the scissor, clamped + * to the framebuffer */ - unsigned minx, miny, maxx, maxy; + unsigned minx = MIN2(fb->width, vp_minx); + unsigned maxx = MIN2(fb->width, vp_maxx); + unsigned miny = MIN2(fb->height, vp_miny); + unsigned maxy = MIN2(fb->height, vp_maxy); - if (ss && ctx->rasterizer && ctx->rasterizer->base.scissor) { - minx = MAX2(ss->minx, vp_minx); - miny = MAX2(ss->miny, vp_miny); - maxx = MIN2(ss->maxx, vp_maxx); - maxy = MIN2(ss->maxy, vp_maxy); - } else { - minx = vp_minx; - miny = vp_miny; - maxx = vp_maxx; - maxy = vp_maxy; + if (ss && rast->scissor) { + minx = MAX2(ss->minx, minx); + miny = MAX2(ss->miny, miny); + maxx = MIN2(ss->maxx, maxx); + maxy = MIN2(ss->maxy, maxy); } - /* Hardware needs the min/max to be strictly ordered, so flip if we - * need to. The viewport transformation in the vertex shader will - * handle the negatives if we don't */ + struct panfrost_transfer T = panfrost_pool_alloc(&batch->pool, MALI_VIEWPORT_LENGTH); - if (miny > maxy) { - unsigned temp = miny; - miny = maxy; - maxy = temp; - } - - if (minx > maxx) { - unsigned temp = minx; - minx = maxx; - maxx = temp; - } + pan_pack(T.cpu, VIEWPORT, cfg) { + cfg.scissor_minimum_x = minx; + cfg.scissor_minimum_y = miny; + cfg.scissor_maximum_x = maxx - 1; + cfg.scissor_maximum_y = maxy - 1; - if (minz > maxz) { - float temp = minz; - minz = maxz; - maxz = temp; + cfg.minimum_z = rast->depth_clip_near ? minz : -INFINITY; + cfg.maximum_z = rast->depth_clip_far ? maxz : INFINITY; } - /* Clamp to the framebuffer size as a last check */ - - minx = MIN2(ctx->pipe_framebuffer.width, minx); - maxx = MIN2(ctx->pipe_framebuffer.width, maxx); - - miny = MIN2(ctx->pipe_framebuffer.height, miny); - maxy = MIN2(ctx->pipe_framebuffer.height, maxy); - - /* Upload */ - - mvp->viewport0[0] = minx; - mvp->viewport1[0] = MALI_POSITIVE(maxx); - - mvp->viewport0[1] = miny; - mvp->viewport1[1] = MALI_POSITIVE(maxy); - - mvp->clip_minz = minz; - mvp->clip_maxz = maxz; -} - -void -panfrost_emit_viewport(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *tiler_postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct mali_viewport mvp; - - panfrost_mali_viewport_init(batch->ctx, &mvp); - - /* Update the job, unless we're doing wallpapering (whose lack of - * scissor we can ignore, since if we "miss" a tile of wallpaper, it'll - * just... be faster :) */ - - if (!ctx->wallpaper_batch) - panfrost_batch_union_scissor(batch, mvp.viewport0[0], - mvp.viewport0[1], - mvp.viewport1[0] + 1, - mvp.viewport1[1] + 1); - - tiler_postfix->viewport = panfrost_upload_transient(batch, &mvp, - sizeof(mvp)); + tiler_postfix->viewport = T.gpu; + panfrost_batch_union_scissor(batch, minx, miny, maxx, maxy); } static mali_ptr @@ -1067,10 +907,10 @@ panfrost_map_constant_buffer_gpu(struct panfrost_batch *batch, * PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT */ return rsrc->bo->gpu + cb->buffer_offset; } else if (cb->user_buffer) { - return panfrost_upload_transient(batch, + return panfrost_pool_upload_aligned(&batch->pool, cb->user_buffer + cb->buffer_offset, - cb->buffer_size); + cb->buffer_size, 16); } else { unreachable("No constant buffer"); } @@ -1272,8 +1112,8 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, size_t sys_size = sizeof(float) * 4 * ss->sysval_count; size_t uniform_size = has_uniforms ? (buf->cb[0].buffer_size) : 0; size_t size = sys_size + uniform_size; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, - size); + struct panfrost_transfer transfer = + panfrost_pool_alloc_aligned(&batch->pool, size, 16); /* Upload sysvals requested by the shader */ panfrost_upload_sysvals(batch, transfer.cpu, ss, stage); @@ -1290,12 +1130,23 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, unsigned ubo_count = panfrost_ubo_count(ctx, stage); assert(ubo_count >= 1); - size_t sz = sizeof(uint64_t) * ubo_count; - uint64_t ubos[PAN_MAX_CONST_BUFFERS]; - int uniform_count = ss->uniform_count; + size_t sz = MALI_UNIFORM_BUFFER_LENGTH * ubo_count; + struct panfrost_transfer ubos = + panfrost_pool_alloc_aligned(&batch->pool, sz, + MALI_UNIFORM_BUFFER_LENGTH); + + uint64_t *ubo_ptr = (uint64_t *) ubos.cpu; /* Upload uniforms as a UBO */ - ubos[0] = MALI_MAKE_UBO(2 + uniform_count, transfer.gpu); + + if (ss->uniform_count) { + pan_pack(ubo_ptr, UNIFORM_BUFFER, cfg) { + cfg.entries = ss->uniform_count; + cfg.pointer = transfer.gpu; + } + } else { + *ubo_ptr = 0; + } /* The rest are honest-to-goodness UBOs */ @@ -1305,22 +1156,19 @@ panfrost_emit_const_buf(struct panfrost_batch *batch, bool empty = usz == 0; if (!enabled || empty) { - /* Stub out disabled UBOs to catch accesses */ - ubos[ubo] = MALI_MAKE_UBO(0, 0xDEAD0000); + ubo_ptr[ubo] = 0; continue; } - mali_ptr gpu = panfrost_map_constant_buffer_gpu(batch, stage, - buf, ubo); - - unsigned bytes_per_field = 16; - unsigned aligned = ALIGN_POT(usz, bytes_per_field); - ubos[ubo] = MALI_MAKE_UBO(aligned / bytes_per_field, gpu); + pan_pack(ubo_ptr + ubo, UNIFORM_BUFFER, cfg) { + cfg.entries = DIV_ROUND_UP(usz, 16); + cfg.pointer = panfrost_map_constant_buffer_gpu(batch, + stage, buf, ubo); + } } - mali_ptr ubufs = panfrost_upload_transient(batch, ubos, sz); postfix->uniforms = transfer.gpu; - postfix->uniform_buffers = ubufs; + postfix->uniform_buffers = ubos.gpu; buf->dirty_mask = 0; } @@ -1331,28 +1179,30 @@ panfrost_emit_shared_memory(struct panfrost_batch *batch, struct midgard_payload_vertex_tiler *vtp) { struct panfrost_context *ctx = batch->ctx; + struct panfrost_device *dev = pan_device(ctx->base.screen); struct panfrost_shader_variants *all = ctx->shader[PIPE_SHADER_COMPUTE]; struct panfrost_shader_state *ss = &all->variants[all->active_variant]; unsigned single_size = util_next_power_of_two(MAX2(ss->shared_size, 128)); - unsigned shared_size = single_size * info->grid[0] * info->grid[1] * - info->grid[2] * 4; + + unsigned log2_instances = + util_logbase2_ceil(info->grid[0]) + + util_logbase2_ceil(info->grid[1]) + + util_logbase2_ceil(info->grid[2]); + + unsigned shared_size = single_size * (1 << log2_instances) * dev->core_count; struct panfrost_bo *bo = panfrost_batch_get_shared_memory(batch, shared_size, 1); struct mali_shared_memory shared = { .shared_memory = bo->gpu, - .shared_workgroup_count = - util_logbase2_ceil(info->grid[0]) + - util_logbase2_ceil(info->grid[1]) + - util_logbase2_ceil(info->grid[2]), - .shared_unk1 = 0x2, - .shared_shift = util_logbase2(single_size) - 1 + .shared_workgroup_count = log2_instances, + .shared_shift = util_logbase2(single_size) + 1 }; - vtp->postfix.shared_memory = panfrost_upload_transient(batch, &shared, - sizeof(shared)); + vtp->postfix.shared_memory = panfrost_pool_upload_aligned(&batch->pool, &shared, + sizeof(shared), 64); } static mali_ptr @@ -1372,11 +1222,23 @@ panfrost_get_tex_desc(struct panfrost_batch *batch, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | panfrost_bo_access_for_stage(st)); - panfrost_batch_add_bo(batch, view->midgard_bo, + panfrost_batch_add_bo(batch, view->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | panfrost_bo_access_for_stage(st)); - return view->midgard_bo->gpu; + return view->bo->gpu; +} + +static void +panfrost_update_sampler_view(struct panfrost_sampler_view *view, + struct pipe_context *pctx) +{ + struct panfrost_resource *rsrc = pan_resource(view->base.texture); + if (view->texture_bo != rsrc->bo->gpu || + view->modifier != rsrc->modifier) { + panfrost_bo_unreference(view->bo); + panfrost_create_sampler_view_bo(view, pctx, &rsrc->base); + } } void @@ -1391,46 +1253,50 @@ panfrost_emit_texture_descriptors(struct panfrost_batch *batch, return; if (device->quirks & IS_BIFROST) { - struct bifrost_texture_descriptor *descriptors; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_BIFROST_TEXTURE_LENGTH * + ctx->sampler_view_count[stage], + MALI_BIFROST_TEXTURE_LENGTH); - descriptors = malloc(sizeof(struct bifrost_texture_descriptor) * - ctx->sampler_view_count[stage]); + struct mali_bifrost_texture_packed *out = + (struct mali_bifrost_texture_packed *) T.cpu; for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; struct pipe_sampler_view *pview = &view->base; struct panfrost_resource *rsrc = pan_resource(pview->texture); + panfrost_update_sampler_view(view, &ctx->base); + out[i] = view->bifrost_descriptor; + /* Add the BOs to the job so they are retained until the job is done. */ panfrost_batch_add_bo(batch, rsrc->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | panfrost_bo_access_for_stage(stage)); - panfrost_batch_add_bo(batch, view->bifrost_bo, + panfrost_batch_add_bo(batch, view->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | panfrost_bo_access_for_stage(stage)); - - memcpy(&descriptors[i], view->bifrost_descriptor, sizeof(*view->bifrost_descriptor)); } - postfix->textures = panfrost_upload_transient(batch, - descriptors, - sizeof(struct bifrost_texture_descriptor) * - ctx->sampler_view_count[stage]); - - free(descriptors); + postfix->textures = T.gpu; } else { uint64_t trampolines[PIPE_MAX_SHADER_SAMPLER_VIEWS]; - for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) - trampolines[i] = panfrost_get_tex_desc(batch, stage, - ctx->sampler_views[stage][i]); + for (int i = 0; i < ctx->sampler_view_count[stage]; ++i) { + struct panfrost_sampler_view *view = ctx->sampler_views[stage][i]; - postfix->textures = panfrost_upload_transient(batch, + panfrost_update_sampler_view(view, &ctx->base); + + trampolines[i] = panfrost_get_tex_desc(batch, stage, view); + } + + postfix->textures = panfrost_pool_upload_aligned(&batch->pool, trampolines, sizeof(uint64_t) * - ctx->sampler_view_count[stage]); + ctx->sampler_view_count[stage], + sizeof(uint64_t)); } } @@ -1440,79 +1306,65 @@ panfrost_emit_sampler_descriptors(struct panfrost_batch *batch, struct mali_vertex_tiler_postfix *postfix) { struct panfrost_context *ctx = batch->ctx; - struct panfrost_device *device = pan_device(ctx->base.screen); if (!ctx->sampler_count[stage]) return; - if (device->quirks & IS_BIFROST) { - size_t desc_size = sizeof(struct bifrost_sampler_descriptor); - size_t transfer_size = desc_size * ctx->sampler_count[stage]; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, - transfer_size); - struct bifrost_sampler_descriptor *desc = (struct bifrost_sampler_descriptor *)transfer.cpu; + size_t desc_size = MALI_BIFROST_SAMPLER_LENGTH; + assert(MALI_BIFROST_SAMPLER_LENGTH == MALI_MIDGARD_SAMPLER_LENGTH); - for (int i = 0; i < ctx->sampler_count[stage]; ++i) - desc[i] = ctx->samplers[stage][i]->bifrost_hw; + size_t sz = desc_size * ctx->sampler_count[stage]; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, sz, desc_size); + struct mali_midgard_sampler_packed *out = (struct mali_midgard_sampler_packed *) T.cpu; - postfix->sampler_descriptor = transfer.gpu; - } else { - size_t desc_size = sizeof(struct mali_sampler_descriptor); - size_t transfer_size = desc_size * ctx->sampler_count[stage]; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, - transfer_size); - struct mali_sampler_descriptor *desc = (struct mali_sampler_descriptor *)transfer.cpu; + for (unsigned i = 0; i < ctx->sampler_count[stage]; ++i) + out[i] = ctx->samplers[stage][i]->hw; - for (int i = 0; i < ctx->sampler_count[stage]; ++i) - desc[i] = ctx->samplers[stage][i]->midgard_hw; - - postfix->sampler_descriptor = transfer.gpu; - } + postfix->sampler_descriptor = T.gpu; } void -panfrost_emit_vertex_attr_meta(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *vertex_postfix) +panfrost_emit_vertex_data(struct panfrost_batch *batch, + struct mali_vertex_tiler_postfix *vertex_postfix) { struct panfrost_context *ctx = batch->ctx; + struct panfrost_vertex_state *so = ctx->vertex; + struct panfrost_shader_state *vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); - if (!ctx->vertex) - return; + unsigned instance_shift = vertex_postfix->instance_shift; + unsigned instance_odd = vertex_postfix->instance_odd; - struct panfrost_vertex_state *so = ctx->vertex; + /* Worst case: everything is NPOT, which is only possible if instancing + * is enabled. Otherwise single record is gauranteed */ + bool could_npot = instance_shift || instance_odd; - panfrost_vertex_state_upd_attr_offs(ctx, vertex_postfix); - vertex_postfix->attribute_meta = panfrost_upload_transient(batch, so->hw, - sizeof(*so->hw) * - PAN_MAX_ATTRIBUTE); -} + struct panfrost_transfer S = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * vs->attribute_count * + (could_npot ? 2 : 1), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); -void -panfrost_emit_vertex_data(struct panfrost_batch *batch, - struct mali_vertex_tiler_postfix *vertex_postfix) -{ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_vertex_state *so = ctx->vertex; + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_LENGTH * vs->attribute_count, + MALI_ATTRIBUTE_LENGTH); + + struct mali_attribute_buffer_packed *bufs = + (struct mali_attribute_buffer_packed *) S.cpu; - /* Staged mali_attr, and index into them. i =/= k, depending on the - * vertex buffer mask and instancing. Twice as much room is allocated, - * for a worst case of NPOT_DIVIDEs which take up extra slot */ - union mali_attr attrs[PIPE_MAX_ATTRIBS * 2]; + struct mali_attribute_packed *out = + (struct mali_attribute_packed *) T.cpu; + + unsigned attrib_to_buffer[PIPE_MAX_ATTRIBS] = { 0 }; unsigned k = 0; for (unsigned i = 0; i < so->num_elements; ++i) { - /* We map a mali_attr to be 1:1 with the mali_attr_meta, which + /* We map buffers 1:1 with the attributes, which * means duplicating some vertex buffers (who cares? aside from * maybe some caching implications but I somehow doubt that * matters) */ struct pipe_vertex_element *elem = &so->pipe[i]; unsigned vbi = elem->vertex_buffer_index; - - /* The exception to 1:1 mapping is that we can have multiple - * entries (NPOT divisors), so we fixup anyways */ - - so->hw[i].index = k; + attrib_to_buffer[i] = k; if (!(ctx->vb_mask & (1 << vbi))) continue; @@ -1524,107 +1376,172 @@ panfrost_emit_vertex_data(struct panfrost_batch *batch, if (!rsrc) continue; - /* Align to 64 bytes by masking off the lower bits. This - * will be adjusted back when we fixup the src_offset in - * mali_attr_meta */ - - mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; - mali_ptr addr = raw_addr & ~63; - unsigned chopped_addr = raw_addr - addr; - /* Add a dependency of the batch on the vertex buffer */ panfrost_batch_add_bo(batch, rsrc->bo, PAN_BO_ACCESS_SHARED | PAN_BO_ACCESS_READ | PAN_BO_ACCESS_VERTEX_TILER); - /* Set common fields */ - attrs[k].elements = addr; - attrs[k].stride = buf->stride; + /* Mask off lower bits, see offset fixup below */ + mali_ptr raw_addr = rsrc->bo->gpu + buf->buffer_offset; + mali_ptr addr = raw_addr & ~63; /* Since we advanced the base pointer, we shrink the buffer - * size */ - attrs[k].size = rsrc->base.width0 - buf->buffer_offset; + * size, but add the offset we subtracted */ + unsigned size = rsrc->base.width0 + (raw_addr - addr) + - buf->buffer_offset; - /* We need to add the extra size we masked off (for - * correctness) so the data doesn't get clamped away */ - attrs[k].size += chopped_addr; + /* When there is a divisor, the hardware-level divisor is + * the product of the instance divisor and the padded count */ + unsigned divisor = elem->instance_divisor; + unsigned hw_divisor = ctx->padded_count * divisor; + unsigned stride = buf->stride; - /* For non-instancing make sure we initialize */ - attrs[k].shift = attrs[k].extra_flags = 0; + /* If there's a divisor(=1) but no instancing, we want every + * attribute to be the same */ - /* Instancing uses a dramatically different code path than - * linear, so dispatch for the actual emission now that the - * common code is finished */ + if (divisor && ctx->instance_count == 1) + stride = 0; - unsigned divisor = elem->instance_divisor; + if (!divisor || ctx->instance_count <= 1) { + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + if (ctx->instance_count > 1) + cfg.type = MALI_ATTRIBUTE_TYPE_1D_MODULUS; + + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + cfg.divisor_r = instance_shift; + cfg.divisor_p = instance_odd; + } + } else if (util_is_power_of_two_or_zero(hw_divisor)) { + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + cfg.type = MALI_ATTRIBUTE_TYPE_1D_POT_DIVISOR; + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + cfg.divisor_r = __builtin_ctz(hw_divisor); + } - if (divisor && ctx->instance_count == 1) { - /* Silly corner case where there's a divisor(=1) but - * there's no legitimate instancing. So we want *every* - * attribute to be the same. So set stride to zero so - * we don't go anywhere. */ - - attrs[k].size = attrs[k].stride + chopped_addr; - attrs[k].stride = 0; - attrs[k++].elements |= MALI_ATTR_LINEAR; - } else if (ctx->instance_count <= 1) { - /* Normal, non-instanced attributes */ - attrs[k++].elements |= MALI_ATTR_LINEAR; } else { - unsigned instance_shift = vertex_postfix->instance_shift; - unsigned instance_odd = vertex_postfix->instance_odd; + unsigned shift = 0, extra_flags = 0; + + unsigned magic_divisor = + panfrost_compute_magic_divisor(hw_divisor, &shift, &extra_flags); - k += panfrost_vertex_instanced(ctx->padded_count, - instance_shift, - instance_odd, - divisor, &attrs[k]); + pan_pack(bufs + k, ATTRIBUTE_BUFFER, cfg) { + cfg.type = MALI_ATTRIBUTE_TYPE_1D_NPOT_DIVISOR; + cfg.pointer = addr; + cfg.stride = stride; + cfg.size = size; + + cfg.divisor_r = shift; + cfg.divisor_e = extra_flags; + } + + pan_pack(bufs + k + 1, ATTRIBUTE_BUFFER_CONTINUATION_NPOT, cfg) { + cfg.divisor_numerator = magic_divisor; + cfg.divisor = divisor; + } + + ++k; } + + ++k; } /* Add special gl_VertexID/gl_InstanceID buffers */ - panfrost_vertex_id(ctx->padded_count, &attrs[k]); - so->hw[PAN_VERTEX_ID].index = k++; - panfrost_instance_id(ctx->padded_count, &attrs[k]); - so->hw[PAN_INSTANCE_ID].index = k++; + if (unlikely(vs->attribute_count >= PAN_VERTEX_ID)) { + panfrost_vertex_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); - /* Upload whatever we emitted and go */ + pan_pack(out + PAN_VERTEX_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_VERTEX_ID]; + } + + panfrost_instance_id(ctx->padded_count, &bufs[k], ctx->instance_count > 1); + + pan_pack(out + PAN_INSTANCE_ID, ATTRIBUTE, cfg) { + cfg.buffer_index = k++; + cfg.format = so->formats[PAN_INSTANCE_ID]; + } + } + + /* Attribute addresses require 64-byte alignment, so let: + * + * base' = base & ~63 = base - (base & 63) + * offset' = offset + (base & 63) + * + * Since base' + offset' = base + offset, these are equivalent + * addressing modes and now base is 64 aligned. + */ + + unsigned start = vertex_postfix->offset_start; + + for (unsigned i = 0; i < so->num_elements; ++i) { + unsigned vbi = so->pipe[i].vertex_buffer_index; + struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; + + /* Adjust by the masked off bits of the offset. Make sure we + * read src_offset from so->hw (which is not GPU visible) + * rather than target (which is) due to caching effects */ + + unsigned src_offset = so->pipe[i].src_offset; - vertex_postfix->attributes = panfrost_upload_transient(batch, attrs, - k * sizeof(*attrs)); + /* BOs aligned to 4k so guaranteed aligned to 64 */ + src_offset += (buf->buffer_offset & 63); + + /* Also, somewhat obscurely per-instance data needs to be + * offset in response to a delayed start in an indexed draw */ + + if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) + src_offset -= buf->stride * start; + + pan_pack(out + i, ATTRIBUTE, cfg) { + cfg.buffer_index = attrib_to_buffer[i]; + cfg.format = so->formats[i]; + cfg.offset = src_offset; + } + } + + vertex_postfix->attributes = S.gpu; + vertex_postfix->attribute_meta = T.gpu; } static mali_ptr -panfrost_emit_varyings(struct panfrost_batch *batch, union mali_attr *slot, - unsigned stride, unsigned count) +panfrost_emit_varyings(struct panfrost_batch *batch, + struct mali_attribute_buffer_packed *slot, + unsigned stride, unsigned count) { - /* Fill out the descriptor */ - slot->stride = stride; - slot->size = stride * count; - slot->shift = slot->extra_flags = 0; + unsigned size = stride * count; + mali_ptr ptr = panfrost_pool_alloc_aligned(&batch->invisible_pool, size, 64).gpu; - struct panfrost_transfer transfer = panfrost_allocate_transient(batch, - slot->size); + pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { + cfg.stride = stride; + cfg.size = size; + cfg.pointer = ptr; + } - slot->elements = transfer.gpu | MALI_ATTR_LINEAR; + return ptr; +} - return transfer.gpu; +static unsigned +panfrost_streamout_offset(unsigned stride, unsigned offset, + struct pipe_stream_output_target *target) +{ + return (target->buffer_offset + (offset * stride * 4)) & 63; } static void -panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot, - unsigned stride, unsigned offset, unsigned count, +panfrost_emit_streamout(struct panfrost_batch *batch, + struct mali_attribute_buffer_packed *slot, + unsigned stride_words, unsigned offset, unsigned count, struct pipe_stream_output_target *target) { - /* Fill out the descriptor */ - slot->stride = stride * 4; - slot->shift = slot->extra_flags = 0; - + unsigned stride = stride_words * 4; unsigned max_size = target->buffer_size; - unsigned expected_size = slot->stride * count; - - slot->size = MIN2(max_size, expected_size); + unsigned expected_size = stride * count; /* Grab the BO and bind it to the batch */ struct panfrost_bo *bo = pan_resource(target->buffer)->bo; @@ -1638,58 +1555,13 @@ panfrost_emit_streamout(struct panfrost_batch *batch, union mali_attr *slot, PAN_BO_ACCESS_VERTEX_TILER | PAN_BO_ACCESS_FRAGMENT); - mali_ptr addr = bo->gpu + target->buffer_offset + (offset * slot->stride); - slot->elements = addr; -} - -/* Given a shader and buffer indices, link varying metadata together */ + /* We will have an offset applied to get alignment */ + mali_ptr addr = bo->gpu + target->buffer_offset + (offset * stride); -static bool -is_special_varying(gl_varying_slot loc) -{ - switch (loc) { - case VARYING_SLOT_POS: - case VARYING_SLOT_PSIZ: - case VARYING_SLOT_PNTC: - case VARYING_SLOT_FACE: - return true; - default: - return false; - } -} - -static void -panfrost_emit_varying_meta(void *outptr, struct panfrost_shader_state *ss, - signed general, signed gl_Position, - signed gl_PointSize, signed gl_PointCoord, - signed gl_FrontFacing) -{ - struct mali_attr_meta *out = (struct mali_attr_meta *) outptr; - - for (unsigned i = 0; i < ss->varying_count; ++i) { - gl_varying_slot location = ss->varyings_loc[i]; - int index = -1; - - switch (location) { - case VARYING_SLOT_POS: - index = gl_Position; - break; - case VARYING_SLOT_PSIZ: - index = gl_PointSize; - break; - case VARYING_SLOT_PNTC: - index = gl_PointCoord; - break; - case VARYING_SLOT_FACE: - index = gl_FrontFacing; - break; - default: - index = general; - break; - } - - assert(index >= 0); - out[i].index = index; + pan_pack(slot, ATTRIBUTE_BUFFER, cfg) { + cfg.pointer = (addr & ~63); + cfg.stride = stride; + cfg.size = MIN2(max_size, expected_size) + (addr & 63); } } @@ -1718,274 +1590,453 @@ pan_get_so(struct pipe_stream_output_info *info, gl_varying_slot loc) unreachable("Varying not captured"); } -void -panfrost_emit_varying_descriptor(struct panfrost_batch *batch, - unsigned vertex_count, - struct mali_vertex_tiler_postfix *vertex_postfix, - struct mali_vertex_tiler_postfix *tiler_postfix, - union midgard_primitive_size *primitive_size) +static unsigned +pan_varying_size(enum mali_format fmt) { - /* Load the shaders */ - struct panfrost_context *ctx = batch->ctx; - struct panfrost_device *device = pan_device(ctx->base.screen); - struct panfrost_shader_state *vs, *fs; - unsigned int num_gen_varyings = 0; - size_t vs_size, fs_size; + unsigned type = MALI_EXTRACT_TYPE(fmt); + unsigned chan = MALI_EXTRACT_CHANNELS(fmt); + unsigned bits = MALI_EXTRACT_BITS(fmt); + unsigned bpc = 0; - /* Allocate the varying descriptor */ + if (bits == MALI_CHANNEL_FLOAT) { + /* No doubles */ + bool fp16 = (type == MALI_FORMAT_SINT); + assert(fp16 || (type == MALI_FORMAT_UNORM)); - vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); - fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); - vs_size = sizeof(struct mali_attr_meta) * vs->varying_count; - fs_size = sizeof(struct mali_attr_meta) * fs->varying_count; + bpc = fp16 ? 2 : 4; + } else { + assert(type >= MALI_FORMAT_SNORM && type <= MALI_FORMAT_SINT); - struct panfrost_transfer trans = panfrost_allocate_transient(batch, - vs_size + - fs_size); + /* See the enums */ + bits = 1 << bits; + assert(bits >= 8); + bpc = bits / 8; + } - struct pipe_stream_output_info *so = &vs->stream_output; + return bpc * chan; +} - /* Check if this varying is linked by us. This is the case for - * general-purpose, non-captured varyings. If it is, link it. If it's - * not, use the provided stream out information to determine the - * offset, since it was already linked for us. */ +/* Indices for named (non-XFB) varyings that are present. These are packed + * tightly so they correspond to a bitfield present (P) indexed by (1 << + * PAN_VARY_*). This has the nice property that you can lookup the buffer index + * of a given special field given a shift S by: + * + * idx = popcount(P & ((1 << S) - 1)) + * + * That is... look at all of the varyings that come earlier and count them, the + * count is the new index since plus one. Likewise, the total number of special + * buffers required is simply popcount(P) + */ - for (unsigned i = 0; i < vs->varying_count; i++) { - gl_varying_slot loc = vs->varyings_loc[i]; +enum pan_special_varying { + PAN_VARY_GENERAL = 0, + PAN_VARY_POSITION = 1, + PAN_VARY_PSIZ = 2, + PAN_VARY_PNTCOORD = 3, + PAN_VARY_FACE = 4, + PAN_VARY_FRAGCOORD = 5, - bool special = is_special_varying(loc); - bool captured = ((vs->so_mask & (1ll << loc)) ? true : false); + /* Keep last */ + PAN_VARY_MAX, +}; - if (captured) { - struct pipe_stream_output *o = pan_get_so(so, loc); +/* Given a varying, figure out which index it correpsonds to */ - unsigned dst_offset = o->dst_offset * 4; /* dwords */ - vs->varyings[i].src_offset = dst_offset; - } else if (!special) { - vs->varyings[i].src_offset = 16 * (num_gen_varyings++); - } - } +static inline unsigned +pan_varying_index(unsigned present, enum pan_special_varying v) +{ + unsigned mask = (1 << v) - 1; + return util_bitcount(present & mask); +} - /* Conversely, we need to set src_offset for the captured varyings. - * Here, the layout is defined by the stream out info, not us */ +/* Get the base offset for XFB buffers, which by convention come after + * everything else. Wrapper function for semantic reasons; by construction this + * is just popcount. */ - /* Link up with fragment varyings */ - bool reads_point_coord = fs->reads_point_coord; +static inline unsigned +pan_xfb_base(unsigned present) +{ + return util_bitcount(present); +} - for (unsigned i = 0; i < fs->varying_count; i++) { - gl_varying_slot loc = fs->varyings_loc[i]; - unsigned src_offset; - signed vs_idx = -1; - - /* Link up */ - for (unsigned j = 0; j < vs->varying_count; ++j) { - if (vs->varyings_loc[j] == loc) { - vs_idx = j; - break; - } - } +/* Computes the present mask for varyings so we can start emitting varying records */ - /* Either assign or reuse */ - if (vs_idx >= 0) - src_offset = vs->varyings[vs_idx].src_offset; - else - src_offset = 16 * (num_gen_varyings++); +static inline unsigned +pan_varying_present( + struct panfrost_shader_state *vs, + struct panfrost_shader_state *fs, + unsigned quirks) +{ + /* At the moment we always emit general and position buffers. Not + * strictly necessary but usually harmless */ - fs->varyings[i].src_offset = src_offset; + unsigned present = (1 << PAN_VARY_GENERAL) | (1 << PAN_VARY_POSITION); - if (has_point_coord(fs->point_sprite_mask, loc)) - reads_point_coord = true; - } + /* Enable special buffers by the shader info */ - memcpy(trans.cpu, vs->varyings, vs_size); - memcpy(trans.cpu + vs_size, fs->varyings, fs_size); + if (vs->writes_point_size) + present |= (1 << PAN_VARY_PSIZ); - union mali_attr varyings[PIPE_MAX_ATTRIBS] = {0}; + if (fs->reads_point_coord) + present |= (1 << PAN_VARY_PNTCOORD); - /* Figure out how many streamout buffers could be bound */ - unsigned so_count = ctx->streamout.num_targets; - for (unsigned i = 0; i < vs->varying_count; i++) { - gl_varying_slot loc = vs->varyings_loc[i]; + if (fs->reads_face) + present |= (1 << PAN_VARY_FACE); - bool captured = ((vs->so_mask & (1ll << loc)) ? true : false); - if (!captured) continue; + if (fs->reads_frag_coord && !(quirks & IS_BIFROST)) + present |= (1 << PAN_VARY_FRAGCOORD); - struct pipe_stream_output *o = pan_get_so(so, loc); - so_count = MAX2(so_count, o->output_buffer + 1); - } + /* Also, if we have a point sprite, we need a point coord buffer */ - signed idx = so_count; - signed general = idx++; - signed gl_Position = idx++; - signed gl_PointSize = vs->writes_point_size ? (idx++) : -1; - signed gl_PointCoord = reads_point_coord ? (idx++) : -1; - signed gl_FrontFacing = fs->reads_face ? (idx++) : -1; - signed gl_FragCoord = (fs->reads_frag_coord && - !(device->quirks & IS_BIFROST)) - ? (idx++) : -1; + for (unsigned i = 0; i < fs->varying_count; i++) { + gl_varying_slot loc = fs->varyings_loc[i]; - /* Emit the stream out buffers */ + if (has_point_coord(fs->point_sprite_mask, loc)) + present |= (1 << PAN_VARY_PNTCOORD); + } - unsigned out_count = u_stream_outputs_for_vertices(ctx->active_prim, - ctx->vertex_count); + return present; +} - for (unsigned i = 0; i < so_count; ++i) { - if (i < ctx->streamout.num_targets) { - panfrost_emit_streamout(batch, &varyings[i], - so->stride[i], - ctx->streamout.offsets[i], - out_count, - ctx->streamout.targets[i]); - } else { - /* Emit a dummy buffer */ - panfrost_emit_varyings(batch, &varyings[i], - so->stride[i] * 4, - out_count); +/* Emitters for varying records */ - /* Clear the attribute type */ - varyings[i].elements &= ~0xF; - } +static void +pan_emit_vary(struct mali_attribute_packed *out, + unsigned present, enum pan_special_varying buf, + unsigned quirks, enum mali_format format, + unsigned offset) +{ + unsigned nr_channels = MALI_EXTRACT_CHANNELS(format); + unsigned swizzle = quirks & HAS_SWIZZLES ? + panfrost_get_default_swizzle(nr_channels) : + panfrost_bifrost_swizzle(nr_channels); + + pan_pack(out, ATTRIBUTE, cfg) { + cfg.buffer_index = pan_varying_index(present, buf); + cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; + cfg.format = (format << 12) | swizzle; + cfg.offset = offset; } +} - panfrost_emit_varyings(batch, &varyings[general], - num_gen_varyings * 16, - vertex_count); +/* General varying that is unused */ - mali_ptr varyings_p; +static void +pan_emit_vary_only(struct mali_attribute_packed *out, + unsigned present, unsigned quirks) +{ + pan_emit_vary(out, present, 0, quirks, MALI_VARYING_DISCARD, 0); +} - /* fp32 vec4 gl_Position */ - varyings_p = panfrost_emit_varyings(batch, &varyings[gl_Position], - sizeof(float) * 4, vertex_count); - tiler_postfix->position_varying = varyings_p; +/* Special records */ +static const enum mali_format pan_varying_formats[PAN_VARY_MAX] = { + [PAN_VARY_POSITION] = MALI_VARYING_POS, + [PAN_VARY_PSIZ] = MALI_R16F, + [PAN_VARY_PNTCOORD] = MALI_R16F, + [PAN_VARY_FACE] = MALI_R32I, + [PAN_VARY_FRAGCOORD] = MALI_RGBA32F +}; - if (panfrost_writes_point_size(ctx)) { - varyings_p = panfrost_emit_varyings(batch, - &varyings[gl_PointSize], - 2, vertex_count); - primitive_size->pointer = varyings_p; - } +static void +pan_emit_vary_special(struct mali_attribute_packed *out, + unsigned present, enum pan_special_varying buf, + unsigned quirks) +{ + assert(buf < PAN_VARY_MAX); + pan_emit_vary(out, present, buf, quirks, pan_varying_formats[buf], 0); +} - if (gl_PointCoord >= 0) - varyings[gl_PointCoord].elements = MALI_VARYING_POINT_COORD; +static enum mali_format +pan_xfb_format(enum mali_format format, unsigned nr) +{ + if (MALI_EXTRACT_BITS(format) == MALI_CHANNEL_FLOAT) + return MALI_R32F | MALI_NR_CHANNELS(nr); + else + return MALI_EXTRACT_TYPE(format) | MALI_NR_CHANNELS(nr) | MALI_CHANNEL_32; +} - if (gl_FrontFacing >= 0) - varyings[gl_FrontFacing].elements = MALI_VARYING_FRONT_FACING; +/* Transform feedback records. Note struct pipe_stream_output is (if packed as + * a bitfield) 32-bit, smaller than a 64-bit pointer, so may as well pass by + * value. */ - if (gl_FragCoord >= 0) - varyings[gl_FragCoord].elements = MALI_VARYING_FRAG_COORD; +static void +pan_emit_vary_xfb(struct mali_attribute_packed *out, + unsigned present, + unsigned max_xfb, + unsigned *streamout_offsets, + unsigned quirks, + enum mali_format format, + struct pipe_stream_output o) +{ + unsigned swizzle = quirks & HAS_SWIZZLES ? + panfrost_get_default_swizzle(o.num_components) : + panfrost_bifrost_swizzle(o.num_components); - assert(!(device->quirks & IS_BIFROST) || !(reads_point_coord)); + pan_pack(out, ATTRIBUTE, cfg) { + /* XFB buffers come after everything else */ + cfg.buffer_index = pan_xfb_base(present) + o.output_buffer; + cfg.unknown = quirks & IS_BIFROST ? 0x0 : 0x1; - /* Let's go ahead and link varying meta to the buffer in question, now - * that that information is available. VARYING_SLOT_POS is mapped to - * gl_FragCoord for fragment shaders but gl_Positionf or vertex shaders - * */ + /* Override number of channels and precision to highp */ + cfg.format = (pan_xfb_format(format, o.num_components) << 12) | swizzle; - panfrost_emit_varying_meta(trans.cpu, vs, general, gl_Position, - gl_PointSize, gl_PointCoord, - gl_FrontFacing); + /* Apply given offsets together */ + cfg.offset = (o.dst_offset * 4) /* dwords */ + + streamout_offsets[o.output_buffer]; + } +} - panfrost_emit_varying_meta(trans.cpu + vs_size, fs, general, - gl_FragCoord, gl_PointSize, - gl_PointCoord, gl_FrontFacing); +/* Determine if we should capture a varying for XFB. This requires actually + * having a buffer for it. If we don't capture it, we'll fallback to a general + * varying path (linked or unlinked, possibly discarding the write) */ - /* Replace streamout */ +static bool +panfrost_xfb_captured(struct panfrost_shader_state *xfb, + unsigned loc, unsigned max_xfb) +{ + if (!(xfb->so_mask & (1ll << loc))) + return false; - struct mali_attr_meta *ovs = (struct mali_attr_meta *)trans.cpu; - struct mali_attr_meta *ofs = ovs + vs->varying_count; + struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); + return o->output_buffer < max_xfb; +} - for (unsigned i = 0; i < vs->varying_count; i++) { - gl_varying_slot loc = vs->varyings_loc[i]; +static void +pan_emit_general_varying(struct mali_attribute_packed *out, + struct panfrost_shader_state *other, + struct panfrost_shader_state *xfb, + gl_varying_slot loc, + enum mali_format format, + unsigned present, + unsigned quirks, + unsigned *gen_offsets, + enum mali_format *gen_formats, + unsigned *gen_stride, + unsigned idx, + bool should_alloc) +{ + /* Check if we're linked */ + signed other_idx = -1; - bool captured = ((vs->so_mask & (1ll << loc)) ? true : false); - if (!captured) - continue; + for (unsigned j = 0; j < other->varying_count; ++j) { + if (other->varyings_loc[j] == loc) { + other_idx = j; + break; + } + } - struct pipe_stream_output *o = pan_get_so(so, loc); - ovs[i].index = o->output_buffer; + if (other_idx < 0) { + pan_emit_vary_only(out, present, quirks); + return; + } - assert(o->stream == 0); - ovs[i].format = (vs->varyings[i].format & ~MALI_NR_CHANNELS(4)) - | MALI_NR_CHANNELS(o->num_components); + unsigned offset = gen_offsets[other_idx]; - if (device->quirks & HAS_SWIZZLES) - ovs[i].swizzle = panfrost_get_default_swizzle(o->num_components); - else - ovs[i].swizzle = panfrost_bifrost_swizzle(o->num_components); + if (should_alloc) { + /* We're linked, so allocate a space via a watermark allocation */ + enum mali_format alt = other->varyings[other_idx]; - /* Link to the fragment */ - signed fs_idx = -1; + /* Do interpolation at minimum precision */ + unsigned size_main = pan_varying_size(format); + unsigned size_alt = pan_varying_size(alt); + unsigned size = MIN2(size_main, size_alt); - /* Link up */ - for (unsigned j = 0; j < fs->varying_count; ++j) { - if (fs->varyings_loc[j] == loc) { - fs_idx = j; - break; - } - } + /* If a varying is marked for XFB but not actually captured, we + * should match the format to the format that would otherwise + * be used for XFB, since dEQP checks for invariance here. It's + * unclear if this is required by the spec. */ - if (fs_idx >= 0) { - ofs[fs_idx].index = ovs[i].index; - ofs[fs_idx].format = ovs[i].format; - ofs[fs_idx].swizzle = ovs[i].swizzle; + if (xfb->so_mask & (1ull << loc)) { + struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); + format = pan_xfb_format(format, o->num_components); + size = pan_varying_size(format); + } else if (size == size_alt) { + format = alt; } + + gen_offsets[idx] = *gen_stride; + gen_formats[other_idx] = format; + offset = *gen_stride; + *gen_stride += size; } - /* Replace point sprite */ - for (unsigned i = 0; i < fs->varying_count; i++) { - /* If we have a point sprite replacement, handle that here. We - * have to translate location first. TODO: Flip y in shader. - * We're already keying ... just time crunch .. */ + pan_emit_vary(out, present, PAN_VARY_GENERAL, quirks, format, offset); +} + +/* Higher-level wrapper around all of the above, classifying a varying into one + * of the above types */ + +static void +panfrost_emit_varying( + struct mali_attribute_packed *out, + struct panfrost_shader_state *stage, + struct panfrost_shader_state *other, + struct panfrost_shader_state *xfb, + unsigned present, + unsigned max_xfb, + unsigned *streamout_offsets, + unsigned quirks, + unsigned *gen_offsets, + enum mali_format *gen_formats, + unsigned *gen_stride, + unsigned idx, + bool should_alloc, + bool is_fragment) +{ + gl_varying_slot loc = stage->varyings_loc[idx]; + enum mali_format format = stage->varyings[idx]; + + /* Override format to match linkage */ + if (!should_alloc && gen_formats[idx]) + format = gen_formats[idx]; + + if (has_point_coord(stage->point_sprite_mask, loc)) { + pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); + } else if (panfrost_xfb_captured(xfb, loc, max_xfb)) { + struct pipe_stream_output *o = pan_get_so(&xfb->stream_output, loc); + pan_emit_vary_xfb(out, present, max_xfb, streamout_offsets, quirks, format, *o); + } else if (loc == VARYING_SLOT_POS) { + if (is_fragment) + pan_emit_vary_special(out, present, PAN_VARY_FRAGCOORD, quirks); + else + pan_emit_vary_special(out, present, PAN_VARY_POSITION, quirks); + } else if (loc == VARYING_SLOT_PSIZ) { + pan_emit_vary_special(out, present, PAN_VARY_PSIZ, quirks); + } else if (loc == VARYING_SLOT_PNTC) { + pan_emit_vary_special(out, present, PAN_VARY_PNTCOORD, quirks); + } else if (loc == VARYING_SLOT_FACE) { + pan_emit_vary_special(out, present, PAN_VARY_FACE, quirks); + } else { + pan_emit_general_varying(out, other, xfb, loc, format, present, + quirks, gen_offsets, gen_formats, gen_stride, + idx, should_alloc); + } +} - if (has_point_coord(fs->point_sprite_mask, - fs->varyings_loc[i])) { - ofs[i].index = gl_PointCoord; +static void +pan_emit_special_input(struct mali_attribute_buffer_packed *out, + unsigned present, + enum pan_special_varying v, + unsigned special) +{ + if (present & (1 << v)) { + unsigned idx = pan_varying_index(present, v); - /* Swizzle out the z/w to 0/1 */ - ofs[i].format = MALI_RG16F; - ofs[i].swizzle = panfrost_get_default_swizzle(2); + pan_pack(out + idx, ATTRIBUTE_BUFFER, cfg) { + cfg.special = special; + cfg.type = 0; } } +} - /* Fix up unaligned addresses */ - for (unsigned i = 0; i < so_count; ++i) { - if (varyings[i].elements < MALI_RECORD_SPECIAL) - continue; +void +panfrost_emit_varying_descriptor(struct panfrost_batch *batch, + unsigned vertex_count, + struct mali_vertex_tiler_postfix *vertex_postfix, + struct mali_vertex_tiler_postfix *tiler_postfix, + union midgard_primitive_size *primitive_size) +{ + /* Load the shaders */ + struct panfrost_context *ctx = batch->ctx; + struct panfrost_device *dev = pan_device(ctx->base.screen); + struct panfrost_shader_state *vs, *fs; + size_t vs_size, fs_size; - unsigned align = (varyings[i].elements & 63); + /* Allocate the varying descriptor */ - /* While we're at it, the SO buffers are linear */ + vs = panfrost_get_shader_state(ctx, PIPE_SHADER_VERTEX); + fs = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); + vs_size = MALI_ATTRIBUTE_LENGTH * vs->varying_count; + fs_size = MALI_ATTRIBUTE_LENGTH * fs->varying_count; - if (!align) { - varyings[i].elements |= MALI_ATTR_LINEAR; - continue; - } + struct panfrost_transfer trans = panfrost_pool_alloc_aligned( + &batch->pool, vs_size + fs_size, MALI_ATTRIBUTE_LENGTH); - /* We need to adjust alignment */ - varyings[i].elements &= ~63; - varyings[i].elements |= MALI_ATTR_LINEAR; - varyings[i].size += align; + struct pipe_stream_output_info *so = &vs->stream_output; + unsigned present = pan_varying_present(vs, fs, dev->quirks); - for (unsigned v = 0; v < vs->varying_count; ++v) { - if (ovs[v].index != i) - continue; + /* Check if this varying is linked by us. This is the case for + * general-purpose, non-captured varyings. If it is, link it. If it's + * not, use the provided stream out information to determine the + * offset, since it was already linked for us. */ - ovs[v].src_offset = vs->varyings[v].src_offset + align; - } + unsigned gen_offsets[32]; + enum mali_format gen_formats[32]; + memset(gen_offsets, 0, sizeof(gen_offsets)); + memset(gen_formats, 0, sizeof(gen_formats)); - for (unsigned f = 0; f < fs->varying_count; ++f) { - if (ofs[f].index != i) - continue; + unsigned gen_stride = 0; + assert(vs->varying_count < ARRAY_SIZE(gen_offsets)); + assert(fs->varying_count < ARRAY_SIZE(gen_offsets)); - ofs[f].src_offset = fs->varyings[f].src_offset + align; - } + unsigned streamout_offsets[32]; + + for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { + streamout_offsets[i] = panfrost_streamout_offset( + so->stride[i], + ctx->streamout.offsets[i], + ctx->streamout.targets[i]); + } + + struct mali_attribute_packed *ovs = (struct mali_attribute_packed *)trans.cpu; + struct mali_attribute_packed *ofs = ovs + vs->varying_count; + + for (unsigned i = 0; i < vs->varying_count; i++) { + panfrost_emit_varying(ovs + i, vs, fs, vs, present, + ctx->streamout.num_targets, streamout_offsets, + dev->quirks, + gen_offsets, gen_formats, &gen_stride, i, true, false); + } + + for (unsigned i = 0; i < fs->varying_count; i++) { + panfrost_emit_varying(ofs + i, fs, vs, vs, present, + ctx->streamout.num_targets, streamout_offsets, + dev->quirks, + gen_offsets, gen_formats, &gen_stride, i, false, true); + } + + unsigned xfb_base = pan_xfb_base(present); + struct panfrost_transfer T = panfrost_pool_alloc_aligned(&batch->pool, + MALI_ATTRIBUTE_BUFFER_LENGTH * (xfb_base + ctx->streamout.num_targets), + MALI_ATTRIBUTE_BUFFER_LENGTH * 2); + struct mali_attribute_buffer_packed *varyings = + (struct mali_attribute_buffer_packed *) T.cpu; + + /* Emit the stream out buffers */ + + unsigned out_count = u_stream_outputs_for_vertices(ctx->active_prim, + ctx->vertex_count); + + for (unsigned i = 0; i < ctx->streamout.num_targets; ++i) { + panfrost_emit_streamout(batch, &varyings[xfb_base + i], + so->stride[i], + ctx->streamout.offsets[i], + out_count, + ctx->streamout.targets[i]); } - varyings_p = panfrost_upload_transient(batch, varyings, - idx * sizeof(*varyings)); - vertex_postfix->varyings = varyings_p; - tiler_postfix->varyings = varyings_p; + panfrost_emit_varyings(batch, + &varyings[pan_varying_index(present, PAN_VARY_GENERAL)], + gen_stride, vertex_count); + + /* fp32 vec4 gl_Position */ + tiler_postfix->position_varying = panfrost_emit_varyings(batch, + &varyings[pan_varying_index(present, PAN_VARY_POSITION)], + sizeof(float) * 4, vertex_count); + + if (present & (1 << PAN_VARY_PSIZ)) { + primitive_size->pointer = panfrost_emit_varyings(batch, + &varyings[pan_varying_index(present, PAN_VARY_PSIZ)], + 2, vertex_count); + } + + pan_emit_special_input(varyings, present, PAN_VARY_PNTCOORD, MALI_ATTRIBUTE_SPECIAL_POINT_COORD); + pan_emit_special_input(varyings, present, PAN_VARY_FACE, MALI_ATTRIBUTE_SPECIAL_FRONT_FACING); + pan_emit_special_input(varyings, present, PAN_VARY_FRAGCOORD, MALI_ATTRIBUTE_SPECIAL_FRAG_COORD); + + vertex_postfix->varyings = T.gpu; + tiler_postfix->varyings = T.gpu; vertex_postfix->varying_meta = trans.gpu; tiler_postfix->varying_meta = trans.gpu + vs_size; @@ -2001,7 +2052,7 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, { struct panfrost_context *ctx = batch->ctx; struct panfrost_device *device = pan_device(ctx->base.screen); - bool wallpapering = ctx->wallpaper_batch && batch->tiler_dep; + bool wallpapering = ctx->wallpaper_batch && batch->scoreboard.tiler_dep; struct bifrost_payload_vertex bifrost_vertex = {0,}; struct bifrost_payload_tiler bifrost_tiler = {0,}; struct midgard_payload_vertex_tiler midgard_vertex = {0,}; @@ -2037,25 +2088,22 @@ panfrost_emit_vertex_tiler_jobs(struct panfrost_batch *batch, if (wallpapering) { /* Inject in reverse order, with "predicted" job indices. * THIS IS A HACK XXX */ - panfrost_new_job(batch, JOB_TYPE_TILER, false, - batch->job_index + 2, tp, tp_size, true); - panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0, + panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, + batch->scoreboard.job_index + 2, tp, tp_size, true); + panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, vp, vp_size, true); return; } /* If rasterizer discard is enable, only submit the vertex */ - bool rasterizer_discard = ctx->rasterizer && - ctx->rasterizer->base.rasterizer_discard; - - unsigned vertex = panfrost_new_job(batch, JOB_TYPE_VERTEX, false, 0, + unsigned vertex = panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_VERTEX, false, 0, vp, vp_size, false); - if (rasterizer_discard) + if (ctx->rasterizer->base.rasterizer_discard) return; - panfrost_new_job(batch, JOB_TYPE_TILER, false, vertex, tp, tp_size, + panfrost_new_job(&batch->pool, &batch->scoreboard, MALI_JOB_TYPE_TILER, false, vertex, tp, tp_size, false); } @@ -2114,5 +2162,5 @@ panfrost_emit_sample_locations(struct panfrost_batch *batch) 0, 0, }; - return panfrost_upload_transient(batch, locations, 96 * sizeof(uint16_t)); + return panfrost_pool_upload_aligned(&batch->pool, locations, 96 * sizeof(uint16_t), 64); }