X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fpanfrost%2Fpan_context.c;h=2fbb19c7d257457269be40210fccb8cfaf50d848;hb=e0a6af9d7b73ee3bf32ba471406810dfc6cfd435;hp=400d83da8095fb82f1b3551446b112120a0dd254;hpb=6afd4addefa111c112b82a88824db7af61003407;p=mesa.git diff --git a/src/gallium/drivers/panfrost/pan_context.c b/src/gallium/drivers/panfrost/pan_context.c index 400d83da809..2fbb19c7d25 100644 --- a/src/gallium/drivers/panfrost/pan_context.c +++ b/src/gallium/drivers/panfrost/pan_context.c @@ -76,20 +76,14 @@ panfrost_emit_midg_tiler(struct panfrost_batch *batch, unsigned vertex_count) t.polygon_list_size = panfrost_tiler_full_size( width, height, t.hierarchy_mask, hierarchy); - /* Sanity check */ - if (vertex_count) { - struct panfrost_bo *tiler_heap; - - tiler_heap = panfrost_batch_get_tiler_heap(batch); t.polygon_list = panfrost_batch_get_polygon_list(batch, header_size + t.polygon_list_size); - /* Allow the entire tiler heap */ - t.heap_start = tiler_heap->gpu; - t.heap_end = tiler_heap->gpu + tiler_heap->size; + t.heap_start = device->tiler_heap->gpu; + t.heap_end = device->tiler_heap->gpu + device->tiler_heap->size; } else { struct panfrost_bo *tiler_dummy; @@ -139,21 +133,9 @@ panfrost_clear( * fragment jobs. */ struct panfrost_batch *batch = panfrost_get_fresh_batch_for_fbo(ctx); - - panfrost_batch_add_fbo_bos(batch); panfrost_batch_clear(batch, buffers, color, depth, stencil); } -/* Reset per-frame context, called on context initialisation as well as after - * flushing a frame */ - -void -panfrost_invalidate_frame(struct panfrost_context *ctx) -{ - /* TODO: When does this need to be handled? */ - ctx->active_queries = true; -} - bool panfrost_writes_point_size(struct panfrost_context *ctx) { @@ -163,73 +145,6 @@ panfrost_writes_point_size(struct panfrost_context *ctx) return vs->writes_point_size && ctx->active_prim == PIPE_PRIM_POINTS; } -void -panfrost_vertex_state_upd_attr_offs(struct panfrost_context *ctx, - struct mali_vertex_tiler_postfix *vertex_postfix) -{ - if (!ctx->vertex) - return; - - struct panfrost_vertex_state *so = ctx->vertex; - - /* Fixup offsets for the second pass. Recall that the hardware - * calculates attribute addresses as: - * - * addr = base + (stride * vtx) + src_offset; - * - * However, on Mali, base must be aligned to 64-bytes, so we - * instead let: - * - * base' = base & ~63 = base - (base & 63) - * - * To compensate when using base' (see emit_vertex_data), we have - * to adjust src_offset by the masked off piece: - * - * addr' = base' + (stride * vtx) + (src_offset + (base & 63)) - * = base - (base & 63) + (stride * vtx) + src_offset + (base & 63) - * = base + (stride * vtx) + src_offset - * = addr; - * - * QED. - */ - - unsigned start = vertex_postfix->offset_start; - - for (unsigned i = 0; i < so->num_elements; ++i) { - unsigned vbi = so->pipe[i].vertex_buffer_index; - struct pipe_vertex_buffer *buf = &ctx->vertex_buffers[vbi]; - - /* Adjust by the masked off bits of the offset. Make sure we - * read src_offset from so->hw (which is not GPU visible) - * rather than target (which is) due to caching effects */ - - unsigned src_offset = so->pipe[i].src_offset; - - /* BOs aligned to 4k so guaranteed aligned to 64 */ - src_offset += (buf->buffer_offset & 63); - - /* Also, somewhat obscurely per-instance data needs to be - * offset in response to a delayed start in an indexed draw */ - - if (so->pipe[i].instance_divisor && ctx->instance_count > 1 && start) - src_offset -= buf->stride * start; - - so->hw[i].src_offset = src_offset; - } -} - -/* Compute number of UBOs active (more specifically, compute the highest UBO - * number addressable -- if there are gaps, include them in the count anyway). - * We always include UBO #0 in the count, since we *need* uniforms enabled for - * sysvals. */ - -unsigned -panfrost_ubo_count(struct panfrost_context *ctx, enum pipe_shader_type stage) -{ - unsigned mask = ctx->constant_buffer[stage].enabled_mask | 1; - return 32 - __builtin_clz(mask); -} - /* The entire frame is in memory -- send it off to the kernel! */ void @@ -296,7 +211,7 @@ panfrost_scissor_culls_everything(struct panfrost_context *ctx) /* Check if we're scissoring at all */ - if (!(ctx->rasterizer && ctx->rasterizer->base.scissor)) + if (!ctx->rasterizer->base.scissor) return false; return (ss->minx == ss->maxx) || (ss->miny == ss->maxy); @@ -364,26 +279,19 @@ panfrost_draw_vbo( assert(ctx->rasterizer != NULL); if (!(ctx->draw_modes & (1 << mode))) { - if (mode == PIPE_PRIM_QUADS && info->count == 4 && !ctx->rasterizer->base.flatshade) { - mode = PIPE_PRIM_TRIANGLE_FAN; - } else { - if (info->count < 4) { - /* Degenerate case? */ - return; - } - - util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base); - util_primconvert_draw_vbo(ctx->primconvert, info); + if (info->count < 4) { + /* Degenerate case? */ return; } + + util_primconvert_save_rasterizer_state(ctx->primconvert, &ctx->rasterizer->base); + util_primconvert_draw_vbo(ctx->primconvert, info); + return; } - /* Now that we have a guaranteed terminating path, find the job. - * Assignment commented out to prevent unused warning */ + /* Now that we have a guaranteed terminating path, find the job. */ struct panfrost_batch *batch = panfrost_get_batch_for_fbo(ctx); - - panfrost_batch_add_fbo_bos(batch); panfrost_batch_set_requirements(batch); /* Take into account a negative bias */ @@ -406,9 +314,6 @@ panfrost_draw_vbo( panfrost_statistics_record(ctx, info); - /* Dispatch "compute jobs" for the vertex/tiler pair as (1, - * vertex_count, 1) */ - panfrost_pack_work_groups_fused(&vertex_prefix, &tiler_prefix, 1, vertex_count, info->instance_count, 1, 1, 1); @@ -422,7 +327,6 @@ panfrost_draw_vbo( &primitive_size); panfrost_emit_shader_meta(batch, PIPE_SHADER_VERTEX, &vertex_postfix); panfrost_emit_shader_meta(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix); - panfrost_emit_vertex_attr_meta(batch, &vertex_postfix); panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix); panfrost_emit_sampler_descriptors(batch, PIPE_SHADER_FRAGMENT, &tiler_postfix); panfrost_emit_texture_descriptors(batch, PIPE_SHADER_VERTEX, &vertex_postfix); @@ -462,6 +366,9 @@ panfrost_create_rasterizer_state( so->base = *cso; + /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */ + assert(cso->offset_clamp == 0.0); + return so; } @@ -477,9 +384,6 @@ panfrost_bind_rasterizer_state( if (!hwcso) return; - /* Gauranteed with the core GL call, so don't expose ARB_polygon_offset */ - assert(ctx->rasterizer->base.offset_clamp == 0.0); - /* Point sprites are emulated */ struct panfrost_shader_state *variant = panfrost_get_shader_state(ctx, PIPE_SHADER_FRAGMENT); @@ -501,34 +405,29 @@ panfrost_create_vertex_elements_state( memcpy(so->pipe, elements, sizeof(*elements) * num_elements); for (int i = 0; i < num_elements; ++i) { - so->hw[i].index = i; - enum pipe_format fmt = elements[i].src_format; const struct util_format_description *desc = util_format_description(fmt); - so->hw[i].unknown1 = 0x2; - + unsigned swizzle = 0; if (dev->quirks & HAS_SWIZZLES) - so->hw[i].swizzle = panfrost_translate_swizzle_4(desc->swizzle); + swizzle = panfrost_translate_swizzle_4(desc->swizzle); else - so->hw[i].swizzle = panfrost_bifrost_swizzle(desc->nr_channels); + swizzle = panfrost_bifrost_swizzle(desc->nr_channels); enum mali_format hw_format = panfrost_pipe_format_table[desc->format].hw; - so->hw[i].format = hw_format; + so->formats[i] = (hw_format << 12) | swizzle; assert(hw_format); } /* Let's also prepare vertex builtins */ - so->hw[PAN_VERTEX_ID].format = MALI_R32UI; if (dev->quirks & HAS_SWIZZLES) - so->hw[PAN_VERTEX_ID].swizzle = panfrost_get_default_swizzle(1); + so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1); else - so->hw[PAN_VERTEX_ID].swizzle = panfrost_bifrost_swizzle(1); + so->formats[PAN_VERTEX_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1); - so->hw[PAN_INSTANCE_ID].format = MALI_R32UI; if (dev->quirks & HAS_SWIZZLES) - so->hw[PAN_INSTANCE_ID].swizzle = panfrost_get_default_swizzle(1); + so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_get_default_swizzle(1); else - so->hw[PAN_INSTANCE_ID].swizzle = panfrost_bifrost_swizzle(1); + so->formats[PAN_INSTANCE_ID] = (MALI_R32UI << 12) | panfrost_bifrost_swizzle(1); return so; } @@ -605,9 +504,9 @@ panfrost_create_sampler_state( so->base = *cso; if (device->quirks & IS_BIFROST) - panfrost_sampler_desc_init_bifrost(cso, &so->bifrost_hw); + panfrost_sampler_desc_init_bifrost(cso, (struct mali_bifrost_sampler_packed *) &so->hw); else - panfrost_sampler_desc_init(cso, &so->midgard_hw); + panfrost_sampler_desc_init(cso, &so->hw); return so; } @@ -958,8 +857,8 @@ panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so, assert(texture->nr_samples <= 1); } - enum mali_texture_type type = - panfrost_translate_texture_type(so->base.target); + enum mali_texture_dimension type = + panfrost_translate_texture_dimension(so->base.target); if (device->quirks & IS_BIFROST) { unsigned char composed_swizzle[4]; @@ -975,9 +874,8 @@ panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so, so->bo = panfrost_bo_create(device, size, 0); - so->bifrost_descriptor = rzalloc(pctx, struct bifrost_texture_descriptor); panfrost_new_texture_bifrost( - so->bifrost_descriptor, + &so->bifrost_descriptor, texture->width0, texture->height0, depth, array_size, format, @@ -1000,7 +898,7 @@ panfrost_create_sampler_view_bo(struct panfrost_sampler_view *so, so->base.u.tex.last_layer, texture->nr_samples, type, prsrc->modifier); - size += sizeof(struct mali_texture_descriptor); + size += MALI_MIDGARD_TEXTURE_LENGTH; so->bo = panfrost_bo_create(device, size, 0); @@ -1078,8 +976,6 @@ panfrost_sampler_view_destroy( pipe_resource_reference(&pview->texture, NULL); panfrost_bo_unreference(view->bo); - if (view->bifrost_descriptor) - ralloc_free(view->bifrost_descriptor); ralloc_free(view); } @@ -1105,7 +1001,6 @@ panfrost_set_framebuffer_state(struct pipe_context *pctx, util_copy_framebuffer_state(&ctx->pipe_framebuffer, fb); ctx->batch = NULL; - panfrost_invalidate_frame(ctx); /* We may need to generate a new variant if the fragment shader is * keyed to the framebuffer format (due to EXT_framebuffer_fetch) */ @@ -1555,7 +1450,6 @@ panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags) /* Prepare for render! */ panfrost_batch_init(ctx); - panfrost_invalidate_frame(ctx); if (!(dev->quirks & IS_BIFROST)) { for (unsigned c = 0; c < PIPE_MAX_COLOR_BUFS; ++c) @@ -1564,6 +1458,7 @@ panfrost_create_context(struct pipe_screen *screen, void *priv, unsigned flags) /* By default mask everything on */ ctx->sample_mask = ~0; + ctx->active_queries = true; return gallium; }