X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr300%2Fr300_flush.c;h=f6c1bf32ca2db24fbd6b0af8183d823893df69a3;hb=63dd1e980c6855cbfe4cc0ea71779b52c03631ca;hp=cbe2b5784489e73d9a850ab8a9f08c01c50c0cea;hpb=6067a30838535c838262a9229b400afe4d92c184;p=mesa.git diff --git a/src/gallium/drivers/r300/r300_flush.c b/src/gallium/drivers/r300/r300_flush.c index cbe2b578448..f6c1bf32ca2 100644 --- a/src/gallium/drivers/r300/r300_flush.c +++ b/src/gallium/drivers/r300/r300_flush.c @@ -24,17 +24,18 @@ #include "draw/draw_context.h" #include "draw/draw_private.h" -#include "util/u_simple_list.h" +#include "util/simple_list.h" #include "util/u_upload_mgr.h" -#include "os/os_time.h" +#include "util/os_time.h" #include "r300_context.h" #include "r300_cs.h" #include "r300_emit.h" -static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags) +static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags, + struct pipe_fence_handle **fence) { struct r300_atom *atom; @@ -44,7 +45,7 @@ static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags) r500_emit_index_bias(r300, 0); /* The DDX doesn't set these regs. */ - if (r300->screen->info.drm_minor >= 6) { + { CS_LOCALS(r300); OUT_CS_REG_SEQ(R300_GB_MSPOS0, 2); OUT_CS(0x66666666); @@ -52,7 +53,7 @@ static void r300_flush_and_cleanup(struct r300_context *r300, unsigned flags) } r300->flush_counter++; - r300->rws->cs_flush(r300->cs, flags, 0); + r300->rws->cs_flush(r300->cs, flags, fence); r300->dirty_hw = 0; /* New kitchen sink, baby. */ @@ -77,27 +78,19 @@ void r300_flush(struct pipe_context *pipe, { struct r300_context *r300 = r300_context(pipe); - if (r300->screen->info.drm_minor >= 12) { - flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; - } - - if (fence) { - *fence = r300->rws->cs_create_fence(r300->cs); - } - if (r300->dirty_hw) { - r300_flush_and_cleanup(r300, flags); + r300_flush_and_cleanup(r300, flags, fence); } else { if (fence) { /* We have to create a fence object, but the command stream is empty * and we cannot emit an empty CS. Let's write to some reg. */ CS_LOCALS(r300); OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0); - r300->rws->cs_flush(r300->cs, flags, 0); + r300->rws->cs_flush(r300->cs, flags, fence); } else { /* Even if hw is not dirty, we should at least reset the CS in case * the space checking failed for the first draw operation. */ - r300->rws->cs_flush(r300->cs, flags, 0); + r300->rws->cs_flush(r300->cs, flags, NULL); } } @@ -119,7 +112,9 @@ void r300_flush(struct pipe_context *pipe, r300_decompress_zmask(r300); } - r300_flush_and_cleanup(r300, flags); + if (fence && *fence) + r300->rws->fence_reference(fence, NULL); + r300_flush_and_cleanup(r300, flags, fence); } /* Revoke Hyper-Z access, so that some other process can take it. */ @@ -134,9 +129,10 @@ static void r300_flush_wrapped(struct pipe_context *pipe, struct pipe_fence_handle **fence, unsigned flags) { - r300_flush(pipe, - flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0, - fence); + if (flags & PIPE_FLUSH_HINT_FINISH) + flags &= ~PIPE_FLUSH_ASYNC; + + r300_flush(pipe, flags, fence); } void r300_init_flush_functions(struct r300_context* r300)