X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr300%2Fr300_reg.h;h=9c93b84ee5f4c0c068e473d402c9757864665a3c;hb=56f9cc9948745b570704f20e18f0247628817de5;hp=60d3b600cb7fcdd1f4b7c658e93bf486d2595335;hpb=6c03c576cc49bbb008de66d374f4302ff0fe0390;p=mesa.git diff --git a/src/gallium/drivers/r300/r300_reg.h b/src/gallium/drivers/r300/r300_reg.h index 60d3b600cb7..9c93b84ee5f 100644 --- a/src/gallium/drivers/r300/r300_reg.h +++ b/src/gallium/drivers/r300/r300_reg.h @@ -191,7 +191,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_VAP_TCL_BYPASS (1 << 8) /* Read only flag if TCL engine is busy. */ # define R300_VAP_PVS_BUSY (1 << 11) -/* TODO: gap for MAX_MPS */ /* Read only flag if the vertex store is busy. */ # define R300_VAP_VS_BUSY (1 << 24) /* Read only flag if the reciprocal engine is busy. */ @@ -427,7 +426,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_PVS_CONST_START 512 # define R500_PVS_CONST_START 1024 # define R300_MAX_PVS_CONST_VECS 256 -# define R500_MAX_PVS_CONST_VECS 1024 +# define R500_MAX_PVS_CONST_VECS 256 # define R300_PVS_UCP_START 1024 # define R500_PVS_UCP_START 1536 # define R300_POINT_VPORT_SCALE_OFFSET 1030 @@ -467,6 +466,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * * See bug #9871. http://bugs.freedesktop.org/attachment.cgi?id=10672&action=view */ +#define R500_VAP_TEX_TO_COLOR_CNTL 0x2218 + #define R300_VAP_CLIP_CNTL 0x221C # define R300_VAP_UCP_ENABLE_0 (1 << 0) # define R300_VAP_UCP_ENABLE_1 (1 << 1) @@ -553,6 +554,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* Addresses are relative to the vertex program parameters area. */ #define R300_VAP_PVS_CONST_CNTL 0x22D4 # define R300_PVS_CONST_BASE_OFFSET_SHIFT 0 +# define R300_PVS_CONST_BASE_OFFSET(x) (x) # define R300_PVS_MAX_CONST_ADDR_SHIFT 16 # define R300_PVS_MAX_CONST_ADDR(x) ((x) << 16) #define R300_VAP_PVS_CODE_CNTL_1 0x22D8 @@ -856,6 +858,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R500_TX_DIRECTION_HORIZONTAL (0<<27) # define R500_TX_DIRECTION_VERITCAL (1<<27) +#define R500_SU_TEX_WRAP_PS3 0x4114 + /* S Texture Coordinate of Vertex 0 for Point texture stuffing (LLC) */ #define R300_GA_POINT_S0 0x4200 @@ -916,9 +920,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * * The line width is given in multiples of 6. * In default mode lines are classified as vertical lines. - * HO: horizontal - * VE: vertical or horizontal - * HO & VE: no classification */ #define R300_GA_LINE_CNTL 0x4234 # define R300_GA_LINE_CNTL_WIDTH_SHIFT 0 @@ -929,12 +930,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_GA_LINE_CNTL_END_TYPE_COMP (3 << 16) /* Computed (perpendicular to slope) */ # define R500_GA_LINE_CNTL_SORT_NO (0 << 18) # define R500_GA_LINE_CNTL_SORT_MINX_MINY (1 << 18) -/** TODO: looks wrong */ -# define R300_LINESIZE_MAX (R300_GA_LINE_CNTL_WIDTH_MASK / 6) -/** TODO: looks wrong */ -# define R300_LINE_CNT_HO (1 << 16) -/** TODO: looks wrong */ -# define R300_LINE_CNT_VE (1 << 17) /* Line Stipple configuration information. */ #define R300_GA_LINE_STIPPLE_CONFIG 0x4238 @@ -1184,7 +1179,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_GA_SOFT_RESET 0x429c /* Not sure why there are duplicate of factor and constant values. - * My best guess so far is that there are seperate zbiases for test and write. + * My best guess so far is that there are separate zbiases for test and write. * Ordering might be wrong. * Some of the tests indicate that fgl has a fallback implementation of zbias * via pixel shaders. @@ -1273,8 +1268,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_RS_IP_1 0x4314 #define R300_RS_IP_2 0x4318 #define R300_RS_IP_3 0x431C -# define R300_RS_INTERP_SRC_SHIFT 2 /* TODO: check for removal */ -# define R300_RS_INTERP_SRC_MASK (7 << 2) /* TODO: check for removal */ # define R300_RS_TEX_PTR(x) (x << 0) # define R300_RS_COL_PTR(x) ((x) << 6) # define R300_RS_COL_FMT(x) ((x) << 9) @@ -1520,11 +1513,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_TX_TRI_PERF_3_8 (3<<15) # define R300_ANISO_THRESHOLD_MASK (7<<17) +# define R400_DXTC_SWIZZLE_ENABLE (1<<21) # define R500_MACRO_SWITCH (1<<22) # define R500_TX_MAX_ANISO(x) ((x) << 23) # define R500_TX_MAX_ANISO_MASK (63 << 23) # define R500_TX_ANISO_HIGH_QUALITY (1 << 30) - # define R500_BORDER_FIX (1<<31) #define R300_TX_FORMAT0_0 0x4480 @@ -1607,6 +1600,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_TX_FORMAT_3D (1 << 25) # define R300_TX_FORMAT_CUBIC_MAP (2 << 25) +# define R300_TX_FORMAT_TEX_COORD_TYPE_MASK (0x3 << 25) /* alpha modes, convenience mostly */ /* if you have alpha, pick constant appropriate to the @@ -1706,10 +1700,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_TX_OFFSET_6 0x4558 #define R300_TX_OFFSET_7 0x455C -# define R300_TXO_ENDIAN_NO_SWAP (0 << 0) -# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) -# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) -# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) +# define R300_TXO_ENDIAN(x) ((x) << 0) # define R300_TXO_MACRO_TILE_LINEAR (0 << 2) # define R300_TXO_MACRO_TILE_TILED (1 << 2) # define R300_TXO_MACRO_TILE(x) ((x) << 2) @@ -2072,18 +2063,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_ALU_OUTC_D2A (3 << 23) # define R300_ALU_OUTC_MIN (4 << 23) # define R300_ALU_OUTC_MAX (5 << 23) -# define R300_ALU_OUTC_CMPH (7 << 23) +# define R300_ALU_OUTC_CND (7 << 23) # define R300_ALU_OUTC_CMP (8 << 23) # define R300_ALU_OUTC_FRC (9 << 23) # define R300_ALU_OUTC_REPL_ALPHA (10 << 23) -# define R300_ALU_OUTC_MOD_NOP (0 << 27) -# define R300_ALU_OUTC_MOD_MUL2 (1 << 27) -# define R300_ALU_OUTC_MOD_MUL4 (2 << 27) -# define R300_ALU_OUTC_MOD_MUL8 (3 << 27) -# define R300_ALU_OUTC_MOD_DIV2 (4 << 27) -# define R300_ALU_OUTC_MOD_DIV4 (5 << 27) -# define R300_ALU_OUTC_MOD_DIV8 (6 << 27) +# define R300_ALU_OUTC_MOD_SHIFT 27 +# define R300_ALU_OUTC_MOD_NOP (0 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_MUL2 (1 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_MUL4 (2 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_MUL8 (3 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_DIV2 (4 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_DIV4 (5 << R300_ALU_OUTC_MOD_SHIFT) +# define R300_ALU_OUTC_MOD_DIV8 (6 << R300_ALU_OUTC_MOD_SHIFT) # define R300_ALU_OUTC_CLAMP (1 << 30) # define R300_ALU_INSERT_NOP (1 << 31) @@ -2160,14 +2152,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. /* R4xx extended fragment shader registers. */ #define R400_US_ALU_EXT_ADDR_0 0x4ac0 /* up to 63 (0x4bbc) */ -# define R400_ADDR0_EXT_RGB_MSB_BIT 0x01 -# define R400_ADDR1_EXT_RGB_MSB_BIT 0x02 -# define R400_ADDR2_EXT_RGB_MSB_BIT 0x04 +# define R400_ADDR_EXT_RGB_MSB_BIT(x) (1 << (x)) # define R400_ADDRD_EXT_RGB_MSB_BIT 0x08 -# define R400_ADDR0_EXT_A_MSB_BIT 0x10 -# define R400_ADDR1_EXT_A_MSB_BIT 0x20 -# define R400_ADDR2_EXT_A_MSB_BIT 0x40 +# define R400_ADDR_EXT_A_MSB_BIT(x) (1 << ((x) + 4)) # define R400_ADDRD_EXT_A_MSB_BIT 0x80 + #define R400_US_CODE_BANK 0x46b8 # define R400_BANK_SHIFT 0 # define R400_BANK_MASK 0xf @@ -2386,7 +2375,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. * Program this register with a 32-bit value in ARGB8888 or ARGB2101010 * formats, ignoring the fields. */ -#define RB3D_COLOR_CLEAR_VALUE 0x4e14 +#define R300_RB3D_COLOR_CLEAR_VALUE 0x4E14 +/* For FP16 AA. */ +#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46C0 +#define R500_RB3D_COLOR_CLEAR_VALUE_GB 0x46C4 /* gap */ @@ -2423,10 +2415,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_COLOR_MICROTILE_ENABLE (1 << 17) # define R300_COLOR_MICROTILE_ENABLE_SQUARE (2 << 17) /* Only available in 16-bit */ # define R300_COLOR_MICROTILE(x) ((x) << 17) -# define R300_COLOR_ENDIAN_NO_SWAP (0 << 19) -# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 19) -# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 19) -# define R300_COLOR_ENDIAN_HALF_DWORD_SWAP (3 << 19) +# define R300_COLOR_ENDIAN(x) ((x) << 19) # define R500_COLOR_FORMAT_ARGB10101010 (0 << 21) # define R500_COLOR_FORMAT_UV1010 (1 << 21) # define R500_COLOR_FORMAT_CI8 (2 << 21) /* 2D only */ @@ -2481,6 +2470,18 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT (2 << 2) /* reserved */ +#define R300_RB3D_CMASK_OFFSET0 0x4E54 +#define R300_RB3D_CMASK_OFFSET1 0x4E58 +#define R300_RB3D_CMASK_OFFSET2 0x4E5C +#define R300_RB3D_CMASK_OFFSET3 0x4E60 +#define R300_RB3D_CMASK_PITCH0 0x4E64 +#define R300_RB3D_CMASK_PITCH1 0x4E68 +#define R300_RB3D_CMASK_PITCH2 0x4E6C +#define R300_RB3D_CMASK_PITCH3 0x4E70 +#define R300_RB3D_CMASK_WRINDEX 0x4E74 +#define R300_RB3D_CMASK_DWORD 0x4E78 +#define R300_RB3D_CMASK_RDINDEX 0x4E7C + /* Resolve buffer destination address. The cache must be empty before changing * this register if the cb is in resolve mode. Unpipelined */ @@ -2629,8 +2630,8 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. #define R300_ZB_BW_CNTL 0x4f1c # define R300_HIZ_DISABLE (0 << 0) # define R300_HIZ_ENABLE (1 << 0) -# define R300_HIZ_MIN (0 << 1) -# define R300_HIZ_MAX (1 << 1) +# define R300_HIZ_MAX (0 << 1) +# define R300_HIZ_MIN (1 << 1) # define R300_FAST_FILL_DISABLE (0 << 2) # define R300_FAST_FILL_ENABLE (1 << 2) # define R300_RD_COMP_DISABLE (0 << 3) @@ -2686,10 +2687,12 @@ USE OR OTHER DEALINGS IN THE SOFTWARE. # define R300_DEPTHMICROTILE_TILED (1 << 17) # define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17) # define R300_DEPTHMICROTILE(x) ((x) << 17) -# define R300_DEPTHENDIAN_NO_SWAP (0 << 18) -# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18) -# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18) -# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18) +# define R300_DEPTHENDIAN(x) ((x) << 19) + +#define R300_SURF_NO_SWAP 0 +#define R300_SURF_WORD_SWAP 1 +#define R300_SURF_DWORD_SWAP 2 +#define R300_SURF_HALF_DWORD_SWAP 3 /* Z Buffer Clear Value */ #define R300_ZB_DEPTHCLEARVALUE 0x4f28 @@ -2941,6 +2944,25 @@ enum { /*\}*/ +#define PVS_OP_DST_OPERAND(opcode, math_inst, macro_inst, reg_index, reg_writemask, reg_class, saturate) \ + (((opcode & PVS_DST_OPCODE_MASK) << PVS_DST_OPCODE_SHIFT) \ + | ((math_inst & PVS_DST_MATH_INST_MASK) << PVS_DST_MATH_INST_SHIFT) \ + | ((macro_inst & PVS_DST_MACRO_INST_MASK) << PVS_DST_MACRO_INST_SHIFT) \ + | ((reg_index & PVS_DST_OFFSET_MASK) << PVS_DST_OFFSET_SHIFT) \ + | ((reg_writemask & 0xf) << PVS_DST_WE_X_SHIFT) /* X Y Z W */ \ + | ((reg_class & PVS_DST_REG_TYPE_MASK) << PVS_DST_REG_TYPE_SHIFT)) \ + | ((math_inst) ? (((saturate) & PVS_DST_ME_SAT_MASK) << PVS_DST_ME_SAT_SHIFT) : \ + (((saturate) & PVS_DST_VE_SAT_MASK) << PVS_DST_VE_SAT_SHIFT)) + +#define PVS_SRC_OPERAND(in_reg_index, comp_x, comp_y, comp_z, comp_w, reg_class, negate) \ + (((in_reg_index & PVS_SRC_OFFSET_MASK) << PVS_SRC_OFFSET_SHIFT) \ + | ((comp_x & PVS_SRC_SWIZZLE_X_MASK) << PVS_SRC_SWIZZLE_X_SHIFT) \ + | ((comp_y & PVS_SRC_SWIZZLE_Y_MASK) << PVS_SRC_SWIZZLE_Y_SHIFT) \ + | ((comp_z & PVS_SRC_SWIZZLE_Z_MASK) << PVS_SRC_SWIZZLE_Z_SHIFT) \ + | ((comp_w & PVS_SRC_SWIZZLE_W_MASK) << PVS_SRC_SWIZZLE_W_SHIFT) \ + | ((negate & 0xf) << PVS_SRC_MODIFIER_X_SHIFT) /* X Y Z W */ \ + | ((reg_class & PVS_SRC_REG_TYPE_MASK) << PVS_SRC_REG_TYPE_SHIFT)) + /* BEGIN: Packet 3 commands */ /* A primitive emission dword. */ @@ -3034,14 +3056,15 @@ enum { # define R500_ALPHA_MOD_B_NEG (1 << 24) # define R500_ALPHA_MOD_B_ABS (2 << 24) # define R500_ALPHA_MOD_B_NAB (3 << 24) -# define R500_ALPHA_OMOD_IDENTITY (0 << 26) -# define R500_ALPHA_OMOD_MUL_2 (1 << 26) -# define R500_ALPHA_OMOD_MUL_4 (2 << 26) -# define R500_ALPHA_OMOD_MUL_8 (3 << 26) -# define R500_ALPHA_OMOD_DIV_2 (4 << 26) -# define R500_ALPHA_OMOD_DIV_4 (5 << 26) -# define R500_ALPHA_OMOD_DIV_8 (6 << 26) -# define R500_ALPHA_OMOD_DISABLE (7 << 26) +# define R500_ALPHA_OMOD_SHIFT 26 +# define R500_ALPHA_OMOD_IDENTITY (0 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_MUL_2 (1 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_MUL_4 (2 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_MUL_8 (3 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_DIV_2 (4 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_DIV_4 (5 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_DIV_8 (6 << R500_ALPHA_OMOD_SHIFT) +# define R500_ALPHA_OMOD_DISABLE (7 << R500_ALPHA_OMOD_SHIFT) # define R500_ALPHA_TARGET(x) ((x) << 29) # define R500_ALPHA_W_OMASK (1 << 31) #define R500_US_ALU_ALPHA_ADDR_0 0x9800 @@ -3191,14 +3214,15 @@ enum { # define R500_ALU_RGB_MOD_B_NEG (1 << 24) # define R500_ALU_RGB_MOD_B_ABS (2 << 24) # define R500_ALU_RGB_MOD_B_NAB (3 << 24) -# define R500_ALU_RGB_OMOD_IDENTITY (0 << 26) -# define R500_ALU_RGB_OMOD_MUL_2 (1 << 26) -# define R500_ALU_RGB_OMOD_MUL_4 (2 << 26) -# define R500_ALU_RGB_OMOD_MUL_8 (3 << 26) -# define R500_ALU_RGB_OMOD_DIV_2 (4 << 26) -# define R500_ALU_RGB_OMOD_DIV_4 (5 << 26) -# define R500_ALU_RGB_OMOD_DIV_8 (6 << 26) -# define R500_ALU_RGB_OMOD_DISABLE (7 << 26) +# define R500_ALU_RGB_OMOD_SHIFT 26 +# define R500_ALU_RGB_OMOD_IDENTITY (0 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_MUL_2 (1 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_MUL_4 (2 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_MUL_8 (3 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_DIV_2 (4 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_DIV_4 (5 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_DIV_8 (6 << R500_ALU_RGB_OMOD_SHIFT) +# define R500_ALU_RGB_OMOD_DISABLE (7 << R500_ALU_RGB_OMOD_SHIFT) # define R500_ALU_RGB_TARGET(x) ((x) << 29) # define R500_ALU_RGB_WMASK (1 << 31) #define R500_US_ALU_RGB_ADDR_0 0x9000 @@ -3221,7 +3245,8 @@ enum { # define R500_INST_TYPE_OUT (1 << 0) # define R500_INST_TYPE_FC (2 << 0) # define R500_INST_TYPE_TEX (3 << 0) -# define R500_INST_TEX_SEM_WAIT (1 << 2) +# define R500_INST_TEX_SEM_WAIT_SHIFT 2 +# define R500_INST_TEX_SEM_WAIT (1 << R500_INST_TEX_SEM_WAIT_SHIFT) # define R500_INST_RGB_PRED_SEL_NONE (0 << 3) # define R500_INST_RGB_PRED_SEL_RGBA (1 << 3) # define R500_INST_RGB_PRED_SEL_RRRR (2 << 3) @@ -3246,6 +3271,8 @@ enum { # define R500_INST_RGB_CLAMP (1 << 19) # define R500_INST_ALPHA_CLAMP (1 << 20) # define R500_INST_ALU_RESULT_SEL (1 << 21) +# define R500_INST_ALU_RESULT_SEL_RED (0 << 21) +# define R500_INST_ALU_RESULT_SEL_ALPHA (1 << 21) # define R500_INST_ALPHA_PRED_INV (1 << 22) # define R500_INST_ALU_RESULT_OP_EQ (0 << 23) # define R500_INST_ALU_RESULT_OP_LT (1 << 23) @@ -3257,7 +3284,7 @@ enum { # define R500_INST_ALPHA_PRED_SEL_GGGG (3 << 25) # define R500_INST_ALPHA_PRED_SEL_BBBB (4 << 25) # define R500_INST_ALPHA_PRED_SEL_AAAA (5 << 25) -/* XXX next four are kind of guessed */ +/* Next four are guessed, documentation doesn't mention order. */ # define R500_INST_STAT_WE_R (1 << 28) # define R500_INST_STAT_WE_G (1 << 29) # define R500_INST_STAT_WE_B (1 << 30) @@ -3401,7 +3428,8 @@ enum { # define R500_TEX_INST_LODBIAS (4 << 22) # define R500_TEX_INST_LOD (5 << 22) # define R500_TEX_INST_DXDY (6 << 22) -# define R500_TEX_SEM_ACQUIRE (1 << 25) +# define R500_TEX_SEM_ACQUIRE_SHIFT 25 +# define R500_TEX_SEM_ACQUIRE (1 << R500_TEX_SEM_ACQUIRE_SHIFT) # define R500_TEX_IGNORE_UNCOVERED (1 << 26) # define R500_TEX_UNSCALED (1 << 27) #define R300_US_W_FMT 0x46b4 @@ -3477,6 +3505,7 @@ enum { * 2. CLEAR_VALUE: Value to write into HIZ RAM. */ #define R300_PACKET3_3D_CLEAR_HIZ 0x00003700 +#define R300_PACKET3_3D_CLEAR_CMASK 0x00003800 /* Draws a set of primitives using vertex buffers pointed by the state data. * At least 2 Parameters: @@ -3501,19 +3530,13 @@ enum { /* * CP type-3 packets */ -#define R300_CP_CMD_BITBLT_MULTI 0xC0009B00 - -/* XXX Corbin's stuff from radeon and r200 */ - #define RADEON_WAIT_UNTIL 0x1720 # define RADEON_WAIT_CRTC_PFLIP (1 << 0) # define RADEON_WAIT_2D_IDLECLEAN (1 << 16) # define RADEON_WAIT_3D_IDLECLEAN (1 << 17) # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18) -#define R200_3D_DRAW_IMMD_2 0xC0003500 - -#define RADEON_CP_PACKET0 0x0 /* XXX stolen from radeon_reg.h */ +#define RADEON_CP_PACKET0 0x00000000 #define RADEON_CP_PACKET3 0xC0000000 #define RADEON_ONE_REG_WR (1 << 15)