X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fevergreen_compute.c;h=4483be358fa66ec45288ef7d0b1e8ae778c298d7;hb=0560c82ff6366edd1ffb52508839586e018457c6;hp=e36c3a8d8316447bea33f47a47d9df52890f856d;hpb=27c054edf0ae92c8c498830e7c7510fa94f5dcfd;p=mesa.git diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index e36c3a8d831..4483be358fa 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -30,7 +30,7 @@ #include "pipe/p_state.h" #include "pipe/p_context.h" #include "util/u_blitter.h" -#include "util/u_double_list.h" +#include "util/list.h" #include "util/u_transfer.h" #include "util/u_surface.h" #include "util/u_pack_color.h" @@ -39,7 +39,6 @@ #include "util/u_framebuffer.h" #include "pipebuffer/pb_buffer.h" #include "evergreend.h" -#include "r600_resource.h" #include "r600_shader.h" #include "r600_pipe.h" #include "r600_formats.h" @@ -48,8 +47,10 @@ #include "compute_memory_pool.h" #include "sb/sb_public.h" #ifdef HAVE_OPENCL -#include "radeon_llvm_util.h" +#include "radeon/radeon_llvm_util.h" #endif +#include "radeon/radeon_elf_util.h" +#include /** RAT0 is for global binding write @@ -82,29 +83,26 @@ writable images will consume TEX slots, VTX slots too because of linear indexing */ -struct r600_resource* r600_compute_buffer_alloc_vram( - struct r600_screen *screen, - unsigned size) +struct r600_resource *r600_compute_buffer_alloc_vram(struct r600_screen *screen, + unsigned size) { - struct pipe_resource * buffer = NULL; + struct pipe_resource *buffer = NULL; assert(size); - buffer = pipe_buffer_create( - (struct pipe_screen*) screen, - PIPE_BIND_CUSTOM, - PIPE_USAGE_IMMUTABLE, - size); + buffer = pipe_buffer_create((struct pipe_screen*) screen, + PIPE_BIND_CUSTOM, + PIPE_USAGE_IMMUTABLE, + size); return (struct r600_resource *)buffer; } -static void evergreen_set_rat( - struct r600_pipe_compute *pipe, - int id, - struct r600_resource* bo, - int start, - int size) +static void evergreen_set_rat(struct r600_pipe_compute *pipe, + unsigned id, + struct r600_resource *bo, + int start, + int size) { struct pipe_surface rat_templ; struct r600_surface *surf = NULL; @@ -144,11 +142,10 @@ static void evergreen_set_rat( evergreen_init_color_surface_rat(rctx, surf); } -static void evergreen_cs_set_vertex_buffer( - struct r600_context * rctx, - unsigned vb_index, - unsigned offset, - struct pipe_resource * buffer) +static void evergreen_cs_set_vertex_buffer(struct r600_context *rctx, + unsigned vb_index, + unsigned offset, + struct pipe_resource *buffer) { struct r600_vertexbuf_state *state = &rctx->cs_vertex_buffer_state; struct pipe_vertex_buffer *vb = &state->vb[vb_index]; @@ -162,15 +159,14 @@ static void evergreen_cs_set_vertex_buffer( rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE; state->enabled_mask |= 1 << vb_index; state->dirty_mask |= 1 << vb_index; - state->atom.dirty = true; + r600_mark_atom_dirty(rctx, &state->atom); } -static void evergreen_cs_set_constant_buffer( - struct r600_context * rctx, - unsigned cb_index, - unsigned offset, - unsigned size, - struct pipe_resource * buffer) +static void evergreen_cs_set_constant_buffer(struct r600_context *rctx, + unsigned cb_index, + unsigned offset, + unsigned size, + struct pipe_resource *buffer) { struct pipe_constant_buffer cb; cb.buffer_size = size; @@ -191,48 +187,119 @@ static const struct u_resource_vtbl r600_global_buffer_vtbl = r600_compute_global_transfer_inline_write /* transfer_inline_write */ }; +/* We need to define these R600 registers here, because we can't include + * evergreend.h and r600d.h. + */ +#define R_028868_SQ_PGM_RESOURCES_VS 0x028868 +#define R_028850_SQ_PGM_RESOURCES_PS 0x028850 + +#ifdef HAVE_OPENCL + +static void r600_shader_binary_read_config(const struct radeon_shader_binary *binary, + struct r600_bytecode *bc, + uint64_t symbol_offset, + boolean *use_kill) +{ + unsigned i; + const unsigned char *config = + radeon_shader_binary_config_start(binary, symbol_offset); + + for (i = 0; i < binary->config_size_per_symbol; i+= 8) { + unsigned reg = + util_le32_to_cpu(*(uint32_t*)(config + i)); + unsigned value = + util_le32_to_cpu(*(uint32_t*)(config + i + 4)); + switch (reg) { + /* R600 / R700 */ + case R_028850_SQ_PGM_RESOURCES_PS: + case R_028868_SQ_PGM_RESOURCES_VS: + /* Evergreen / Northern Islands */ + case R_028844_SQ_PGM_RESOURCES_PS: + case R_028860_SQ_PGM_RESOURCES_VS: + case R_0288D4_SQ_PGM_RESOURCES_LS: + bc->ngpr = MAX2(bc->ngpr, G_028844_NUM_GPRS(value)); + bc->nstack = MAX2(bc->nstack, G_028844_STACK_SIZE(value)); + break; + case R_02880C_DB_SHADER_CONTROL: + *use_kill = G_02880C_KILL_ENABLE(value); + break; + case R_0288E8_SQ_LDS_ALLOC: + bc->nlds_dw = value; + break; + } + } +} + +static unsigned r600_create_shader(struct r600_bytecode *bc, + const struct radeon_shader_binary *binary, + boolean *use_kill) -void *evergreen_create_compute_state( - struct pipe_context *ctx_, - const const struct pipe_compute_state *cso) +{ + assert(binary->code_size % 4 == 0); + bc->bytecode = CALLOC(1, binary->code_size); + memcpy(bc->bytecode, binary->code, binary->code_size); + bc->ndw = binary->code_size / 4; + + r600_shader_binary_read_config(binary, bc, 0, use_kill); + return 0; +} + +#endif + +static void r600_destroy_shader(struct r600_bytecode *bc) +{ + FREE(bc->bytecode); +} + +void *evergreen_create_compute_state(struct pipe_context *ctx_, + const const struct pipe_compute_state *cso) { struct r600_context *ctx = (struct r600_context *)ctx_; struct r600_pipe_compute *shader = CALLOC_STRUCT(r600_pipe_compute); - #ifdef HAVE_OPENCL - const struct pipe_llvm_program_header * header; - const unsigned char * code; - unsigned i; + const struct pipe_llvm_program_header *header; + const char *code; + void *p; + boolean use_kill; COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n"); - header = cso->prog; code = cso->prog + sizeof(struct pipe_llvm_program_header); + radeon_shader_binary_init(&shader->binary); + radeon_elf_read(code, header->num_bytes, &shader->binary); + r600_create_shader(&shader->bc, &shader->binary, &use_kill); + + shader->code_bo = r600_compute_buffer_alloc_vram(ctx->screen, + shader->bc.ndw * 4); + p = r600_buffer_map_sync_with_rings(&ctx->b, shader->code_bo, PIPE_TRANSFER_WRITE); + memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4); + ctx->b.ws->buffer_unmap(shader->code_bo->buf); #endif - shader->ctx = (struct r600_context*)ctx; + shader->ctx = ctx; shader->local_size = cso->req_local_mem; shader->private_size = cso->req_private_mem; shader->input_size = cso->req_input_mem; -#ifdef HAVE_OPENCL - shader->num_kernels = radeon_llvm_get_num_kernels(code, header->num_bytes); - shader->kernels = CALLOC(sizeof(struct r600_kernel), shader->num_kernels); - - for (i = 0; i < shader->num_kernels; i++) { - struct r600_kernel *kernel = &shader->kernels[i]; - kernel->llvm_module = radeon_llvm_get_kernel_module(i, code, - header->num_bytes); - } -#endif return shader; } -void evergreen_delete_compute_state(struct pipe_context *ctx, void* state) +void evergreen_delete_compute_state(struct pipe_context *ctx_, void *state) { - struct r600_pipe_compute *shader = (struct r600_pipe_compute *)state; + struct r600_context *ctx = (struct r600_context *)ctx_; + struct r600_pipe_compute *shader = state; + + COMPUTE_DBG(ctx->screen, "*** evergreen_delete_compute_state\n"); - free(shader); + if (!shader) + return; + + radeon_shader_binary_clean(&shader->binary); + r600_destroy_shader(&shader->bc); + + /* TODO destroy shader->code_bo, shader->const_bo + * we'll need something like r600_buffer_free */ + FREE(shader); } static void evergreen_bind_compute_state(struct pipe_context *ctx_, void *state) @@ -245,7 +312,7 @@ static void evergreen_bind_compute_state(struct pipe_context *ctx_, void *state) } /* The kernel parameters are stored a vtx buffer (ID=0), besides the explicit - * kernel parameters there are inplicit parameters that need to be stored + * kernel parameters there are implicit parameters that need to be stored * in the vertex buffer as well. Here is how these parameters are organized in * the buffer: * @@ -255,23 +322,22 @@ static void evergreen_bind_compute_state(struct pipe_context *ctx_, void *state) * (x,y,z) * DWORDS 9+ : Kernel parameters */ -void evergreen_compute_upload_input( - struct pipe_context *ctx_, - const uint *block_layout, - const uint *grid_layout, - const void *input) +void evergreen_compute_upload_input(struct pipe_context *ctx_, + const uint *block_layout, + const uint *grid_layout, + const void *input) { struct r600_context *ctx = (struct r600_context *)ctx_; struct r600_pipe_compute *shader = ctx->cs_shader_state.shader; - int i; + unsigned i; /* We need to reserve 9 dwords (36 bytes) for implicit kernel * parameters. */ unsigned input_size = shader->input_size + 36; - uint32_t * num_work_groups_start; - uint32_t * global_size_start; - uint32_t * local_size_start; - uint32_t * kernel_parameters_start; + uint32_t *num_work_groups_start; + uint32_t *global_size_start; + uint32_t *local_size_start; + uint32_t *kernel_parameters_start; struct pipe_box box; struct pipe_transfer *transfer = NULL; @@ -310,7 +376,7 @@ void evergreen_compute_upload_input( memcpy(kernel_parameters_start, input, shader->input_size); for (i = 0; i < (input_size / 4); i++) { - COMPUTE_DBG(ctx->screen, "input %i : %i\n", i, + COMPUTE_DBG(ctx->screen, "input %i : %u\n", i, ((unsigned*)num_work_groups_start)[i]); } @@ -321,19 +387,21 @@ void evergreen_compute_upload_input( (struct pipe_resource*)shader->kernel_param); } -static void evergreen_emit_direct_dispatch( - struct r600_context *rctx, - const uint *block_layout, const uint *grid_layout) +static void evergreen_emit_direct_dispatch(struct r600_context *rctx, + const uint *block_layout, + const uint *grid_layout) { int i; - struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; + struct radeon_winsys_cs *cs = rctx->b.gfx.cs; struct r600_pipe_compute *shader = rctx->cs_shader_state.shader; unsigned num_waves; - unsigned num_pipes = rctx->screen->b.info.r600_max_pipes; + unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; unsigned wave_divisor = (16 * num_pipes); int group_size = 1; int grid_size = 1; - unsigned lds_size = shader->local_size / 4 + shader->active_kernel->bc.nlds_dw; + unsigned lds_size = shader->local_size / 4 + + shader->bc.nlds_dw; + /* Calculate group_size/grid_size */ for (i = 0; i < 3; i++) { @@ -353,17 +421,17 @@ static void evergreen_emit_direct_dispatch( "allocating %u dwords lds.\n", num_pipes, num_waves, lds_size); - r600_write_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size); + radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size); - r600_write_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3); + radeon_set_config_reg_seq(cs, R_00899C_VGT_COMPUTE_START_X, 3); radeon_emit(cs, 0); /* R_00899C_VGT_COMPUTE_START_X */ radeon_emit(cs, 0); /* R_0089A0_VGT_COMPUTE_START_Y */ radeon_emit(cs, 0); /* R_0089A4_VGT_COMPUTE_START_Z */ - r600_write_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, + radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, group_size); - r600_write_compute_context_reg_seq(cs, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, 3); + radeon_compute_set_context_reg_seq(cs, R_0286EC_SPI_COMPUTE_NUM_THREAD_X, 3); radeon_emit(cs, block_layout[0]); /* R_0286EC_SPI_COMPUTE_NUM_THREAD_X */ radeon_emit(cs, block_layout[1]); /* R_0286F0_SPI_COMPUTE_NUM_THREAD_Y */ radeon_emit(cs, block_layout[2]); /* R_0286F4_SPI_COMPUTE_NUM_THREAD_Z */ @@ -376,7 +444,7 @@ static void evergreen_emit_direct_dispatch( assert(lds_size <= 8160); } - r600_write_compute_context_reg(cs, CM_R_0288E8_SQ_LDS_ALLOC, + radeon_compute_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_size | (num_waves << 14)); /* Dispatch packet */ @@ -388,16 +456,16 @@ static void evergreen_emit_direct_dispatch( radeon_emit(cs, 1); } -static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, - const uint *grid_layout) +static void compute_emit_cs(struct r600_context *ctx, + const uint *block_layout, + const uint *grid_layout) { - struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; - unsigned flush_flags = 0; - int i; + struct radeon_winsys_cs *cs = ctx->b.gfx.cs; + unsigned i; /* make sure that the gfx ring is only one active */ - if (ctx->b.rings.dma.cs) { - ctx->b.rings.dma.flush(ctx, RADEON_FLUSH_ASYNC); + if (ctx->b.dma.cs && ctx->b.dma.cs->cdw) { + ctx->b.dma.flush(ctx, RADEON_FLUSH_ASYNC, NULL); } /* Initialize all the compute-related registers. @@ -407,6 +475,10 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, */ r600_emit_command_buffer(cs, &ctx->start_compute_cs_cmd); + /* emit config state */ + if (ctx->b.chip_class == EVERGREEN) + r600_emit_atom(ctx, &ctx->config_state.atom); + ctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; r600_flush_emit(ctx); @@ -414,11 +486,12 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, /* XXX support more than 8 colorbuffers (the offsets are not a multiple of 0x3C for CB8-11) */ for (i = 0; i < 8 && i < ctx->framebuffer.state.nr_cbufs; i++) { struct r600_surface *cb = (struct r600_surface*)ctx->framebuffer.state.cbufs[i]; - unsigned reloc = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, + unsigned reloc = radeon_add_to_buffer_list(&ctx->b, &ctx->b.gfx, (struct r600_resource*)cb->base.texture, - RADEON_USAGE_READWRITE); + RADEON_USAGE_READWRITE, + RADEON_PRIO_SHADER_RW_BUFFER); - r600_write_compute_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7); + radeon_compute_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 7); radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */ radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */ radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */ @@ -430,27 +503,18 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ radeon_emit(cs, reloc); - if (!ctx->keep_tiling_flags) { - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */ - radeon_emit(cs, reloc); - } - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ radeon_emit(cs, reloc); } - if (ctx->keep_tiling_flags) { - for (; i < 8 ; i++) { - r600_write_compute_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); - } - for (; i < 12; i++) { - r600_write_compute_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, - S_028C70_FORMAT(V_028C70_COLOR_INVALID)); - } - } + for (; i < 8 ; i++) + radeon_compute_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, + S_028C70_FORMAT(V_028C70_COLOR_INVALID)); + for (; i < 12; i++) + radeon_compute_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, + S_028C70_FORMAT(V_028C70_COLOR_INVALID)); /* Set CB_TARGET_MASK XXX: Use cb_misc_state */ - r600_write_compute_context_reg(cs, R_028238_CB_TARGET_MASK, + radeon_compute_set_context_reg(cs, R_028238_CB_TARGET_MASK, ctx->compute_cb_target_mask); @@ -461,6 +525,12 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, /* Emit constant buffer state */ r600_emit_atom(ctx, &ctx->constbuf_state[PIPE_SHADER_COMPUTE].atom); + /* Emit sampler state */ + r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].states.atom); + + /* Emit sampler view (texture resource) state */ + r600_emit_atom(ctx, &ctx->samplers[PIPE_SHADER_COMPUTE].views.atom); + /* Emit compute shader state */ r600_emit_atom(ctx, &ctx->cs_shader_state.atom); @@ -475,6 +545,17 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, r600_flush_emit(ctx); ctx->b.flags = 0; + if (ctx->b.chip_class >= CAYMAN) { + cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); + cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CS_PARTIAL_FLUSH) | EVENT_INDEX(4); + /* DEALLOC_STATE prevents the GPU from hanging when a + * SURFACE_SYNC packet is emitted some time after a DISPATCH_DIRECT + * with any of the CB*_DEST_BASE_ENA or DB_DEST_BASE_ENA bits set. + */ + cs->buf[cs->cdw++] = PKT3C(PKT3_DEALLOC_STATE, 0, 0); + cs->buf[cs->cdw++] = 0; + } + #if 0 COMPUTE_DBG(ctx->screen, "cdw: %i\n", cs->cdw); for (i = 0; i < cs->cdw; i++) { @@ -488,84 +569,59 @@ static void compute_emit_cs(struct r600_context *ctx, const uint *block_layout, /** * Emit function for r600_cs_shader_state atom */ -void evergreen_emit_cs_shader( - struct r600_context *rctx, - struct r600_atom *atom) +void evergreen_emit_cs_shader(struct r600_context *rctx, + struct r600_atom *atom) { struct r600_cs_shader_state *state = (struct r600_cs_shader_state*)atom; struct r600_pipe_compute *shader = state->shader; - struct r600_kernel *kernel = &shader->kernels[state->kernel_index]; - struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; + struct radeon_winsys_cs *cs = rctx->b.gfx.cs; uint64_t va; + struct r600_resource *code_bo; + unsigned ngpr, nstack; - va = r600_resource_va(&rctx->screen->b.b, &kernel->code_bo->b.b); + code_bo = shader->code_bo; + va = shader->code_bo->gpu_address + state->pc; + ngpr = shader->bc.ngpr; + nstack = shader->bc.nstack; - r600_write_compute_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3); + radeon_compute_set_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3); radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */ radeon_emit(cs, /* R_0288D4_SQ_PGM_RESOURCES_LS */ - S_0288D4_NUM_GPRS(kernel->bc.ngpr) - | S_0288D4_STACK_SIZE(kernel->bc.nstack)); + S_0288D4_NUM_GPRS(ngpr) + | S_0288D4_STACK_SIZE(nstack)); radeon_emit(cs, 0); /* R_0288D8_SQ_PGM_RESOURCES_LS_2 */ radeon_emit(cs, PKT3C(PKT3_NOP, 0, 0)); - radeon_emit(cs, r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, - kernel->code_bo, RADEON_USAGE_READ)); + radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, + code_bo, RADEON_USAGE_READ, + RADEON_PRIO_USER_SHADER)); } -static void evergreen_launch_grid( - struct pipe_context *ctx_, - const uint *block_layout, const uint *grid_layout, - uint32_t pc, const void *input) +static void evergreen_launch_grid(struct pipe_context *ctx_, + const struct pipe_grid_info *info) { struct r600_context *ctx = (struct r600_context *)ctx_; - +#ifdef HAVE_OPENCL struct r600_pipe_compute *shader = ctx->cs_shader_state.shader; - struct r600_kernel *kernel = &shader->kernels[pc]; + boolean use_kill; - COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", pc); + ctx->cs_shader_state.pc = info->pc; + /* Get the config information for this kernel. */ + r600_shader_binary_read_config(&shader->binary, &shader->bc, + info->pc, &use_kill); +#endif -#ifdef HAVE_OPENCL + COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", info->pc); - if (!kernel->code_bo) { - void *p; - struct r600_bytecode *bc = &kernel->bc; - LLVMModuleRef mod = kernel->llvm_module; - boolean use_kill = false; - bool dump = (ctx->screen->b.debug_flags & DBG_CS) != 0; - unsigned use_sb = ctx->screen->b.debug_flags & DBG_SB_CS; - unsigned sb_disasm = use_sb || - (ctx->screen->b.debug_flags & DBG_SB_DISASM); - - r600_bytecode_init(bc, ctx->b.chip_class, ctx->b.family, - ctx->screen->has_compressed_msaa_texturing); - bc->type = TGSI_PROCESSOR_COMPUTE; - bc->isa = ctx->isa; - r600_llvm_compile(mod, ctx->b.family, bc, &use_kill, dump); - - if (dump && !sb_disasm) { - r600_bytecode_disasm(bc); - } else if ((dump && sb_disasm) || use_sb) { - if (r600_sb_bytecode_process(ctx, bc, NULL, dump, use_sb)) - R600_ERR("r600_sb_bytecode_process failed!\n"); - } - kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen, - kernel->bc.ndw * 4); - p = r600_buffer_map_sync_with_rings(&ctx->b, kernel->code_bo, PIPE_TRANSFER_WRITE); - memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4); - ctx->b.ws->buffer_unmap(kernel->code_bo->cs_buf); - } -#endif - shader->active_kernel = kernel; - ctx->cs_shader_state.kernel_index = pc; - evergreen_compute_upload_input(ctx_, block_layout, grid_layout, input); - compute_emit_cs(ctx, block_layout, grid_layout); + evergreen_compute_upload_input(ctx_, info->block, info->grid, info->input); + compute_emit_cs(ctx, info->block, info->grid); } -static void evergreen_set_compute_resources(struct pipe_context * ctx_, - unsigned start, unsigned count, - struct pipe_surface ** surfaces) +static void evergreen_set_compute_resources(struct pipe_context *ctx_, + unsigned start, unsigned count, + struct pipe_surface **surfaces) { struct r600_context *ctx = (struct r600_context *)ctx_; struct r600_surface **resources = (struct r600_surface **)surfaces; @@ -573,7 +629,7 @@ static void evergreen_set_compute_resources(struct pipe_context * ctx_, COMPUTE_DBG(ctx->screen, "*** evergreen_set_compute_resources: start = %u count = %u\n", start, count); - for (int i = 0; i < count; i++) { + for (unsigned i = 0; i < count; i++) { /* The First two vertex buffers are reserved for parameters and * global buffers. */ unsigned vtx_id = 2 + i; @@ -597,34 +653,16 @@ static void evergreen_set_compute_resources(struct pipe_context * ctx_, } } -static void evergreen_set_cs_sampler_view(struct pipe_context *ctx_, - unsigned start_slot, unsigned count, - struct pipe_sampler_view **views) -{ - struct r600_pipe_sampler_view **resource = - (struct r600_pipe_sampler_view **)views; - - for (int i = 0; i < count; i++) { - if (resource[i]) { - assert(i+1 < 12); - /* XXX: Implement */ - assert(!"Compute samplers not implemented."); - ///FETCH0 = VTX0 (param buffer), - //FETCH1 = VTX1 (global buffer pool), FETCH2... = TEX - } - } -} - - -static void evergreen_set_global_binding( - struct pipe_context *ctx_, unsigned first, unsigned n, - struct pipe_resource **resources, - uint32_t **handles) +static void evergreen_set_global_binding(struct pipe_context *ctx_, + unsigned first, unsigned n, + struct pipe_resource **resources, + uint32_t **handles) { struct r600_context *ctx = (struct r600_context *)ctx_; struct compute_memory_pool *pool = ctx->screen->global_pool; struct r600_resource_global **buffers = (struct r600_resource_global **)resources; + unsigned i; COMPUTE_DBG(ctx->screen, "*** evergreen_set_global_binding first = %u n = %u\n", first, n); @@ -634,14 +672,31 @@ static void evergreen_set_global_binding( return; } - compute_memory_finalize_pending(pool, ctx_); + /* We mark these items for promotion to the pool if they + * aren't already there */ + for (i = first; i < first + n; i++) { + struct compute_memory_item *item = buffers[i]->chunk; + + if (!is_item_in_pool(item)) + buffers[i]->chunk->status |= ITEM_FOR_PROMOTING; + } - for (int i = 0; i < n; i++) + if (compute_memory_finalize_pending(pool, ctx_) == -1) { + /* XXX: Unset */ + return; + } + + for (i = first; i < first + n; i++) { + uint32_t buffer_offset; + uint32_t handle; assert(resources[i]->target == PIPE_BUFFER); assert(resources[i]->bind & PIPE_BIND_GLOBAL); - *(handles[i]) = buffers[i]->chunk->start_in_dw * 4; + buffer_offset = util_le32_to_cpu(*(handles[i])); + handle = buffer_offset + buffers[i]->chunk->start_in_dw * 4; + + *(handles[i]) = util_cpu_to_le32(handle); } evergreen_set_rat(ctx->cs_shader_state.shader, 0, pool->bo, 0, pool->size_in_dw * 4); @@ -656,7 +711,7 @@ static void evergreen_set_global_binding( * command stream by the start_cs_cmd atom. However, since the SET_CONTEXT_REG * packet requires that the shader type bit be set, we must initialize all * context registers needed for compute in this function. The registers - * intialized by the start_cs_cmd atom can be found in evereen_state.c in the + * initialized by the start_cs_cmd atom can be found in evergreen_state.c in the * functions evergreen_init_atom_start_cs or cayman_init_atom_start_cs depending * on the GPU family. */ @@ -666,7 +721,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx) int num_threads; int num_stack_entries; - /* since all required registers are initialised in the + /* since all required registers are initialized in the * start_compute_cs_cmd atom, we can EMIT_EARLY here. */ r600_init_command_buffer(cb, 256); @@ -728,7 +783,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx) /* Config Registers */ if (ctx->b.chip_class < CAYMAN) - evergreen_init_common_regs(cb, ctx->b.chip_class, ctx->b.family, + evergreen_init_common_regs(ctx, cb, ctx->b.chip_class, ctx->b.family, ctx->screen->b.info.drm_minor); else cayman_init_common_regs(cb, ctx->b.chip_class, ctx->b.family, @@ -751,7 +806,7 @@ void evergreen_init_atom_start_compute_cs(struct r600_context *ctx) * R_008E28_SQ_STATIC_THREAD_MGMT3 */ - /* XXX: We may need to adjust the thread and stack resouce + /* XXX: We may need to adjust the thread and stack resource * values for 3D/compute interop */ r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5); @@ -848,18 +903,13 @@ void evergreen_init_compute_state_functions(struct r600_context *ctx) ctx->b.b.bind_compute_state = evergreen_bind_compute_state; // ctx->context.create_sampler_view = evergreen_compute_create_sampler_view; ctx->b.b.set_compute_resources = evergreen_set_compute_resources; - ctx->b.b.set_compute_sampler_views = evergreen_set_cs_sampler_view; ctx->b.b.set_global_binding = evergreen_set_global_binding; ctx->b.b.launch_grid = evergreen_launch_grid; - /* We always use at least one vertex buffer for parameters (id = 1)*/ - ctx->cs_vertex_buffer_state.enabled_mask = - ctx->cs_vertex_buffer_state.dirty_mask = 0x2; } -struct pipe_resource *r600_compute_global_buffer_create( - struct pipe_screen *screen, - const struct pipe_resource *templ) +struct pipe_resource *r600_compute_global_buffer_create(struct pipe_screen *screen, + const struct pipe_resource *templ) { struct r600_resource_global* result = NULL; struct r600_screen* rscreen = NULL; @@ -880,8 +930,8 @@ struct pipe_resource *r600_compute_global_buffer_create( templ->array_size); result->base.b.vtbl = &r600_global_buffer_vtbl; - result->base.b.b.screen = screen; result->base.b.b = *templ; + result->base.b.b.screen = screen; pipe_reference_init(&result->base.b.b.reference, 1); size_in_dw = (templ->width0+3) / 4; @@ -897,9 +947,8 @@ struct pipe_resource *r600_compute_global_buffer_create( return &result->base.b.b; } -void r600_compute_global_buffer_destroy( - struct pipe_screen *screen, - struct pipe_resource *res) +void r600_compute_global_buffer_destroy(struct pipe_screen *screen, + struct pipe_resource *res) { struct r600_resource_global* buffer = NULL; struct r600_screen* rscreen = NULL; @@ -916,29 +965,45 @@ void r600_compute_global_buffer_destroy( free(res); } -void *r600_compute_global_transfer_map( - struct pipe_context *ctx_, - struct pipe_resource *resource, - unsigned level, - unsigned usage, - const struct pipe_box *box, - struct pipe_transfer **ptransfer) +void *r600_compute_global_transfer_map(struct pipe_context *ctx_, + struct pipe_resource *resource, + unsigned level, + unsigned usage, + const struct pipe_box *box, + struct pipe_transfer **ptransfer) { struct r600_context *rctx = (struct r600_context*)ctx_; struct compute_memory_pool *pool = rctx->screen->global_pool; struct r600_resource_global* buffer = (struct r600_resource_global*)resource; + struct compute_memory_item *item = buffer->chunk; + struct pipe_resource *dst = NULL; + unsigned offset = box->x; + + if (is_item_in_pool(item)) { + compute_memory_demote_item(pool, item, ctx_); + } + else { + if (item->real_buffer == NULL) { + item->real_buffer = + r600_compute_buffer_alloc_vram(pool->screen, item->size_in_dw * 4); + } + } + + dst = (struct pipe_resource*)item->real_buffer; + + if (usage & PIPE_TRANSFER_READ) + buffer->chunk->status |= ITEM_MAPPED_FOR_READING; + COMPUTE_DBG(rctx->screen, "* r600_compute_global_transfer_map()\n" "level = %u, usage = %u, box(x = %u, y = %u, z = %u " "width = %u, height = %u, depth = %u)\n", level, usage, box->x, box->y, box->z, box->width, box->height, box->depth); - COMPUTE_DBG(rctx->screen, "Buffer: %u (buffer offset in global memory) " - "+ %u (box.x)\n", buffer->chunk->start_in_dw, box->x); - + COMPUTE_DBG(rctx->screen, "Buffer id = %"PRIi64" offset = " + "%u (box.x)\n", item->id, box->x); - compute_memory_finalize_pending(pool, ctx_); assert(resource->target == PIPE_BUFFER); assert(resource->bind & PIPE_BIND_GLOBAL); @@ -947,14 +1012,12 @@ void *r600_compute_global_transfer_map( assert(box->z == 0); ///TODO: do it better, mapping is not possible if the pool is too big - return pipe_buffer_map_range(ctx_, (struct pipe_resource*)buffer->chunk->pool->bo, - box->x + (buffer->chunk->start_in_dw * 4), - box->width, usage, ptransfer); + return pipe_buffer_map_range(ctx_, dst, + offset, box->width, usage, ptransfer); } -void r600_compute_global_transfer_unmap( - struct pipe_context *ctx_, - struct pipe_transfer* transfer) +void r600_compute_global_transfer_unmap(struct pipe_context *ctx_, + struct pipe_transfer *transfer) { /* struct r600_resource_global are not real resources, they just map * to an offset within the compute memory pool. The function @@ -969,23 +1032,21 @@ void r600_compute_global_transfer_unmap( assert (!"This function should not be called"); } -void r600_compute_global_transfer_flush_region( - struct pipe_context *ctx_, - struct pipe_transfer *transfer, - const struct pipe_box *box) +void r600_compute_global_transfer_flush_region(struct pipe_context *ctx_, + struct pipe_transfer *transfer, + const struct pipe_box *box) { assert(0 && "TODO"); } -void r600_compute_global_transfer_inline_write( - struct pipe_context *pipe, - struct pipe_resource *resource, - unsigned level, - unsigned usage, - const struct pipe_box *box, - const void *data, - unsigned stride, - unsigned layer_stride) +void r600_compute_global_transfer_inline_write(struct pipe_context *pipe, + struct pipe_resource *resource, + unsigned level, + unsigned usage, + const struct pipe_box *box, + const void *data, + unsigned stride, + unsigned layer_stride) { assert(0 && "TODO"); }