X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fevergreen_state.c;h=58d98a90550a4b18c4e6e08240e5d0bc9087281f;hb=8cdce30cc20983dcb971dd906a9a9007e282081d;hp=684eee7a355979021a32c0d2d3e1ccfd4ec09daa;hpb=12596cfd4cea4cff2bc067876d5ff25c54cdc874;p=mesa.git diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 684eee7a355..58d98a90550 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -35,13 +35,12 @@ static inline unsigned evergreen_array_mode(unsigned mode) { switch (mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: return V_028C70_ARRAY_LINEAR_ALIGNED; break; case RADEON_SURF_MODE_1D: return V_028C70_ARRAY_1D_TILED_THIN1; break; case RADEON_SURF_MODE_2D: return V_028C70_ARRAY_2D_TILED_THIN1; - default: - case RADEON_SURF_MODE_LINEAR: return V_028C70_ARRAY_LINEAR_GENERAL; } } @@ -213,13 +212,14 @@ static uint32_t r600_translate_dbformat(enum pipe_format format) static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) { - return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; + return r600_translate_texformat(screen, format, NULL, NULL, NULL, + FALSE) != ~0U; } static bool r600_is_colorbuffer_format_supported(enum chip_class chip, enum pipe_format format) { - return r600_translate_colorformat(chip, format) != ~0U && - r600_translate_colorswap(format) != ~0U; + return r600_translate_colorformat(chip, format, FALSE) != ~0U && + r600_translate_colorswap(format, FALSE) != ~0U; } static bool r600_is_zs_format_supported(enum pipe_format format) @@ -294,10 +294,10 @@ boolean evergreen_is_format_supported(struct pipe_screen *screen, retval |= PIPE_BIND_VERTEX_BUFFER; } - if (usage & PIPE_BIND_TRANSFER_READ) - retval |= PIPE_BIND_TRANSFER_READ; - if (usage & PIPE_BIND_TRANSFER_WRITE) - retval |= PIPE_BIND_TRANSFER_WRITE; + if ((usage & PIPE_BIND_LINEAR) && + !util_format_is_compressed(format) && + !(usage & PIPE_BIND_DEPTH_STENCIL)) + retval |= PIPE_BIND_LINEAR; return retval == usage; } @@ -404,7 +404,7 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx, unsigned db_depth_control, alpha_test_control, alpha_ref; struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); - if (dsa == NULL) { + if (!dsa) { return NULL; } @@ -461,12 +461,14 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, float psize_min, psize_max; struct r600_rasterizer_state *rs = CALLOC_STRUCT(r600_rasterizer_state); - if (rs == NULL) { + if (!rs) { return NULL; } r600_init_command_buffer(&rs->buffer, 30); + rs->scissor_enable = state->scissor; + rs->clip_halfz = state->clip_halfz; rs->flatshade = state->flatshade; rs->sprite_coord_enable = state->sprite_coord_enable; rs->two_side = state->light_twoside; @@ -475,7 +477,6 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; rs->pa_cl_clip_cntl = - S_028810_PS_UCP_MODE(3) | S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) | S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | @@ -487,6 +488,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, rs->offset_units = state->offset_units; rs->offset_scale = state->offset_scale * 16.0f; rs->offset_enable = state->offset_point || state->offset_line || state->offset_tri; + rs->offset_units_unscaled = state->offset_units_unscaled; if (state->point_size_per_vertex) { psize_min = util_get_min_point_size(state); @@ -523,7 +525,7 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, r600_store_context_reg(&rs->buffer, R_0286D4_SPI_INTERP_CONTROL_0, spi_interp); r600_store_context_reg(&rs->buffer, R_028A48_PA_SC_MODE_CNTL_0, S_028A48_MSAA_ENABLE(state->multisample) | - S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) | + S_028A48_VPORT_SCISSOR_ENABLE(1) | S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)); if (rctx->b.chip_class == CAYMAN) { @@ -555,10 +557,13 @@ static void *evergreen_create_rs_state(struct pipe_context *ctx, static void *evergreen_create_sampler_state(struct pipe_context *ctx, const struct pipe_sampler_state *state) { + struct r600_common_screen *rscreen = (struct r600_common_screen*)ctx->screen; struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); - unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0; + unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso + : state->max_anisotropy; + unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso); - if (ss == NULL) { + if (!ss) { return NULL; } @@ -569,10 +574,10 @@ static void *evergreen_create_sampler_state(struct pipe_context *ctx, S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | - S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | - S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | + S_03C000_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) | + S_03C000_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) | S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | - S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | + S_03C000_MAX_ANISO_RATIO(max_aniso_ratio) | S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | S_03C000_BORDER_COLOR_TYPE(ss->border_color_use ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ @@ -604,8 +609,8 @@ texture_buffer_sampler_view(struct r600_context *rctx, unsigned swizzle_res; unsigned char swizzle[4]; const struct util_format_description *desc; - unsigned offset = view->base.u.buf.first_element * stride; - unsigned size = (view->base.u.buf.last_element - view->base.u.buf.first_element + 1) * stride; + unsigned offset = view->base.u.buf.offset; + unsigned size = view->base.u.buf.size; swizzle[0] = view->base.swizzle_r; swizzle[1] = view->base.swizzle_g; @@ -643,7 +648,7 @@ texture_buffer_sampler_view(struct r600_context *rctx, view->tex_resource_words[7] = S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_BUFFER); if (tmp->resource.gpu_address) - LIST_ADDTAIL(&view->list, &rctx->b.texture_buffers); + LIST_ADDTAIL(&view->list, &rctx->texture_buffers); return &view->base; } @@ -668,8 +673,9 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, unsigned base_level, first_level, last_level; unsigned dim, last_layer; uint64_t va; + bool do_endian_swap = FALSE; - if (view == NULL) + if (!view) return NULL; /* initialize base object */ @@ -692,14 +698,16 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, surflevel = tmp->surface.level; /* Texturing with separate depth and stencil. */ - if (tmp->is_depth && !tmp->is_flushing_texture) { + if (tmp->db_compatible) { switch (pipe_format) { case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: pipe_format = PIPE_FORMAT_Z32_FLOAT; break; case PIPE_FORMAT_X8Z24_UNORM: case PIPE_FORMAT_S8_UINT_Z24_UNORM: - /* Z24 is always stored like this. */ + /* Z24 is always stored like this for DB + * compatibility. + */ pipe_format = PIPE_FORMAT_Z24X8_UNORM; break; case PIPE_FORMAT_X24S8_UINT: @@ -713,16 +721,19 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, } } + if (R600_BIG_ENDIAN) + do_endian_swap = !tmp->db_compatible; + format = r600_translate_texformat(ctx->screen, pipe_format, swizzle, - &word4, &yuv_format); + &word4, &yuv_format, do_endian_swap); assert(format != ~0); if (format == ~0) { FREE(view); return NULL; } - endian = r600_colorformat_endian_swap(format); + endian = r600_colorformat_endian_swap(format, do_endian_swap); base_level = 0; first_level = state->u.tex.first_level; @@ -744,6 +755,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, non_disp_tiling = tmp->non_disp_tiling; switch (surflevel[base_level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; break; @@ -753,10 +765,6 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, case RADEON_SURF_MODE_1D: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; - case RADEON_SURF_MODE_LINEAR: - default: - array_mode = V_028C70_ARRAY_LINEAR_GENERAL; - break; } macro_aspect = tmp->surface.mtilea; bankw = tmp->surface.bankw; @@ -772,7 +780,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, if (util_format_get_blocksize(pipe_format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); if (state->target == PIPE_TEXTURE_1D_ARRAY) { height = 1; @@ -844,10 +852,12 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples); view->tex_resource_words[6] |= S_030018_FMASK_BANK_HEIGHT(fmask_bankh); } else { + bool no_mip = first_level == last_level; + view->tex_resource_words[4] |= S_030010_BASE_LEVEL(first_level); view->tex_resource_words[5] |= S_030014_LAST_LEVEL(last_level); /* aniso max 16 samples */ - view->tex_resource_words[6] |= S_030018_MAX_ANISO(4); + view->tex_resource_words[6] |= S_030018_MAX_ANISO_RATIO(no_mip ? 0 : 4); } view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) | @@ -856,7 +866,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, S_03001C_BANK_HEIGHT(bankh) | S_03001C_MACRO_TILE_ASPECT(macro_aspect) | S_03001C_NUM_BANKS(nbanks) | - S_03001C_DEPTH_SAMPLE_ORDER(tmp->is_depth && !tmp->is_flushing_texture); + S_03001C_DEPTH_SAMPLE_ORDER(tmp->db_compatible); return &view->base; } @@ -869,6 +879,33 @@ evergreen_create_sampler_view(struct pipe_context *ctx, tex->width0, tex->height0, 0); } +static void evergreen_emit_config_state(struct r600_context *rctx, struct r600_atom *atom) +{ + struct radeon_winsys_cs *cs = rctx->b.gfx.cs; + struct r600_config_state *a = (struct r600_config_state*)atom; + + radeon_set_config_reg_seq(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, 3); + if (a->dyn_gpr_enabled) { + radeon_emit(cs, S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs)); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } else { + radeon_emit(cs, a->sq_gpr_resource_mgmt_1); + radeon_emit(cs, a->sq_gpr_resource_mgmt_2); + radeon_emit(cs, a->sq_gpr_resource_mgmt_3); + } + radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8)); + if (a->dyn_gpr_enabled) { + radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, + S_028838_PS_GPRS(0x1e) | + S_028838_VS_GPRS(0x1e) | + S_028838_GS_GPRS(0x1e) | + S_028838_ES_GPRS(0x1e) | + S_028838_HS_GPRS(0x1e) | + S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/ + } +} + static void evergreen_emit_clip_state(struct r600_context *rctx, struct r600_atom *atom) { struct radeon_winsys_cs *cs = rctx->b.gfx.cs; @@ -887,60 +924,12 @@ static void evergreen_get_scissor_rect(struct r600_context *rctx, unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y, uint32_t *tl, uint32_t *br) { - /* EG hw workaround */ - if (br_x == 0) - tl_x = 1; - if (br_y == 0) - tl_y = 1; + struct pipe_scissor_state scissor = {tl_x, tl_y, br_x, br_y}; - /* cayman hw workaround */ - if (rctx->b.chip_class == CAYMAN) { - if (br_x == 1 && br_y == 1) - br_x = 2; - } + evergreen_apply_scissor_bug_workaround(&rctx->b, &scissor); - *tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y); - *br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y); -} - -static void evergreen_set_scissor_states(struct pipe_context *ctx, - unsigned start_slot, - unsigned num_scissors, - const struct pipe_scissor_state *state) -{ - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_scissor_state *rstate = &rctx->scissor; - int i; - - for (i = start_slot; i < start_slot + num_scissors; i++) - rstate->scissor[i] = state[i - start_slot]; - rstate->dirty_mask |= ((1 << num_scissors) - 1) << start_slot; - rstate->atom.num_dw = util_bitcount(rstate->dirty_mask) * 4; - r600_mark_atom_dirty(rctx, &rstate->atom); -} - -static void evergreen_emit_scissor_state(struct r600_context *rctx, struct r600_atom *atom) -{ - struct radeon_winsys_cs *cs = rctx->b.gfx.cs; - struct r600_scissor_state *rstate = &rctx->scissor; - struct pipe_scissor_state *state; - uint32_t dirty_mask; - unsigned i, offset; - uint32_t tl, br; - - dirty_mask = rstate->dirty_mask; - while (dirty_mask != 0) { - i = u_bit_scan(&dirty_mask); - state = &rstate->scissor[i]; - evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br); - - offset = i * 4 * 2; - radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset, 2); - radeon_emit(cs, tl); - radeon_emit(cs, br); - } - rstate->dirty_mask = 0; - rstate->atom.num_dw = 0; + *tl = S_028240_TL_X(scissor.minx) | S_028240_TL_Y(scissor.miny); + *br = S_028244_BR_X(scissor.maxx) | S_028244_BR_Y(scissor.maxy); } /** @@ -953,22 +942,15 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx, { struct pipe_resource *pipe_buffer = surf->base.texture; unsigned format = r600_translate_colorformat(rctx->b.chip_class, - surf->base.format); - unsigned endian = r600_colorformat_endian_swap(format); - unsigned swap = r600_translate_colorswap(surf->base.format); + surf->base.format, FALSE); + unsigned endian = r600_colorformat_endian_swap(format, FALSE); + unsigned swap = r600_translate_colorswap(surf->base.format, FALSE); unsigned block_size = align(util_format_get_blocksize(pipe_buffer->format), 4); unsigned pitch_alignment = - MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size); + MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size); unsigned pitch = align(pipe_buffer->width0, pitch_alignment); - /* XXX: This is copied from evergreen_init_color_surface(). I don't - * know why this is necessary. - */ - if (pipe_buffer->usage == PIPE_USAGE_STAGING) { - endian = ENDIAN_NONE; - } - surf->cb_color_base = r600_resource(pipe_buffer)->gpu_address >> 8; surf->cb_color_pitch = (pitch / 8) - 1; @@ -1015,17 +997,11 @@ void evergreen_init_color_surface(struct r600_context *rctx, unsigned non_disp_tiling, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; const struct util_format_description *desc; int i; - bool blend_clamp = 0, blend_bypass = 0; + bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE; offset = rtex->surface.level[level].offset; - if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) { - assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer); - offset += rtex->surface.level[level].slice_size * - surf->base.u.tex.first_layer; - color_view = 0; - } else - color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | - S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); + color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) | + S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer); pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; @@ -1034,6 +1010,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, } color_info = 0; switch (rtex->surface.level[level].mode) { + default: case RADEON_SURF_MODE_LINEAR_ALIGNED: color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED); non_disp_tiling = 1; @@ -1046,11 +1023,6 @@ void evergreen_init_color_surface(struct r600_context *rctx, color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1); non_disp_tiling = rtex->non_disp_tiling; break; - case RADEON_SURF_MODE_LINEAR: - default: - color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL); - non_disp_tiling = 1; - break; } tile_split = rtex->surface.tile_split; macro_aspect = rtex->surface.mtilea; @@ -1071,7 +1043,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, if (util_format_get_blocksize(surf->base.format) >= 16) non_disp_tiling = 1; } - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); desc = util_format_description(surf->base.format); for (i = 0; i < 4; i++) { if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { @@ -1089,7 +1061,7 @@ void evergreen_init_color_surface(struct r600_context *rctx, if (rctx->b.chip_class == CAYMAN) { color_attrib |= S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == - UTIL_FORMAT_SWIZZLE_1); + PIPE_SWIZZLE_1); if (rtex->resource.b.b.nr_samples > 1) { unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples); @@ -1113,17 +1085,17 @@ void evergreen_init_color_surface(struct r600_context *rctx, ntype = V_028C70_NUMBER_UINT; } - format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format); + if (R600_BIG_ENDIAN) + do_endian_swap = !rtex->db_compatible; + + format = r600_translate_colorformat(rctx->b.chip_class, surf->base.format, + do_endian_swap); assert(format != ~0); - swap = r600_translate_colorswap(surf->base.format); + swap = r600_translate_colorswap(surf->base.format, do_endian_swap); assert(swap != ~0); - if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { - endian = ENDIAN_NONE; - } else { - endian = r600_colorformat_endian_swap(format); - } + endian = r600_colorformat_endian_swap(format, do_endian_swap); /* blend clamp should be set for all NORM/SRGB types */ if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM || @@ -1213,7 +1185,6 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, break; case RADEON_SURF_MODE_1D: case RADEON_SURF_MODE_LINEAR_ALIGNED: - case RADEON_SURF_MODE_LINEAR: default: array_mode = V_028C70_ARRAY_1D_TILED_THIN1; break; @@ -1226,7 +1197,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, macro_aspect = eg_macro_tile_aspect(macro_aspect); bankw = eg_bank_wh(bankw); bankh = eg_bank_wh(bankh); - nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rscreen->b.info.r600_num_banks); offset >>= 8; surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | @@ -1250,27 +1221,6 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x * levelinfo->nblk_y / 64 - 1); - switch (surf->base.format) { - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - surf->pa_su_poly_offset_db_fmt_cntl = - S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); - break; - case PIPE_FORMAT_Z32_FLOAT: - case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: - surf->pa_su_poly_offset_db_fmt_cntl = - S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | - S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); - break; - case PIPE_FORMAT_Z16_UNORM: - surf->pa_su_poly_offset_db_fmt_cntl = - S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); - break; - default:; - } - if (rtex->surface.flags & RADEON_SURF_SBUFFER) { uint64_t stencil_offset; unsigned stile_split = rtex->surface.stencil_tile_split; @@ -1314,20 +1264,17 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, struct r600_texture *rtex; uint32_t i, log_samples; - if (rctx->framebuffer.state.nr_cbufs) { - rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | - R600_CONTEXT_FLUSH_AND_INV_CB_META; - } - if (rctx->framebuffer.state.zsbuf) { - rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | R600_CONTEXT_FLUSH_AND_INV; - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB; - - rtex = (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture; - if (rtex->htile_buffer) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META; - } - } + /* Flush TC when changing the framebuffer state, because the only + * client not using TC that can change textures is the framebuffer. + * Other places don't typically have to flush TC. + */ + rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE | + R600_CONTEXT_FLUSH_AND_INV | + R600_CONTEXT_FLUSH_AND_INV_CB | + R600_CONTEXT_FLUSH_AND_INV_CB_META | + R600_CONTEXT_FLUSH_AND_INV_DB | + R600_CONTEXT_FLUSH_AND_INV_DB_META | + R600_CONTEXT_INV_TEX_CACHE; util_copy_framebuffer_state(&rctx->framebuffer.state, state); @@ -1439,15 +1386,13 @@ static void evergreen_set_framebuffer_state(struct pipe_context *ctx, /* Colorbuffers. */ rctx->framebuffer.atom.num_dw += state->nr_cbufs * 23; - if (rctx->keep_tiling_flags) - rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2; + rctx->framebuffer.atom.num_dw += state->nr_cbufs * 2; rctx->framebuffer.atom.num_dw += (12 - state->nr_cbufs) * 3; /* ZS buffer. */ if (state->zsbuf) { rctx->framebuffer.atom.num_dw += 24; - if (rctx->keep_tiling_flags) - rctx->framebuffer.atom.num_dw += 2; + rctx->framebuffer.atom.num_dw += 2; } else if (rctx->screen->b.info.drm_minor >= 18) { rctx->framebuffer.atom.num_dw += 4; } @@ -1533,18 +1478,18 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, nr_samples = 0; break; case 2: - radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_2x)); - radeon_emit_array(cs, eg_sample_locs_2x, Elements(eg_sample_locs_2x)); + radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_2x)); + radeon_emit_array(cs, eg_sample_locs_2x, ARRAY_SIZE(eg_sample_locs_2x)); max_dist = eg_max_dist_2x; break; case 4: - radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(eg_sample_locs_4x)); - radeon_emit_array(cs, eg_sample_locs_4x, Elements(eg_sample_locs_4x)); + radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(eg_sample_locs_4x)); + radeon_emit_array(cs, eg_sample_locs_4x, ARRAY_SIZE(eg_sample_locs_4x)); max_dist = eg_max_dist_4x; break; case 8: - radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, Elements(sample_locs_8x)); - radeon_emit_array(cs, sample_locs_8x, Elements(sample_locs_8x)); + radeon_set_context_reg_seq(cs, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0, ARRAY_SIZE(sample_locs_8x)); + radeon_emit_array(cs, sample_locs_8x, ARRAY_SIZE(sample_locs_8x)); max_dist = max_dist_8x; break; } @@ -1555,12 +1500,17 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1)); + radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) | + EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); } else { radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ - radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0); + radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, + EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); } } @@ -1624,11 +1574,6 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C60_CB_COLOR0_BASE */ radeon_emit(cs, reloc); - if (!rctx->keep_tiling_flags) { - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */ - radeon_emit(cs, reloc); - } - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C74_CB_COLOR0_ATTRIB */ radeon_emit(cs, reloc); @@ -1642,27 +1587,12 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r if (i == 1 && state->cbufs[0]) { radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, cb->cb_color_info | tex->cb_color_info); - - if (!rctx->keep_tiling_flags) { - unsigned reloc = radeon_add_to_buffer_list(&rctx->b, - &rctx->b.gfx, - (struct r600_resource*)state->cbufs[0]->texture, - RADEON_USAGE_READWRITE, - RADEON_PRIO_COLOR_BUFFER); - - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028C70_CB_COLOR0_INFO */ - radeon_emit(cs, reloc); - } i++; } - if (rctx->keep_tiling_flags) { - for (; i < 8 ; i++) { - radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); - } - for (; i < 12; i++) { - radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0); - } - } + for (; i < 8 ; i++) + radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); + for (; i < 12; i++) + radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0); /* ZS buffer. */ if (state->zsbuf) { @@ -1675,8 +1605,6 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r RADEON_PRIO_DEPTH_BUFFER_MSAA : RADEON_PRIO_DEPTH_BUFFER); - radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, - zb->pa_su_poly_offset_db_fmt_cntl); radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8); @@ -1689,11 +1617,6 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */ radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */ - if (!rctx->keep_tiling_flags) { - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028040_DB_Z_INFO */ - radeon_emit(cs, reloc); - } - radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); /* R_028048_DB_Z_READ_BASE */ radeon_emit(cs, reloc); @@ -1723,8 +1646,14 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r if (rctx->b.chip_class == EVERGREEN) { evergreen_emit_msaa_state(rctx, rctx->framebuffer.nr_samples, rctx->ps_iter_samples); } else { - cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples); - cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, rctx->ps_iter_samples, 0); + unsigned sc_mode_cntl_1 = + EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1); + + if (rctx->framebuffer.nr_samples > 1) + cayman_emit_msaa_sample_locs(cs, rctx->framebuffer.nr_samples); + cayman_emit_msaa_config(cs, rctx->framebuffer.nr_samples, + rctx->ps_iter_samples, 0, sc_mode_cntl_1); } } @@ -1734,18 +1663,28 @@ static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600 struct r600_poly_offset_state *state = (struct r600_poly_offset_state*)a; float offset_units = state->offset_units; float offset_scale = state->offset_scale; + uint32_t pa_su_poly_offset_db_fmt_cntl = 0; - switch (state->zs_format) { - case PIPE_FORMAT_Z24X8_UNORM: - case PIPE_FORMAT_Z24_UNORM_S8_UINT: - case PIPE_FORMAT_X8Z24_UNORM: - case PIPE_FORMAT_S8_UINT_Z24_UNORM: - offset_units *= 2.0f; - break; - case PIPE_FORMAT_Z16_UNORM: - offset_units *= 4.0f; - break; - default:; + if (!state->offset_units_unscaled) { + switch (state->zs_format) { + case PIPE_FORMAT_Z24X8_UNORM: + case PIPE_FORMAT_Z24_UNORM_S8_UINT: + case PIPE_FORMAT_X8Z24_UNORM: + case PIPE_FORMAT_S8_UINT_Z24_UNORM: + offset_units *= 2.0f; + pa_su_poly_offset_db_fmt_cntl = + S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24); + break; + case PIPE_FORMAT_Z16_UNORM: + offset_units *= 4.0f; + pa_su_poly_offset_db_fmt_cntl = + S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16); + break; + default: + pa_su_poly_offset_db_fmt_cntl = + S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) | + S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); + } } radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 4); @@ -1753,6 +1692,9 @@ static void evergreen_emit_polygon_offset(struct r600_context *rctx, struct r600 radeon_emit(cs, fui(offset_units)); radeon_emit(cs, fui(offset_scale)); radeon_emit(cs, fui(offset_units)); + + radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, + pa_su_poly_offset_db_fmt_cntl); } static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) @@ -1785,8 +1727,8 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rtex->htile_buffer, RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = reloc_idx; + radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); + radeon_emit(cs, reloc_idx); } else { radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, 0); radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0); @@ -1801,38 +1743,26 @@ static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_ unsigned db_count_control = 0; unsigned db_render_override = S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | - S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) | - /* There is a hang with HTILE if stencil is used and - * fast stencil is enabled. */ - S_02800C_FAST_STENCIL_DISABLE(1); + S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); - if (a->occlusion_query_enabled) { + if (rctx->b.num_occlusion_queries > 0 && + !a->occlusion_queries_disabled) { db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1); if (rctx->b.chip_class == CAYMAN) { db_count_control |= S_028004_SAMPLE_RATE(a->log_samples); } db_render_override |= S_02800C_NOOP_CULL_DISABLE(1); - } - /* FIXME we should be able to use hyperz even if we are not writing to - * zbuffer but somehow this trigger GPU lockup. See : - * - * https://bugs.freedesktop.org/show_bug.cgi?id=60848 - * - * Disable hyperz for now if not writing to zbuffer. - */ - if (rctx->db_state.rsurf && rctx->db_state.rsurf->db_htile_surface && rctx->zwritemask) { - /* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL */ - db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF); - /* This is to fix a lockup when hyperz and alpha test are enabled at - * the same time somehow GPU get confuse on which order to pick for - * z test - */ - if (rctx->alphatest_state.sx_alpha_test_control) { - db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1); - } } else { - db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE); + db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1); } + + /* This is to fix a lockup when hyperz and alpha test are enabled at + * the same time somehow GPU get confuse on which order to pick for + * z test + */ + if (rctx->alphatest_state.sx_alpha_test_control) + db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1); + if (a->flush_depthstencil_through_cb) { assert(a->copy_depth || a->copy_stencil); @@ -1939,7 +1869,7 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, if (!gs_ring_buffer) { radeon_set_context_reg_flag(cs, reg_alu_constbuf_size + buffer_index * 4, - ALIGN_DIVUP(cb->buffer_size >> 4, 16), pkt_flags); + DIV_ROUND_UP(cb->buffer_size, 256), pkt_flags); radeon_set_context_reg_flag(cs, reg_alu_const_cache + buffer_index * 4, va >> 8, pkt_flags); } @@ -1978,13 +1908,22 @@ static void evergreen_emit_constant_buffers(struct r600_context *rctx, state->dirty_mask = 0; } +/* VS constants can be in VS/ES (same space) or LS if tess is enabled */ static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) { - evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], - EG_FETCH_CONSTANTS_OFFSET_VS, - R_028180_ALU_CONST_BUFFER_SIZE_VS_0, - R_028980_ALU_CONST_CACHE_VS_0, - 0 /* PKT3 flags */); + if (rctx->vs_shader->current->shader.vs_as_ls) { + evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], + EG_FETCH_CONSTANTS_OFFSET_LS, + R_028FC0_ALU_CONST_BUFFER_SIZE_LS_0, + R_028F40_ALU_CONST_CACHE_LS_0, + 0 /* PKT3 flags */); + } else { + evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX], + EG_FETCH_CONSTANTS_OFFSET_VS, + R_028180_ALU_CONST_BUFFER_SIZE_VS_0, + R_028980_ALU_CONST_CACHE_VS_0, + 0 /* PKT3 flags */); + } } static void evergreen_emit_gs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) @@ -2014,6 +1953,29 @@ static void evergreen_emit_cs_constant_buffers(struct r600_context *rctx, struct RADEON_CP_PACKET3_COMPUTE_MODE); } +/* tes constants can be emitted to VS or ES - which are common */ +static void evergreen_emit_tes_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) +{ + if (!rctx->tes_shader) + return; + evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL], + EG_FETCH_CONSTANTS_OFFSET_VS, + R_028180_ALU_CONST_BUFFER_SIZE_VS_0, + R_028980_ALU_CONST_CACHE_VS_0, + 0); +} + +static void evergreen_emit_tcs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) +{ + if (!rctx->tes_shader) + return; + evergreen_emit_constant_buffers(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL], + EG_FETCH_CONSTANTS_OFFSET_HS, + R_028F80_ALU_CONST_BUFFER_SIZE_HS_0, + R_028F00_ALU_CONST_CACHE_HS_0, + 0); +} + static void evergreen_emit_sampler_views(struct r600_context *rctx, struct r600_samplerview_state *state, unsigned resource_id_base, unsigned pkt_flags) @@ -2049,8 +2011,13 @@ static void evergreen_emit_sampler_views(struct r600_context *rctx, static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) { - evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, - EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0); + if (rctx->vs_shader->current->shader.vs_as_ls) { + evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, + EG_FETCH_CONSTANTS_OFFSET_LS + R600_MAX_CONST_BUFFERS, 0); + } else { + evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views, + EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0); + } } static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) @@ -2059,6 +2026,18 @@ static void evergreen_emit_gs_sampler_views(struct r600_context *rctx, struct r6 EG_FETCH_CONSTANTS_OFFSET_GS + R600_MAX_CONST_BUFFERS, 0); } +static void evergreen_emit_tcs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) +{ + evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views, + EG_FETCH_CONSTANTS_OFFSET_HS + R600_MAX_CONST_BUFFERS, 0); +} + +static void evergreen_emit_tes_sampler_views(struct r600_context *rctx, struct r600_atom *atom) +{ + evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views, + EG_FETCH_CONSTANTS_OFFSET_VS + R600_MAX_CONST_BUFFERS, 0); +} + static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) { evergreen_emit_sampler_views(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views, @@ -2102,8 +2081,13 @@ static void evergreen_emit_sampler_states(struct r600_context *rctx, static void evergreen_emit_vs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) { - evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, - R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0); + if (rctx->vs_shader->current->shader.vs_as_ls) { + evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 72, + R_00A450_TD_LS_SAMPLER0_BORDER_COLOR_INDEX, 0); + } else { + evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_VERTEX], 18, + R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0); + } } static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) @@ -2112,6 +2096,18 @@ static void evergreen_emit_gs_sampler_states(struct r600_context *rctx, struct r R_00A428_TD_GS_SAMPLER0_BORDER_INDEX, 0); } +static void evergreen_emit_tcs_sampler_states(struct r600_context *rctx, struct r600_atom *atom) +{ + evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL], 54, + R_00A43C_TD_HS_SAMPLER0_BORDER_COLOR_INDEX, 0); +} + +static void evergreen_emit_tes_sampler_states(struct r600_context *rctx, struct r600_atom *atom) +{ + evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL], 18, + R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, 0); +} + static void evergreen_emit_ps_sampler_states(struct r600_context *rctx, struct r600_atom *atom) { evergreen_emit_sampler_states(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT], 0, @@ -2156,7 +2152,7 @@ static void evergreen_emit_vertex_fetch_shader(struct r600_context *rctx, struct radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, shader->buffer, RADEON_USAGE_READ, - RADEON_PRIO_INTERNAL_SHADER)); + RADEON_PRIO_SHADER_BINARY)); } static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_atom *a) @@ -2164,7 +2160,7 @@ static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_ struct radeon_winsys_cs *cs = rctx->b.gfx.cs; struct r600_shader_stages_state *state = (struct r600_shader_stages_state*)a; - uint32_t v = 0, v2 = 0, primid = 0; + uint32_t v = 0, v2 = 0, primid = 0, tf_param = 0; if (rctx->vs_shader->current->shader.vs_as_gs_a) { v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_A); @@ -2182,9 +2178,11 @@ static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_ cut_val = V_028A40_GS_CUT_512; else cut_val = V_028A40_GS_CUT_1024; - v = S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | - S_028B54_GS_EN(1) | - S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); + + v = S_028B54_GS_EN(1) | + S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER); + if (!rctx->tes_shader) + v |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL); v2 = S_028A40_MODE(V_028A40_GS_SCENARIO_G) | S_028A40_CUT_MODE(cut_val); @@ -2193,9 +2191,72 @@ static void evergreen_emit_shader_stages(struct r600_context *rctx, struct r600_ primid = 1; } + if (rctx->tes_shader) { + uint32_t type, partitioning, topology; + struct tgsi_shader_info *info = &rctx->tes_shader->current->selector->info; + unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE]; + unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING]; + bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW]; + bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE]; + switch (tes_prim_mode) { + case PIPE_PRIM_LINES: + type = V_028B6C_TESS_ISOLINE; + break; + case PIPE_PRIM_TRIANGLES: + type = V_028B6C_TESS_TRIANGLE; + break; + case PIPE_PRIM_QUADS: + type = V_028B6C_TESS_QUAD; + break; + default: + assert(0); + return; + } + + switch (tes_spacing) { + case PIPE_TESS_SPACING_FRACTIONAL_ODD: + partitioning = V_028B6C_PART_FRAC_ODD; + break; + case PIPE_TESS_SPACING_FRACTIONAL_EVEN: + partitioning = V_028B6C_PART_FRAC_EVEN; + break; + case PIPE_TESS_SPACING_EQUAL: + partitioning = V_028B6C_PART_INTEGER; + break; + default: + assert(0); + return; + } + + if (tes_point_mode) + topology = V_028B6C_OUTPUT_POINT; + else if (tes_prim_mode == PIPE_PRIM_LINES) + topology = V_028B6C_OUTPUT_LINE; + else if (tes_vertex_order_cw) + /* XXX follow radeonsi and invert */ + topology = V_028B6C_OUTPUT_TRIANGLE_CCW; + else + topology = V_028B6C_OUTPUT_TRIANGLE_CW; + + tf_param = S_028B6C_TYPE(type) | + S_028B6C_PARTITIONING(partitioning) | + S_028B6C_TOPOLOGY(topology); + } + + if (rctx->tes_shader) { + v |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | + S_028B54_HS_EN(1); + if (!state->geom_enable) + v |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS); + else + v |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS); + } + + radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, v ? 1 : 0 ); radeon_set_context_reg(cs, R_028B54_VGT_SHADER_STAGES_EN, v); radeon_set_context_reg(cs, R_028A40_VGT_GS_MODE, v2); radeon_set_context_reg(cs, R_028A84_VGT_PRIMITIVEID_EN, primid); + radeon_set_context_reg(cs, R_028B6C_VGT_TF_PARAM, tf_param); } static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom *a) @@ -2215,7 +2276,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_RINGS_STREAMOUT)); + RADEON_PRIO_SHADER_RINGS)); radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, state->esgs_ring.buffer_size >> 8); @@ -2225,7 +2286,7 @@ static void evergreen_emit_gs_rings(struct r600_context *rctx, struct r600_atom radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, rbuffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_RINGS_STREAMOUT)); + RADEON_PRIO_SHADER_RINGS)); radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, state->gsvs_ring.buffer_size >> 8); } else { @@ -2264,9 +2325,9 @@ void cayman_init_common_regs(struct r600_command_buffer *cb, static void cayman_init_atom_start_cs(struct r600_context *rctx) { struct r600_command_buffer *cb = &rctx->start_cs_cmd; - int tmp, i; + int i; - r600_init_command_buffer(cb, 320); + r600_init_command_buffer(cb, 338); /* This must be first. */ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); @@ -2277,12 +2338,24 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); + /* This enables pipeline stat & streamout queries. + * They are only disabled by blits. + */ + r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); + r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); + cayman_init_common_regs(cb, rctx->b.chip_class, rctx->b.family, rctx->screen->b.info.drm_minor); r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); + /* remove LS/HS from one SIMD for hw workaround */ + r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3); + r600_store_value(cb, 0xffffffff); + r600_store_value(cb, 0xffffffff); + r600_store_value(cb, 0xfffffffe); + r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6); r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */ r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */ @@ -2300,9 +2373,9 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ - r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ + r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ + r600_store_value(cb, fui(0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ + r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ @@ -2314,18 +2387,14 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0); - r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2); - r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */ - r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ - r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2); r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */ r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */ - r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2); - r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */ + r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2); + r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */ r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */ r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0); @@ -2348,21 +2417,9 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); - r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS); - for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) { - r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ - r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ - } - r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); - r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4); - r600_store_value(cb, fui(1.0)); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */ - r600_store_value(cb, fui(1.0)); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */ - r600_store_value(cb, fui(1.0)); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */ - r600_store_value(cb, fui(1.0)); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */ - r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ @@ -2375,6 +2432,9 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); + r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); + r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); + r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); /* to avoid GPU doing any preloading of constant from random address */ @@ -2408,17 +2468,22 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2); r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ - r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0); + r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2); + r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ + r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ + r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF); } -void evergreen_init_common_regs(struct r600_command_buffer *cb, - enum chip_class ctx_chip_class, - enum radeon_family ctx_family, - int ctx_drm_minor) +void evergreen_init_common_regs(struct r600_context *rctx, struct r600_command_buffer *cb, + enum chip_class ctx_chip_class, + enum radeon_family ctx_family, + int ctx_drm_minor) { int ps_prio; int vs_prio; @@ -2429,31 +2494,23 @@ void evergreen_init_common_regs(struct r600_command_buffer *cb, int cs_prio; int ls_prio; - int num_ps_gprs; - int num_vs_gprs; - int num_gs_gprs; - int num_es_gprs; - int num_hs_gprs; - int num_ls_gprs; - int num_temp_gprs; - unsigned tmp; ps_prio = 0; vs_prio = 1; gs_prio = 2; es_prio = 3; - hs_prio = 0; - ls_prio = 0; + hs_prio = 3; + ls_prio = 3; cs_prio = 0; - num_ps_gprs = 93; - num_vs_gprs = 46; - num_temp_gprs = 4; - num_gs_gprs = 31; - num_es_gprs = 31; - num_hs_gprs = 23; - num_ls_gprs = 23; + rctx->default_gprs[R600_HW_STAGE_PS] = 93; + rctx->default_gprs[R600_HW_STAGE_VS] = 46; + rctx->r6xx_num_clause_temp_gprs = 4; + rctx->default_gprs[R600_HW_STAGE_GS] = 31; + rctx->default_gprs[R600_HW_STAGE_ES] = 31; + rctx->default_gprs[EG_HW_STAGE_HS] = 23; + rctx->default_gprs[EG_HW_STAGE_LS] = 23; tmp = 0; switch (ctx_family) { @@ -2476,40 +2533,12 @@ void evergreen_init_common_regs(struct r600_command_buffer *cb, tmp |= S_008C00_GS_PRIO(gs_prio); tmp |= S_008C00_ES_PRIO(es_prio); - /* enable dynamic GPR resource management */ - if (ctx_drm_minor >= 7) { - r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2); - r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */ - /* always set temp clauses */ - r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */ - r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2); - r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */ - r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */ - r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8)); - r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, - S_028838_PS_GPRS(0x1e) | - S_028838_VS_GPRS(0x1e) | - S_028838_GS_GPRS(0x1e) | - S_028838_ES_GPRS(0x1e) | - S_028838_HS_GPRS(0x1e) | - S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/ - } else { - r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4); - r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */ + r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 1); + r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */ - tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs); - tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); - tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); - r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */ - - tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); - tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); - r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */ - - tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs); - tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs); - r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */ - } + r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2); + r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */ + r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */ /* The cs checker requires this register to be set. */ r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); @@ -2545,7 +2574,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) return; } - r600_init_command_buffer(cb, 320); + r600_init_command_buffer(cb, 338); /* This must be first. */ r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); @@ -2556,7 +2585,13 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); - evergreen_init_common_regs(cb, rctx->b.chip_class, + /* This enables pipeline stat & streamout queries. + * They are only disabled by blits. + */ + r600_store_value(cb, PKT3(PKT3_EVENT_WRITE, 0, 0)); + r600_store_value(cb, EVENT_TYPE(EVENT_TYPE_PIPELINESTAT_START) | EVENT_INDEX(0)); + + evergreen_init_common_regs(rctx, cb, rctx->b.chip_class, rctx->b.family, rctx->screen->b.info.drm_minor); family = rctx->b.family; @@ -2638,8 +2673,8 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) num_vs_threads = 25; num_gs_threads = 25; num_es_threads = 25; - num_hs_threads = 25; - num_ls_threads = 25; + num_hs_threads = 16; + num_ls_threads = 16; num_ps_stack_entries = 42; num_vs_stack_entries = 42; num_gs_stack_entries = 42; @@ -2652,8 +2687,8 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) num_vs_threads = 25; num_gs_threads = 25; num_es_threads = 25; - num_hs_threads = 25; - num_ls_threads = 25; + num_hs_threads = 16; + num_ls_threads = 16; num_ps_stack_entries = 85; num_vs_stack_entries = 85; num_gs_stack_entries = 85; @@ -2690,7 +2725,7 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) num_ls_stack_entries = 42; break; case CHIP_CAICOS: - num_ps_threads = 128; + num_ps_threads = 96; num_vs_threads = 10; num_gs_threads = 10; num_es_threads = 10; @@ -2732,6 +2767,12 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT, S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000)); + /* remove LS/HS from one SIMD for hw workaround */ + r600_store_config_reg_seq(cb, R_008E20_SQ_STATIC_THREAD_MGMT1, 3); + r600_store_value(cb, 0xffffffff); + r600_store_value(cb, 0xffffffff); + r600_store_value(cb, 0xfffffffe); + r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0); r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4)); @@ -2752,9 +2793,9 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ - r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ - r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ + r600_store_value(cb, fui(64)); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ + r600_store_value(cb, fui(1.0)); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ + r600_store_value(cb, 16); /* R_028A20_VGT_HOS_REUSE_DEPTH */ r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ @@ -2764,10 +2805,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */ - r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2); - r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */ - r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ - r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1); r600_store_context_reg(cb, R_0288F0_SQ_VTX_SEMANTIC_CLEAR, ~0); @@ -2784,12 +2821,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); - r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2 * R600_MAX_VIEWPORTS); - for (tmp = 0; tmp < R600_MAX_VIEWPORTS; tmp++) { - r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ - r600_store_value(cb, fui(1.0)); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ - } - r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0); r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); @@ -2798,12 +2829,6 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */ r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */ - r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4); - r600_store_value(cb, fui(1.0)); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ - r600_store_value(cb, fui(1.0)); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ - r600_store_value(cb, fui(1.0)); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ - r600_store_value(cb, fui(1.0)); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ - r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ @@ -2817,6 +2842,8 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg(cb, R_02887C_SQ_PGM_RESOURCES_2_GS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_028894_SQ_PGM_RESOURCES_2_ES, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0); + r600_store_context_reg(cb, R_0288C0_SQ_PGM_RESOURCES_2_HS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); + r600_store_context_reg(cb, R_0288D8_SQ_PGM_RESOURCES_2_LS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); /* to avoid GPU doing any preloading of constant from random address */ r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 16); @@ -2851,12 +2878,32 @@ void evergreen_init_atom_start_cs(struct r600_context *rctx) r600_store_context_reg_seq(cb, R_0286E4_SPI_PS_IN_CONTROL_2, 2); r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ - r600_store_context_reg(cb, R_0288EC_SQ_LDS_ALLOC_PS, 0); - r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0); + + r600_store_context_reg_seq(cb, R_0288E8_SQ_LDS_ALLOC, 2); + r600_store_value(cb, 0); /* R_0288E8_SQ_LDS_ALLOC */ + r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */ + + if (rctx->b.family == CHIP_CAICOS) { + r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 2); + r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ + r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ + r600_store_context_reg(cb, R_028B6C_VGT_TF_PARAM, 0); + } else { + r600_store_context_reg_seq(cb, R_028B54_VGT_SHADER_STAGES_EN, 7); + r600_store_value(cb, 0); /* R028B54_VGT_SHADER_STAGES_EN */ + r600_store_value(cb, 0); /* R028B58_VGT_LS_HS_CONFIG */ + r600_store_value(cb, 0); /* R028B5C_VGT_LS_SIZE */ + r600_store_value(cb, 0); /* R028B60_VGT_HS_SIZE */ + r600_store_value(cb, 0); /* R028B64_VGT_LS_HS_ALLOC */ + r600_store_value(cb, 0); /* R028B68_VGT_HS_PATCH_CONST */ + r600_store_value(cb, 0); /* R028B68_VGT_TF_PARAM */ + } eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (64 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (96 * 4), 0x01000FFF); + eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (128 * 4), 0x01000FFF); } void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) @@ -2920,6 +2967,10 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader if (sid) { tmp = S_028644_SEMANTIC(sid); + /* D3D 9 behaviour. GL is undefined */ + if (rshader->input[i].name == TGSI_SEMANTIC_COLOR && rshader->input[i].sid == 0) + tmp |= S_028644_DEFAULT_VAL(3); + if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && @@ -3071,7 +3122,6 @@ void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader /* VGT_GS_MODE is written by evergreen_emit_shader_stages */ - r600_store_context_reg(cb, R_028AB8_VGT_VTX_CNT_EN, 1); r600_store_context_reg(cb, R_028B38_VGT_GS_MAX_VERT_OUT, S_028B38_MAX_VERT_OUT(shader->selector->gs_max_out_vertices)); @@ -3177,6 +3227,31 @@ void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader S_02881C_USE_VTX_RENDER_TARGET_INDX(rshader->vs_out_layer); } +void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) +{ + struct r600_command_buffer *cb = &shader->command_buffer; + struct r600_shader *rshader = &shader->shader; + + r600_init_command_buffer(cb, 32); + r600_store_context_reg(cb, R_0288BC_SQ_PGM_RESOURCES_HS, + S_0288BC_NUM_GPRS(rshader->bc.ngpr) | + S_0288BC_STACK_SIZE(rshader->bc.nstack)); + r600_store_context_reg(cb, R_0288B8_SQ_PGM_START_HS, + shader->bo->gpu_address >> 8); +} + +void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader) +{ + struct r600_command_buffer *cb = &shader->command_buffer; + struct r600_shader *rshader = &shader->shader; + + r600_init_command_buffer(cb, 32); + r600_store_context_reg(cb, R_0288D4_SQ_PGM_RESOURCES_LS, + S_0288D4_NUM_GPRS(rshader->bc.ngpr) | + S_0288D4_STACK_SIZE(rshader->bc.nstack)); + r600_store_context_reg(cb, R_0288D0_SQ_PGM_START_LS, + shader->bo->gpu_address >> 8); +} void *evergreen_create_resolve_blend(struct r600_context *rctx) { struct pipe_blend_state blend; @@ -3284,9 +3359,6 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */ @@ -3297,9 +3369,9 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, sub_cmd = EG_DMA_COPY_TILED; lbpp = util_logbase2(bpp); pitch_tile_max = ((pitch / bpp) / 8) - 1; - nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks); + nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks); - if (dst_mode == RADEON_SURF_MODE_LINEAR) { + if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) { /* T2L */ array_mode = evergreen_array_mode(src_mode); slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); @@ -3353,7 +3425,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, size = (copy_height * pitch) / 4; ncopy = (size / EG_DMA_COPY_MAX_SIZE) + !!(size % EG_DMA_COPY_MAX_SIZE); - r600_need_dma_space(&rctx->b, ncopy * 9); + r600_need_dma_space(&rctx->b, ncopy * 9, &rdst->resource, &rsrc->resource); for (i = 0; i < ncopy; i++) { cheight = copy_height; @@ -3366,21 +3438,22 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, RADEON_USAGE_READ, RADEON_PRIO_SDMA_TEXTURE); radeon_add_to_buffer_list(&rctx->b, &rctx->b.dma, &rdst->resource, RADEON_USAGE_WRITE, RADEON_PRIO_SDMA_TEXTURE); - cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size); - cs->buf[cs->cdw++] = base >> 8; - cs->buf[cs->cdw++] = (detile << 31) | (array_mode << 27) | - (lbpp << 24) | (bank_h << 21) | - (bank_w << 18) | (mt_aspect << 16); - cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16); - cs->buf[cs->cdw++] = (slice_tile_max << 0); - cs->buf[cs->cdw++] = (x << 0) | (z << 18); - cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28); - cs->buf[cs->cdw++] = addr & 0xfffffffc; - cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff; + radeon_emit(cs, DMA_PACKET(DMA_PACKET_COPY, sub_cmd, size)); + radeon_emit(cs, base >> 8); + radeon_emit(cs, (detile << 31) | (array_mode << 27) | + (lbpp << 24) | (bank_h << 21) | + (bank_w << 18) | (mt_aspect << 16)); + radeon_emit(cs, (pitch_tile_max << 0) | ((height - 1) << 16)); + radeon_emit(cs, (slice_tile_max << 0)); + radeon_emit(cs, (x << 0) | (z << 18)); + radeon_emit(cs, (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28)); + radeon_emit(cs, addr & 0xfffffffc); + radeon_emit(cs, (addr >> 32UL) & 0xff); copy_height -= cheight; addr += cheight * pitch; y += cheight; } + r600_dma_emit_wait_idle(&rctx->b); } static void evergreen_dma_copy(struct pipe_context *ctx, @@ -3408,14 +3481,10 @@ static void evergreen_dma_copy(struct pipe_context *ctx, return; } - if (src->format != dst->format || src_box->depth > 1 || - (rdst->dirty_level_mask | rdst->stencil_dirty_level_mask) & (1 << dst_level)) { + if (src_box->depth > 1 || + !r600_prepare_for_dma_blit(&rctx->b, rdst, dst_level, dstx, dsty, + dstz, rsrc, src_level, src_box)) goto fallback; - } - - if (rsrc->dirty_level_mask & (1 << src_level)) { - ctx->flush_resource(ctx, src); - } src_x = util_format_get_nblocksx(src->format, src_box->x); dst_x = util_format_get_nblocksx(src->format, dst_x); @@ -3431,9 +3500,6 @@ static void evergreen_dma_copy(struct pipe_context *ctx, dst_mode = rdst->surface.level[dst_level].mode; src_mode = rsrc->surface.level[src_level].mode; - /* downcast linear aligned to linear to simplify test */ - src_mode = src_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : src_mode; - dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) { /* FIXME evergreen can do partial blit */ @@ -3484,31 +3550,49 @@ fallback: src, src_level, src_box); } +static void evergreen_set_tess_state(struct pipe_context *ctx, + const float default_outer_level[4], + const float default_inner_level[2]) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + + memcpy(rctx->tess_state, default_outer_level, sizeof(float) * 4); + memcpy(rctx->tess_state+4, default_inner_level, sizeof(float) * 2); + rctx->tess_state_dirty = true; +} + void evergreen_init_state_functions(struct r600_context *rctx) { unsigned id = 1; - + unsigned i; /* !!! - * To avoid GPU lockup registers must be emited in a specific order + * To avoid GPU lockup registers must be emitted in a specific order * (no kidding ...). The order below is important and have been - * partialy infered from analyzing fglrx command stream. + * partially inferred from analyzing fglrx command stream. * * Don't reorder atom without carefully checking the effect (GPU lockup * or piglit regression). * !!! */ - + if (rctx->b.chip_class == EVERGREEN) { + r600_init_atom(rctx, &rctx->config_state.atom, id++, evergreen_emit_config_state, 11); + rctx->config_state.dyn_gpr_enabled = true; + } r600_init_atom(rctx, &rctx->framebuffer.atom, id++, evergreen_emit_framebuffer_state, 0); /* shader const */ r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_VERTEX].atom, id++, evergreen_emit_vs_constant_buffers, 0); r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_GEOMETRY].atom, id++, evergreen_emit_gs_constant_buffers, 0); r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_FRAGMENT].atom, id++, evergreen_emit_ps_constant_buffers, 0); + r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_CTRL].atom, id++, evergreen_emit_tcs_constant_buffers, 0); + r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_TESS_EVAL].atom, id++, evergreen_emit_tes_constant_buffers, 0); r600_init_atom(rctx, &rctx->constbuf_state[PIPE_SHADER_COMPUTE].atom, id++, evergreen_emit_cs_constant_buffers, 0); /* shader program */ r600_init_atom(rctx, &rctx->cs_shader_state.atom, id++, evergreen_emit_cs_shader, 0); /* sampler */ r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].states.atom, id++, evergreen_emit_vs_sampler_states, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].states.atom, id++, evergreen_emit_gs_sampler_states, 0); + r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].states.atom, id++, evergreen_emit_tcs_sampler_states, 0); + r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].states.atom, id++, evergreen_emit_tes_sampler_states, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].states.atom, id++, evergreen_emit_ps_sampler_states, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].states.atom, id++, evergreen_emit_cs_sampler_states, 0); /* resources */ @@ -3516,6 +3600,8 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->cs_vertex_buffer_state.atom, id++, evergreen_cs_emit_vertex_buffers, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_VERTEX].views.atom, id++, evergreen_emit_vs_sampler_views, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_GEOMETRY].views.atom, id++, evergreen_emit_gs_sampler_views, 0); + r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_CTRL].views.atom, id++, evergreen_emit_tcs_sampler_views, 0); + r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_TESS_EVAL].views.atom, id++, evergreen_emit_tes_sampler_views, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_FRAGMENT].views.atom, id++, evergreen_emit_ps_sampler_views, 0); r600_init_atom(rctx, &rctx->samplers[PIPE_SHADER_COMPUTE].views.atom, id++, evergreen_emit_cs_sampler_views, 0); @@ -3532,25 +3618,23 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->blend_color.atom, id++, r600_emit_blend_color, 6); r600_init_atom(rctx, &rctx->blend_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->cb_misc_state.atom, id++, evergreen_emit_cb_misc_state, 4); - r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); + r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 9); r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26); r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 10); r600_init_atom(rctx, &rctx->db_state.atom, id++, evergreen_emit_db_state, 14); r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); - r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6); + r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 9); r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); - r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 0); - r600_init_atom(rctx, &rctx->viewport.atom, id++, r600_emit_viewport_state, 0); + r600_add_atom(rctx, &rctx->b.scissors.atom, id++); + r600_add_atom(rctx, &rctx->b.viewports.atom, id++); r600_init_atom(rctx, &rctx->stencil_ref.atom, id++, r600_emit_stencil_ref, 4); r600_init_atom(rctx, &rctx->vertex_fetch_shader.atom, id++, evergreen_emit_vertex_fetch_shader, 5); r600_add_atom(rctx, &rctx->b.render_cond_atom, id++); r600_add_atom(rctx, &rctx->b.streamout.begin_atom, id++); r600_add_atom(rctx, &rctx->b.streamout.enable_atom, id++); - r600_init_atom(rctx, &rctx->vertex_shader.atom, id++, r600_emit_shader, 23); - r600_init_atom(rctx, &rctx->pixel_shader.atom, id++, r600_emit_shader, 0); - r600_init_atom(rctx, &rctx->geometry_shader.atom, id++, r600_emit_shader, 0); - r600_init_atom(rctx, &rctx->export_shader.atom, id++, r600_emit_shader, 0); - r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 6); + for (i = 0; i < EG_NUM_HW_STAGES; i++) + r600_init_atom(rctx, &rctx->hw_shader_stages[i].atom, id++, r600_emit_shader, 0); + r600_init_atom(rctx, &rctx->shader_stages.atom, id++, evergreen_emit_shader_stages, 15); r600_init_atom(rctx, &rctx->gs_rings.atom, id++, evergreen_emit_gs_rings, 26); rctx->b.b.create_blend_state = evergreen_create_blend_state; @@ -3561,8 +3645,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) rctx->b.b.set_framebuffer_state = evergreen_set_framebuffer_state; rctx->b.b.set_polygon_stipple = evergreen_set_polygon_stipple; rctx->b.b.set_min_samples = evergreen_set_min_samples; - rctx->b.b.set_scissor_states = evergreen_set_scissor_states; - + rctx->b.b.set_tess_state = evergreen_set_tess_state; if (rctx->b.chip_class == EVERGREEN) rctx->b.b.get_sample_position = evergreen_get_sample_position; else @@ -3571,3 +3654,272 @@ void evergreen_init_state_functions(struct r600_context *rctx) evergreen_init_compute_state_functions(rctx); } + +/** + * This calculates the LDS size for tessellation shaders (VS, TCS, TES). + * + * The information about LDS and other non-compile-time parameters is then + * written to the const buffer. + + * const buffer contains - + * uint32_t input_patch_size + * uint32_t input_vertex_size + * uint32_t num_tcs_input_cp + * uint32_t num_tcs_output_cp; + * uint32_t output_patch_size + * uint32_t output_vertex_size + * uint32_t output_patch0_offset + * uint32_t perpatch_output_offset + * and the same constbuf is bound to LS/HS/VS(ES). + */ +void evergreen_setup_tess_constants(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned *num_patches) +{ + struct pipe_constant_buffer constbuf = {0}; + struct r600_pipe_shader_selector *tcs = rctx->tcs_shader ? rctx->tcs_shader : rctx->tes_shader; + struct r600_pipe_shader_selector *ls = rctx->vs_shader; + unsigned num_tcs_input_cp = info->vertices_per_patch; + unsigned num_tcs_outputs; + unsigned num_tcs_output_cp; + unsigned num_tcs_patch_outputs; + unsigned num_tcs_inputs; + unsigned input_vertex_size, output_vertex_size; + unsigned input_patch_size, pervertex_output_patch_size, output_patch_size; + unsigned output_patch0_offset, perpatch_output_offset, lds_size; + uint32_t values[16]; + unsigned num_waves; + unsigned num_pipes = rctx->screen->b.info.r600_max_quad_pipes; + unsigned wave_divisor = (16 * num_pipes); + + *num_patches = 1; + + if (!rctx->tes_shader) { + rctx->lds_alloc = 0; + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX, + R600_LDS_INFO_CONST_BUFFER, NULL); + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL, + R600_LDS_INFO_CONST_BUFFER, NULL); + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL, + R600_LDS_INFO_CONST_BUFFER, NULL); + return; + } + + if (rctx->lds_alloc != 0 && + rctx->last_ls == ls && + !rctx->tess_state_dirty && + rctx->last_num_tcs_input_cp == num_tcs_input_cp && + rctx->last_tcs == tcs) + return; + + num_tcs_inputs = util_last_bit64(ls->lds_outputs_written_mask); + + if (rctx->tcs_shader) { + num_tcs_outputs = util_last_bit64(tcs->lds_outputs_written_mask); + num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT]; + num_tcs_patch_outputs = util_last_bit64(tcs->lds_patch_outputs_written_mask); + } else { + num_tcs_outputs = num_tcs_inputs; + num_tcs_output_cp = num_tcs_input_cp; + num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */ + } + + /* size in bytes */ + input_vertex_size = num_tcs_inputs * 16; + output_vertex_size = num_tcs_outputs * 16; + + input_patch_size = num_tcs_input_cp * input_vertex_size; + + pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; + output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; + + output_patch0_offset = rctx->tcs_shader ? input_patch_size * *num_patches : 0; + perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size; + + lds_size = output_patch0_offset + output_patch_size * *num_patches; + + values[0] = input_patch_size; + values[1] = input_vertex_size; + values[2] = num_tcs_input_cp; + values[3] = num_tcs_output_cp; + + values[4] = output_patch_size; + values[5] = output_vertex_size; + values[6] = output_patch0_offset; + values[7] = perpatch_output_offset; + + /* docs say HS_NUM_WAVES - CEIL((LS_HS_CONFIG.NUM_PATCHES * + LS_HS_CONFIG.HS_NUM_OUTPUT_CP) / (NUM_GOOD_PIPES * 16)) */ + num_waves = ceilf((float)(*num_patches * num_tcs_output_cp) / (float)wave_divisor); + + rctx->lds_alloc = (lds_size | (num_waves << 14)); + + memcpy(&values[8], rctx->tess_state, 6 * sizeof(float)); + values[14] = 0; + values[15] = 0; + + rctx->tess_state_dirty = false; + rctx->last_ls = ls; + rctx->last_tcs = tcs; + rctx->last_num_tcs_input_cp = num_tcs_input_cp; + + constbuf.user_buffer = values; + constbuf.buffer_size = 16 * 4; + + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_VERTEX, + R600_LDS_INFO_CONST_BUFFER, &constbuf); + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_CTRL, + R600_LDS_INFO_CONST_BUFFER, &constbuf); + rctx->b.b.set_constant_buffer(&rctx->b.b, PIPE_SHADER_TESS_EVAL, + R600_LDS_INFO_CONST_BUFFER, &constbuf); + pipe_resource_reference(&constbuf.buffer, NULL); +} + +uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, + const struct pipe_draw_info *info, + unsigned num_patches) +{ + unsigned num_output_cp; + + if (!rctx->tes_shader) + return 0; + + num_output_cp = rctx->tcs_shader ? + rctx->tcs_shader->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : + info->vertices_per_patch; + + return S_028B58_NUM_PATCHES(num_patches) | + S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) | + S_028B58_HS_NUM_OUTPUT_CP(num_output_cp); +} + +void evergreen_set_ls_hs_config(struct r600_context *rctx, + struct radeon_winsys_cs *cs, + uint32_t ls_hs_config) +{ + radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); +} + +void evergreen_set_lds_alloc(struct r600_context *rctx, + struct radeon_winsys_cs *cs, + uint32_t lds_alloc) +{ + radeon_set_context_reg(cs, R_0288E8_SQ_LDS_ALLOC, lds_alloc); +} + +/* on evergreen if you are running tessellation you need to disable dynamic + GPRs to workaround a hardware bug.*/ +bool evergreen_adjust_gprs(struct r600_context *rctx) +{ + unsigned num_gprs[EG_NUM_HW_STAGES]; + unsigned def_gprs[EG_NUM_HW_STAGES]; + unsigned cur_gprs[EG_NUM_HW_STAGES]; + unsigned new_gprs[EG_NUM_HW_STAGES]; + unsigned def_num_clause_temp_gprs = rctx->r6xx_num_clause_temp_gprs; + unsigned max_gprs; + unsigned i; + unsigned total_gprs; + unsigned tmp[3]; + bool rework = false, set_default = false, set_dirty = false; + max_gprs = 0; + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + def_gprs[i] = rctx->default_gprs[i]; + max_gprs += def_gprs[i]; + } + max_gprs += def_num_clause_temp_gprs * 2; + + /* if we have no TESS and dyn gpr is enabled then do nothing. */ + if (!rctx->hw_shader_stages[EG_HW_STAGE_HS].shader) { + if (rctx->config_state.dyn_gpr_enabled) + return true; + + /* transition back to dyn gpr enabled state */ + rctx->config_state.dyn_gpr_enabled = true; + r600_mark_atom_dirty(rctx, &rctx->config_state.atom); + rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; + return true; + } + + + /* gather required shader gprs */ + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + if (rctx->hw_shader_stages[i].shader) + num_gprs[i] = rctx->hw_shader_stages[i].shader->shader.bc.ngpr; + else + num_gprs[i] = 0; + } + + cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); + cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1); + cur_gprs[R600_HW_STAGE_GS] = G_008C08_NUM_GS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); + cur_gprs[R600_HW_STAGE_ES] = G_008C08_NUM_ES_GPRS(rctx->config_state.sq_gpr_resource_mgmt_2); + cur_gprs[EG_HW_STAGE_LS] = G_008C0C_NUM_LS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3); + cur_gprs[EG_HW_STAGE_HS] = G_008C0C_NUM_HS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_3); + + total_gprs = 0; + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + new_gprs[i] = num_gprs[i]; + total_gprs += num_gprs[i]; + } + + if (total_gprs > (max_gprs - (2 * def_num_clause_temp_gprs))) + return false; + + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + if (new_gprs[i] > cur_gprs[i]) { + rework = true; + break; + } + } + + if (rctx->config_state.dyn_gpr_enabled) { + set_dirty = true; + rctx->config_state.dyn_gpr_enabled = false; + } + + if (rework) { + set_default = true; + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + if (new_gprs[i] > def_gprs[i]) + set_default = false; + } + + if (set_default) { + for (i = 0; i < EG_NUM_HW_STAGES; i++) { + new_gprs[i] = def_gprs[i]; + } + } else { + unsigned ps_value = max_gprs; + + ps_value -= (def_num_clause_temp_gprs * 2); + for (i = R600_HW_STAGE_VS; i < EG_NUM_HW_STAGES; i++) + ps_value -= new_gprs[i]; + + new_gprs[R600_HW_STAGE_PS] = ps_value; + } + + tmp[0] = S_008C04_NUM_PS_GPRS(new_gprs[R600_HW_STAGE_PS]) | + S_008C04_NUM_VS_GPRS(new_gprs[R600_HW_STAGE_VS]) | + S_008C04_NUM_CLAUSE_TEMP_GPRS(def_num_clause_temp_gprs); + + tmp[1] = S_008C08_NUM_ES_GPRS(new_gprs[R600_HW_STAGE_ES]) | + S_008C08_NUM_GS_GPRS(new_gprs[R600_HW_STAGE_GS]); + + tmp[2] = S_008C0C_NUM_HS_GPRS(new_gprs[EG_HW_STAGE_HS]) | + S_008C0C_NUM_LS_GPRS(new_gprs[EG_HW_STAGE_LS]); + + if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] || + rctx->config_state.sq_gpr_resource_mgmt_2 != tmp[1] || + rctx->config_state.sq_gpr_resource_mgmt_3 != tmp[2]) { + rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0]; + rctx->config_state.sq_gpr_resource_mgmt_2 = tmp[1]; + rctx->config_state.sq_gpr_resource_mgmt_3 = tmp[2]; + set_dirty = true; + } + } + + + if (set_dirty) { + r600_mark_atom_dirty(rctx, &rctx->config_state.atom); + rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; + } + return true; +}