X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600.h;h=229fa7068b269c3a1d7b7f3d6c8baf78318d4ec1;hb=85571ed53c18f4e5c31ea8eb81c1231c6d786ae4;hp=719119a1599f93073d6f12a8e8ca6f0c9fc9357d;hpb=1a532ca79a4a87bb86c641a6ca22da0301dc1f62;p=mesa.git diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index 719119a1599..229fa7068b2 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -28,16 +28,11 @@ #include "../../winsys/radeon/drm/radeon_winsys.h" #include "util/u_double_list.h" +#include "util/u_vbuf.h" #define R600_ERR(fmt, args...) \ fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) -typedef uint64_t u64; -typedef uint32_t u32; -typedef uint16_t u16; -typedef uint8_t u8; - -struct radeon; struct winsys_handle; enum radeon_family { @@ -82,36 +77,16 @@ struct r600_tiling_info { unsigned group_bytes; }; -enum radeon_family r600_get_family(struct radeon *rw); -enum chip_class r600_get_family_class(struct radeon *radeon); - -/* r600_bo.c */ -struct r600_bo; -struct radeon_winsys_cs; - -struct r600_bo *r600_bo(struct radeon *radeon, - unsigned size, unsigned alignment, - unsigned binding, unsigned usage); -struct r600_bo *r600_bo_handle(struct radeon *radeon, struct winsys_handle *whandle, - unsigned *stride, unsigned *array_mode); -void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, struct radeon_winsys_cs *cs, unsigned usage); -void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo); -boolean r600_bo_get_winsys_handle(struct radeon *radeon, struct r600_bo *pb_bo, - unsigned stride, struct winsys_handle *whandle); +struct r600_resource { + struct u_vbuf_resource b; -void r600_bo_destroy(struct r600_bo *bo); - -/* this relies on the pipe_reference being the first member of r600_bo */ -static INLINE void r600_bo_reference(struct r600_bo **dst, struct r600_bo *src) -{ - struct r600_bo *old = *dst; - - if (pipe_reference((struct pipe_reference *)(*dst), (struct pipe_reference *)src)) { - r600_bo_destroy(old); - } - *dst = src; -} + /* Winsys objects. */ + struct pb_buffer *buf; + struct radeon_winsys_cs_handle *cs_buf; + /* Resource state. */ + unsigned domains; +}; /* R600/R700 STATES */ #define R600_GROUP_MAX 16 @@ -130,12 +105,11 @@ static INLINE void r600_bo_reference(struct r600_bo **dst, struct r600_bo *src) #define CTX_BLOCK_ID(offset) (((offset - RANGE_OFFSET_START) >> 2) & ((1 << HASH_SHIFT) - 1)) struct r600_pipe_reg { - u32 value; - u32 mask; + uint32_t value; struct r600_block *block; - struct r600_bo *bo; + struct r600_resource *bo; enum radeon_bo_usage bo_usage; - u32 id; + uint32_t id; }; struct r600_pipe_state { @@ -146,9 +120,9 @@ struct r600_pipe_state { struct r600_pipe_resource_state { unsigned id; - u32 val[8]; - struct r600_bo *bo[2]; - enum radeon_bo_usage bo_usage[2]; /* XXX set these */ + uint32_t val[8]; + struct r600_resource *bo[2]; + enum radeon_bo_usage bo_usage[2]; }; #define R600_BLOCK_STATUS_ENABLED (1 << 0) @@ -158,10 +132,8 @@ struct r600_pipe_resource_state { #define R600_BLOCK_STATUS_RESOURCE_VERTEX (1 << 3) struct r600_block_reloc { - struct r600_bo *bo; + struct r600_resource *bo; enum radeon_bo_usage bo_usage; - unsigned flush_flags; - unsigned flush_mask; unsigned bo_pm4_index; }; @@ -172,12 +144,11 @@ struct r600_block { unsigned flags; unsigned start_offset; unsigned pm4_ndwords; - unsigned pm4_flush_ndwords; unsigned nbo; - u16 nreg; - u16 nreg_dirty; - u32 *reg; - u32 pm4[R600_BLOCK_MAX_REG]; + uint16_t nreg; + uint16_t nreg_dirty; + uint32_t *reg; + uint32_t pm4[R600_BLOCK_MAX_REG]; unsigned pm4_bo_index[R600_BLOCK_MAX_REG]; struct r600_block_reloc reloc[R600_BLOCK_MAX_BO]; }; @@ -186,87 +157,60 @@ struct r600_range { struct r600_block **blocks; }; -/* - * query - */ struct r600_query { - u64 result; + union { + uint64_t u64; + boolean b; + struct pipe_query_data_so_statistics so; + } result; /* The kind of query */ unsigned type; /* Offset of the first result for current query */ unsigned results_start; /* Offset of the next free result after current query data */ unsigned results_end; - /* Size of the result */ + /* Size of the result in memory for both begin_query and end_query, + * this can be one or two numbers, or it could even be a size of a structure. */ unsigned result_size; - /* Count of new queries started in one stream without flushing */ - unsigned queries_emitted; - /* State flags */ - unsigned state; /* The buffer where query results are stored. It's used as a ring, * data blocks for current query are stored sequentially from * results_start to results_end, with wrapping on the buffer end */ - struct r600_bo *buffer; - unsigned buffer_size; + struct r600_resource *buffer; + /* The number of dwords for begin_query or end_query. */ + unsigned num_cs_dw; /* linked list of queries */ struct list_head list; }; -#define R600_QUERY_STATE_STARTED (1 << 0) -#define R600_QUERY_STATE_ENDED (1 << 1) -#define R600_QUERY_STATE_SUSPENDED (1 << 2) -#define R600_QUERY_STATE_FLUSHED (1 << 3) +struct r600_so_target { + struct pipe_stream_output_target b; + + /* The buffer where BUFFER_FILLED_SIZE is stored. */ + struct r600_resource *filled_size; + unsigned stride_in_dw; + unsigned so_index; +}; #define R600_CONTEXT_DRAW_PENDING (1 << 0) #define R600_CONTEXT_DST_CACHES_DIRTY (1 << 1) #define R600_CONTEXT_CHECK_EVENT_FLUSH (1 << 2) -struct r600_context { - struct radeon *radeon; - struct radeon_winsys_cs *cs; - - struct r600_range *range; - unsigned nblocks; - struct r600_block **blocks; - struct list_head dirty; - struct list_head resource_dirty; - struct list_head enable_list; - unsigned pm4_ndwords; - unsigned pm4_dirty_cdwords; - unsigned ctx_pm4_ndwords; - unsigned init_dwords; - - unsigned creloc; - struct r600_bo **bo; - - u32 *pm4; - unsigned pm4_cdwords; - - struct list_head query_list; - unsigned num_query_running; - unsigned backend_mask; - unsigned max_db; /* for OQ */ - unsigned num_dest_buffers; - unsigned flags; - boolean predicate_drawing; - struct r600_range ps_resources; - struct r600_range vs_resources; - struct r600_range fs_resources; - int num_ps_resources, num_vs_resources, num_fs_resources; - boolean have_depth_texture, have_depth_fb; -}; - struct r600_draw { - u32 vgt_num_indices; - u32 vgt_num_instances; - u32 vgt_index_type; - u32 vgt_draw_initiator; - u32 indices_bo_offset; - struct r600_bo *indices; + uint32_t vgt_num_indices; + uint32_t vgt_num_instances; + uint32_t vgt_index_type; + uint32_t vgt_draw_initiator; + uint32_t indices_bo_offset; + unsigned db_render_override; + unsigned db_render_control; + struct r600_resource *indices; }; +struct r600_context; +struct r600_screen; + void r600_get_backend_mask(struct r600_context *ctx); -int r600_context_init(struct r600_context *ctx, struct radeon *radeon); +int r600_context_init(struct r600_context *ctx); void r600_context_fini(struct r600_context *ctx); void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); @@ -285,48 +229,54 @@ boolean r600_context_query_result(struct r600_context *ctx, void r600_query_begin(struct r600_context *ctx, struct r600_query *query); void r600_query_end(struct r600_context *ctx, struct r600_query *query); void r600_context_queries_suspend(struct r600_context *ctx); -void r600_context_queries_resume(struct r600_context *ctx, boolean flushed); +void r600_context_queries_resume(struct r600_context *ctx); void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, int flag_wait); -void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence, +void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, unsigned offset, unsigned value); -void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags); -void r600_context_flush_dest_caches(struct r600_context *ctx); - -int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon); +void r600_inval_shader_cache(struct r600_context *ctx); +void r600_inval_texture_cache(struct r600_context *ctx); +void r600_inval_vertex_cache(struct r600_context *ctx); +void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now); + +void r600_context_streamout_begin(struct r600_context *ctx); +void r600_context_streamout_end(struct r600_context *ctx); +void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t); +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block); +void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block); + +int evergreen_context_init(struct r600_context *ctx); void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); -void evergreen_context_flush_dest_caches(struct r600_context *ctx); void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); void evergreen_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); void evergreen_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid); void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); -struct radeon *radeon_destroy(struct radeon *radeon); - void _r600_pipe_state_add_reg(struct r600_context *ctx, struct r600_pipe_state *state, - u32 offset, u32 value, u32 mask, - u32 range_id, u32 block_id, - struct r600_bo *bo, + uint32_t offset, uint32_t value, + uint32_t range_id, uint32_t block_id, + struct r600_resource *bo, enum radeon_bo_usage usage); void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, - u32 offset, u32 value, u32 mask, - struct r600_bo *bo, + uint32_t offset, uint32_t value, + struct r600_resource *bo, enum radeon_bo_usage usage); -#define r600_pipe_state_add_reg(state, offset, value, mask, bo, usage) _r600_pipe_state_add_reg(&rctx->ctx, state, offset, value, mask, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage) +#define r600_pipe_state_add_reg(state, offset, value, bo, usage) _r600_pipe_state_add_reg(rctx, state, offset, value, CTX_RANGE_ID(offset), CTX_BLOCK_ID(offset), bo, usage) static inline void r600_pipe_state_mod_reg(struct r600_pipe_state *state, - u32 value) + uint32_t value) { state->regs[state->nregs].value = value; state->nregs++; } static inline void r600_pipe_state_mod_reg_bo(struct r600_pipe_state *state, - u32 value, struct r600_bo *bo, + uint32_t value, struct r600_resource *bo, enum radeon_bo_usage usage) { state->regs[state->nregs].value = value;