X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_asm.h;h=e37d92672bd0ceef59125586905a4b1638bb30c4;hb=7b0067d23a6f64cf83c42e7f11b2cd4100c569fe;hp=182f403aa773ec7bb323540d5f596f1790e84d58;hpb=d23aa650015ec017649f5a4ce8cb12d8c314bd3a;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_asm.h b/src/gallium/drivers/r600/r600_asm.h index 182f403aa77..e37d92672bd 100644 --- a/src/gallium/drivers/r600/r600_asm.h +++ b/src/gallium/drivers/r600/r600_asm.h @@ -24,6 +24,7 @@ #define R600_ASM_H #include "r600_pipe.h" +#include "r600_isa.h" struct r600_bytecode_alu_src { unsigned sel; @@ -32,6 +33,7 @@ struct r600_bytecode_alu_src { unsigned abs; unsigned rel; unsigned kc_bank; + unsigned kc_rel; uint32_t value; }; @@ -47,7 +49,7 @@ struct r600_bytecode_alu { struct list_head list; struct r600_bytecode_alu_src src[3]; struct r600_bytecode_alu_dst dst; - unsigned inst; + unsigned op; unsigned last; unsigned is_op3; unsigned execute_mask; @@ -61,7 +63,7 @@ struct r600_bytecode_alu { struct r600_bytecode_tex { struct list_head list; - unsigned inst; + unsigned op; unsigned inst_mod; unsigned resource_id; unsigned src_gpr; @@ -85,11 +87,14 @@ struct r600_bytecode_tex { unsigned src_sel_y; unsigned src_sel_z; unsigned src_sel_w; + /* indexed samplers/resources only on evergreen/cayman */ + unsigned sampler_index_mode; + unsigned resource_index_mode; }; struct r600_bytecode_vtx { struct list_head list; - unsigned inst; + unsigned op; unsigned fetch_type; unsigned buffer_id; unsigned src_gpr; @@ -107,6 +112,7 @@ struct r600_bytecode_vtx { unsigned srf_mode_all; unsigned offset; unsigned endian; + unsigned buffer_index_mode; }; struct r600_bytecode_output { @@ -114,10 +120,8 @@ struct r600_bytecode_output { unsigned array_size; unsigned comp_mask; unsigned type; - unsigned end_of_program; - /* CF_INST. This is already bit-shifted and only needs to be or'd for bytecode. */ - unsigned inst; + unsigned op; unsigned elem_size; unsigned gpr; @@ -126,29 +130,20 @@ struct r600_bytecode_output { unsigned swizzle_z; unsigned swizzle_w; unsigned burst_count; - unsigned barrier; + unsigned index_gpr; }; struct r600_bytecode_kcache { unsigned bank; unsigned mode; unsigned addr; + unsigned index_mode; }; -/* A value of CF_NATIVE in r600_bytecode_cf::inst means that this instruction - * has already been encoded, and the encoding has been stored in - * r600_bytecode::isa. This is used by the LLVM backend to emit CF instructions - * e.g. RAT_WRITE_* that can't be properly represented by struct - * r600_bytecode_cf. - */ -#define CF_NATIVE ~0 - struct r600_bytecode_cf { struct list_head list; - /* CF_INST. This is already bit-shifted and only needs to be or'd for bytecode. */ - unsigned inst; - + unsigned op; unsigned addr; unsigned ndw; unsigned id; @@ -158,6 +153,8 @@ struct r600_bytecode_cf { struct r600_bytecode_kcache kcache[4]; unsigned r6xx_uses_waterfall; unsigned eg_alu_extended; + unsigned barrier; + unsigned end_of_program; struct list_head alu; struct list_head tex; struct list_head vtx; @@ -183,20 +180,30 @@ struct r600_cf_stack_entry { }; #define SQ_MAX_CALL_DEPTH 0x00000020 -struct r600_cf_callstack { - unsigned fc_sp_before_entry; - int sub_desc_index; - int current; - int max; -}; #define AR_HANDLE_NORMAL 0 #define AR_HANDLE_RV6XX 1 /* except RV670 */ +struct r600_stack_info { + /* current level of non-WQM PUSH operations + * (PUSH, PUSH_ELSE, ALU_PUSH_BEFORE) */ + int push; + /* current level of WQM PUSH operations + * (PUSH, PUSH_ELSE, PUSH_WQM) */ + int push_wqm; + /* current loop level */ + int loop; + + /* required depth */ + int max_entries; + /* subentries per entry */ + int entry_size; +}; struct r600_bytecode { enum chip_class chip_class; - enum r600_msaa_texture_mode msaa_texture_mode; + enum radeon_family family; + bool has_compressed_msaa_texturing; int type; struct list_head cf; struct r600_bytecode_cf *cf_last; @@ -204,38 +211,53 @@ struct r600_bytecode { unsigned ncf; unsigned ngpr; unsigned nstack; + unsigned nlds_dw; unsigned nresource; unsigned force_add_cf; uint32_t *bytecode; uint32_t fc_sp; struct r600_cf_stack_entry fc_stack[32]; - unsigned call_sp; - struct r600_cf_callstack callstack[SQ_MAX_CALL_DEPTH]; + struct r600_stack_info stack; unsigned ar_loaded; unsigned ar_reg; + unsigned ar_chan; unsigned ar_handling; unsigned r6xx_nop_after_rel_dst; + bool index_loaded[2]; + unsigned index_reg[2]; /* indexing register CF_INDEX_[01] */ + unsigned debug_id; + struct r600_isa* isa; }; /* eg_asm.c */ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf); +int egcm_load_index_reg(struct r600_bytecode *bc, unsigned id, bool inside_alu_clause); /* r600_asm.c */ void r600_bytecode_init(struct r600_bytecode *bc, enum chip_class chip_class, enum radeon_family family, - enum r600_msaa_texture_mode msaa_texture_mode); + bool has_compressed_msaa_texturing); void r600_bytecode_clear(struct r600_bytecode *bc); -int r600_bytecode_add_alu(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu); -int r600_bytecode_add_vtx(struct r600_bytecode *bc, const struct r600_bytecode_vtx *vtx); -int r600_bytecode_add_tex(struct r600_bytecode *bc, const struct r600_bytecode_tex *tex); -int r600_bytecode_add_output(struct r600_bytecode *bc, const struct r600_bytecode_output *output); +int r600_bytecode_add_alu(struct r600_bytecode *bc, + const struct r600_bytecode_alu *alu); +int r600_bytecode_add_vtx(struct r600_bytecode *bc, + const struct r600_bytecode_vtx *vtx); +int r600_bytecode_add_tex(struct r600_bytecode *bc, + const struct r600_bytecode_tex *tex); +int r600_bytecode_add_output(struct r600_bytecode *bc, + const struct r600_bytecode_output *output); int r600_bytecode_build(struct r600_bytecode *bc); -int r600_bytecode_add_cfinst(struct r600_bytecode *bc, int inst); -int r600_bytecode_add_alu_type(struct r600_bytecode *bc, const struct r600_bytecode_alu *alu, int type); -void r600_bytecode_special_constants(uint32_t value, unsigned *sel, unsigned *neg); -void r600_bytecode_dump(struct r600_bytecode *bc); -void r600_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1); +int r600_bytecode_add_cf(struct r600_bytecode *bc); +int r600_bytecode_add_cfinst(struct r600_bytecode *bc, + unsigned op); +int r600_bytecode_add_alu_type(struct r600_bytecode *bc, + const struct r600_bytecode_alu *alu, unsigned type); +void r600_bytecode_special_constants(uint32_t value, + unsigned *sel, unsigned *neg); +void r600_bytecode_disasm(struct r600_bytecode *bc); +void r600_bytecode_alu_read(struct r600_bytecode *bc, + struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1); int cm_bytecode_add_cf_end(struct r600_bytecode *bc); @@ -244,11 +266,16 @@ void *r600_create_vertex_fetch_shader(struct pipe_context *ctx, const struct pipe_vertex_element *elements); /* r700_asm.c */ -void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct r600_bytecode_cf *cf); -int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id); -void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1); -void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1); -void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0, uint32_t word1); +void r700_bytecode_cf_vtx_build(uint32_t *bytecode, + const struct r600_bytecode_cf *cf); +int r700_bytecode_alu_build(struct r600_bytecode *bc, + struct r600_bytecode_alu *alu, unsigned id); +void r700_bytecode_alu_read(struct r600_bytecode *bc, + struct r600_bytecode_alu *alu, uint32_t word0, uint32_t word1); +void r600_bytecode_export_read(struct r600_bytecode *bc, + struct r600_bytecode_output *output, uint32_t word0, uint32_t word1); +void eg_bytecode_export_read(struct r600_bytecode *bc, + struct r600_bytecode_output *output, uint32_t word0, uint32_t word1); void r600_vertex_data_type(enum pipe_format pformat, unsigned *format, unsigned *num_format, unsigned *format_comp, unsigned *endian);