X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_hw_context.c;h=de6bcd7eccf63d5aee1eec349ded0ff322b54d82;hb=2d2af4cd2caa081381b80e987af80022765d98dc;hp=18e17bb0723333c3edc629283fa9c056feee1448;hpb=6317a3fb31014d89edff2993f3cf403f651a07f6;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 18e17bb0723..de6bcd7eccf 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -29,98 +29,15 @@ #include #include -/* Get backends mask */ -void r600_get_backend_mask(struct r600_context *ctx) -{ - struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; - struct r600_resource *buffer; - uint32_t *results; - unsigned num_backends = ctx->screen->b.info.r600_num_backends; - unsigned i, mask = 0; - uint64_t va; - - /* if backend_map query is supported by the kernel */ - if (ctx->screen->b.info.r600_backend_map_valid) { - unsigned num_tile_pipes = ctx->screen->b.info.r600_num_tile_pipes; - unsigned backend_map = ctx->screen->b.info.r600_backend_map; - unsigned item_width, item_mask; - - if (ctx->b.chip_class >= EVERGREEN) { - item_width = 4; - item_mask = 0x7; - } else { - item_width = 2; - item_mask = 0x3; - } - - while(num_tile_pipes--) { - i = backend_map & item_mask; - mask |= (1<>= item_width; - } - if (mask != 0) { - ctx->backend_mask = mask; - return; - } - } - - /* otherwise backup path for older kernels */ - - /* create buffer for event data */ - buffer = (struct r600_resource*) - pipe_buffer_create(&ctx->screen->b.b, PIPE_BIND_CUSTOM, - PIPE_USAGE_STAGING, ctx->max_db*16); - if (!buffer) - goto err; - va = r600_resource_va(&ctx->screen->b.b, (void*)buffer); - - /* initialize buffer with zeroes */ - results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_WRITE); - if (results) { - memset(results, 0, ctx->max_db * 4 * 4); - ctx->b.ws->buffer_unmap(buffer->cs_buf); - - /* emit EVENT_WRITE for ZPASS_DONE */ - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); - cs->buf[cs->cdw++] = va; - cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; - - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, buffer, RADEON_USAGE_WRITE); - - /* analyze results */ - results = r600_buffer_mmap_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ); - if (results) { - for(i = 0; i < ctx->max_db; i++) { - /* at least highest bit will be set if backend is used */ - if (results[i*4 + 1]) - mask |= (1<b.ws->buffer_unmap(buffer->cs_buf); - } - } - - pipe_resource_reference((struct pipe_resource**)&buffer, NULL); - - if (mask != 0) { - ctx->backend_mask = mask; - return; - } - -err: - /* fallback to old method - set num_backends lower bits to 1 */ - ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); - return; -} void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in) { + if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) { ctx->b.gtt = 0; ctx->b.vram = 0; - ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC); + ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); return; } /* all will be accounted once relocation are emited */ @@ -137,7 +54,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, for (i = 0; i < R600_NUM_ATOMS; i++) { if (ctx->atoms[i] && ctx->atoms[i]->dirty) { num_dw += ctx->atoms[i]->num_dw; - if (ctx->screen->trace_bo) { + if (ctx->screen->b.trace_bo) { num_dw += R600_TRACE_CS_DWORDS; } } @@ -145,13 +62,13 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, /* The upper-bound of how much space a draw command would take. */ num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS; - if (ctx->screen->trace_bo) { + if (ctx->screen->b.trace_bo) { num_dw += R600_TRACE_CS_DWORDS; } } /* Count in queries_suspend. */ - num_dw += ctx->num_cs_dw_nontimer_queries_suspend; + num_dw += ctx->b.num_cs_dw_nontimer_queries_suspend; /* Count in streamout_end at the end of CS. */ if (ctx->b.streamout.begin_emitted) { @@ -159,12 +76,12 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, } /* Count in render_condition(NULL) at the end of CS. */ - if (ctx->predicate_drawing) { + if (ctx->b.predicate_drawing) { num_dw += 3; } /* SX_MISC */ - if (ctx->b.chip_class <= R700) { + if (ctx->b.chip_class == R600) { num_dw += 3; } @@ -176,7 +93,7 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, /* Flush if there's not enough space. */ if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { - ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC); + ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); } } @@ -247,7 +164,10 @@ void r600_flush_emit(struct r600_context *rctx) : S_0085F0_TC_ACTION_ENA(1); } if (rctx->b.flags & R600_CONTEXT_INV_TEX_CACHE) { - cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1); + /* Textures use the texture cache. + * Texture buffer objects use the vertex cache. */ + cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1) | + (rctx->has_vertex_cache ? S_0085F0_VC_ACTION_ENA(1) : 0); } /* Don't use the DB CP COHER logic on r6xx. @@ -290,6 +210,15 @@ void r600_flush_emit(struct r600_context *rctx) S_0085F0_SMX_ACTION_ENA(1); } + /* Workaround for buggy flushing on some R6xx chipsets. */ + if (rctx->b.flags & R600_CONTEXT_FLUSH_AND_INV && + (rctx->b.family == CHIP_RV670 || + rctx->b.family == CHIP_RS780 || + rctx->b.family == CHIP_RS880)) { + cp_coher_cntl |= S_0085F0_CB1_DEST_BASE_ENA(1) | + S_0085F0_DEST_BASE_0_ENA(1); + } + if (cp_coher_cntl) { cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); cs->buf[cs->cdw++] = cp_coher_cntl; /* CP_COHER_CNTL */ @@ -310,27 +239,20 @@ void r600_flush_emit(struct r600_context *rctx) rctx->b.flags = 0; } -void r600_context_flush(struct r600_context *ctx, unsigned flags) +void r600_context_gfx_flush(void *context, unsigned flags, + struct pipe_fence_handle **fence) { + struct r600_context *ctx = context; struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; - ctx->nontimer_queries_suspended = false; - ctx->b.streamout.suspended = false; + if (cs->cdw == ctx->b.initial_gfx_cs_size && !fence) + return; - /* suspend queries */ - if (ctx->num_cs_dw_nontimer_queries_suspend) { - r600_suspend_nontimer_queries(ctx); - ctx->nontimer_queries_suspended = true; - } + ctx->b.rings.gfx.flushing = true; - if (ctx->b.streamout.begin_emitted) { - r600_emit_streamout_end(&ctx->b); - ctx->b.streamout.suspended = true; - } + r600_preflush_suspend_features(&ctx->b); - /* flush is needed to avoid lockups on some chips with user fences - * this will also flush the framebuffer cache - */ + /* flush the framebuffer cache */ ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV | R600_CONTEXT_FLUSH_AND_INV_CB | R600_CONTEXT_FLUSH_AND_INV_DB | @@ -342,7 +264,7 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) r600_flush_emit(ctx); /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */ - if (ctx->b.chip_class <= R700) { + if (ctx->b.chip_class == R600) { r600_write_context_reg(cs, R_028350_SX_MISC, 0); } @@ -352,13 +274,16 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags) } /* Flush the CS. */ - ctx->b.ws->cs_flush(ctx->b.rings.gfx.cs, flags, ctx->screen->cs_count++); + ctx->b.ws->cs_flush(cs, flags, fence, ctx->screen->b.cs_count++); + ctx->b.rings.gfx.flushing = false; + + r600_begin_new_cs(ctx); } void r600_begin_new_cs(struct r600_context *ctx) { unsigned shader; - + int i; ctx->b.flags = 0; ctx->b.gtt = 0; ctx->b.vram = 0; @@ -379,12 +304,21 @@ void r600_begin_new_cs(struct r600_context *ctx) ctx->poly_offset_state.atom.dirty = true; ctx->vgt_state.atom.dirty = true; ctx->sample_mask.atom.dirty = true; - ctx->scissor.atom.dirty = true; + for (i = 0; i < 16; i++) { + ctx->scissor[i].atom.dirty = true; + ctx->viewport[i].atom.dirty = true; + } ctx->config_state.atom.dirty = true; ctx->stencil_ref.atom.dirty = true; ctx->vertex_fetch_shader.atom.dirty = true; + ctx->export_shader.atom.dirty = true; + if (ctx->gs_shader) { + ctx->geometry_shader.atom.dirty = true; + ctx->shader_stages.atom.dirty = true; + ctx->gs_rings.atom.dirty = true; + } ctx->vertex_shader.atom.dirty = true; - ctx->viewport.atom.dirty = true; + ctx->b.streamout.enable_atom.dirty = true; if (ctx->blend_state.cso) ctx->blend_state.atom.dirty = true; @@ -414,50 +348,13 @@ void r600_begin_new_cs(struct r600_context *ctx) r600_sampler_states_dirty(ctx, &samplers->states); } - if (ctx->b.streamout.suspended) { - ctx->b.streamout.append_bitmask = ctx->b.streamout.enabled_mask; - r600_streamout_buffers_dirty(&ctx->b); - } - - /* resume queries */ - if (ctx->nontimer_queries_suspended) { - r600_resume_nontimer_queries(ctx); - } + r600_postflush_resume_features(&ctx->b); /* Re-emit the draw state. */ ctx->last_primitive_type = -1; ctx->last_start_instance = -1; - ctx->initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw; -} - -void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) -{ - struct radeon_winsys_cs *cs = ctx->b.rings.gfx.cs; - uint64_t va; - - r600_need_cs_space(ctx, 10, FALSE); - - va = r600_resource_va(&ctx->screen->b.b, (void*)fence_bo); - va = va + (offset << 2); - - /* Use of WAIT_UNTIL is deprecated on Cayman+ */ - if (ctx->b.family >= CHIP_CAYMAN) { - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); - } else { - r600_write_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); - } - - cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); - cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); - cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ - /* DATA_SEL | INT_EN | ADDRESS_HI */ - cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); - cs->buf[cs->cdw++] = value; /* DATA_LO */ - cs->buf[cs->cdw++] = 0; /* DATA_HI */ - cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); - cs->buf[cs->cdw++] = r600_context_bo_reloc(&ctx->b, &ctx->b.rings.gfx, fence_bo, RADEON_USAGE_WRITE); + ctx->b.initial_gfx_cs_size = ctx->b.rings.gfx.cs->cdw; } /* The max number of bytes to copy per packet. */ @@ -471,15 +368,28 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, struct radeon_winsys_cs *cs = rctx->b.rings.gfx.cs; assert(size); - assert(rctx->screen->has_cp_dma); + assert(rctx->screen->b.has_cp_dma); + + /* Mark the buffer range of destination as valid (initialized), + * so that transfer_map knows it should wait for the GPU when mapping + * that range. */ + util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, + dst_offset + size); dst_offset += r600_resource_va(&rctx->screen->b.b, dst); src_offset += r600_resource_va(&rctx->screen->b.b, src); /* Flush the caches where the resources are bound. */ - r600_flag_resource_cache_flush(rctx, src); - r600_flag_resource_cache_flush(rctx, dst); - rctx->b.flags |= R600_CONTEXT_WAIT_3D_IDLE; + rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE | + R600_CONTEXT_INV_VERTEX_CACHE | + R600_CONTEXT_INV_TEX_CACHE | + R600_CONTEXT_FLUSH_AND_INV | + R600_CONTEXT_FLUSH_AND_INV_CB | + R600_CONTEXT_FLUSH_AND_INV_DB | + R600_CONTEXT_FLUSH_AND_INV_CB_META | + R600_CONTEXT_FLUSH_AND_INV_DB_META | + R600_CONTEXT_STREAMOUT_FLUSH | + R600_CONTEXT_WAIT_3D_IDLE; /* There are differences between R700 and EG in CP DMA, * but we only use the common bits here. */ @@ -501,8 +411,10 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, } /* This must be done after r600_need_cs_space. */ - src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src, RADEON_USAGE_READ); - dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst, RADEON_USAGE_WRITE); + src_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)src, + RADEON_USAGE_READ, RADEON_PRIO_MIN); + dst_reloc = r600_context_bo_reloc(&rctx->b, &rctx->b.rings.gfx, (struct r600_resource*)dst, + RADEON_USAGE_WRITE, RADEON_PRIO_MIN); radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, 0)); radeon_emit(cs, src_offset); /* SRC_ADDR_LO [31:0] */ @@ -521,173 +433,48 @@ void r600_cp_dma_copy_buffer(struct r600_context *rctx, dst_offset += byte_count; } - /* Flush the cache of the dst resource again in case the 3D engine - * has been prefetching it. */ - r600_flag_resource_cache_flush(rctx, dst); - - util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, - dst_offset + size); + /* Invalidate the read caches. */ + rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE | + R600_CONTEXT_INV_VERTEX_CACHE | + R600_CONTEXT_INV_TEX_CACHE; } -void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw) -{ - /* The number of dwords we already used in the DMA so far. */ - num_dw += ctx->b.rings.dma.cs->cdw; - /* Flush if there's not enough space. */ - if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { - ctx->b.rings.dma.flush(ctx, RADEON_FLUSH_ASYNC); - } -} - -void r600_dma_copy(struct r600_context *rctx, - struct pipe_resource *dst, - struct pipe_resource *src, - uint64_t dst_offset, - uint64_t src_offset, - uint64_t size) +void r600_dma_copy_buffer(struct r600_context *rctx, + struct pipe_resource *dst, + struct pipe_resource *src, + uint64_t dst_offset, + uint64_t src_offset, + uint64_t size) { struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs; - unsigned i, ncopy, csize, shift; + unsigned i, ncopy, csize; struct r600_resource *rdst = (struct r600_resource*)dst; struct r600_resource *rsrc = (struct r600_resource*)src; - /* make sure that the dma ring is only one active */ - rctx->b.rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC); + /* Mark the buffer range of destination as valid (initialized), + * so that transfer_map knows it should wait for the GPU when mapping + * that range. */ + util_range_add(&rdst->valid_buffer_range, dst_offset, + dst_offset + size); - size >>= 2; - shift = 2; - ncopy = (size / 0xffff) + !!(size % 0xffff); + size >>= 2; /* convert to dwords */ + ncopy = (size / R600_DMA_COPY_MAX_SIZE_DW) + !!(size % R600_DMA_COPY_MAX_SIZE_DW); - r600_need_dma_space(rctx, ncopy * 5); + r600_need_dma_space(&rctx->b, ncopy * 5); for (i = 0; i < ncopy; i++) { - csize = size < 0xffff ? size : 0xffff; + csize = size < R600_DMA_COPY_MAX_SIZE_DW ? size : R600_DMA_COPY_MAX_SIZE_DW; /* emit reloc before writting cs so that cs is always in consistent state */ - r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ); - r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rsrc, RADEON_USAGE_READ, + RADEON_PRIO_MIN); + r600_context_bo_reloc(&rctx->b, &rctx->b.rings.dma, rdst, RADEON_USAGE_WRITE, + RADEON_PRIO_MIN); cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_COPY, 0, 0, csize); cs->buf[cs->cdw++] = dst_offset & 0xfffffffc; cs->buf[cs->cdw++] = src_offset & 0xfffffffc; cs->buf[cs->cdw++] = (dst_offset >> 32UL) & 0xff; cs->buf[cs->cdw++] = (src_offset >> 32UL) & 0xff; - dst_offset += csize << shift; - src_offset += csize << shift; + dst_offset += csize << 2; + src_offset += csize << 2; size -= csize; } - - util_range_add(&rdst->valid_buffer_range, dst_offset, - dst_offset + size); -} - -/* Flag the cache of the resource for it to be flushed later if the resource - * is bound. Otherwise do nothing. Used for synchronization between engines. - */ -void r600_flag_resource_cache_flush(struct r600_context *rctx, - struct pipe_resource *res) -{ - /* Check vertex buffers. */ - uint32_t mask = rctx->vertex_buffer_state.enabled_mask; - while (mask) { - uint32_t i = u_bit_scan(&mask); - if (rctx->vertex_buffer_state.vb[i].buffer == res) { - rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE; - } - } - - /* Check vertex buffers for compute. */ - mask = rctx->cs_vertex_buffer_state.enabled_mask; - while (mask) { - uint32_t i = u_bit_scan(&mask); - if (rctx->cs_vertex_buffer_state.vb[i].buffer == res) { - rctx->b.flags |= R600_CONTEXT_INV_VERTEX_CACHE; - } - } - - /* Check constant buffers. */ - unsigned shader; - for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) { - struct r600_constbuf_state *state = &rctx->constbuf_state[shader]; - uint32_t mask = state->enabled_mask; - - while (mask) { - unsigned i = u_bit_scan(&mask); - if (state->cb[i].buffer == res) { - rctx->b.flags |= R600_CONTEXT_INV_CONST_CACHE; - - shader = PIPE_SHADER_TYPES; /* break the outer loop */ - break; - } - } - } - - /* Check textures. */ - for (shader = 0; shader < PIPE_SHADER_TYPES; shader++) { - struct r600_samplerview_state *state = &rctx->samplers[shader].views; - uint32_t mask = state->enabled_mask; - - while (mask) { - uint32_t i = u_bit_scan(&mask); - if (&state->views[i]->tex_resource->b.b == res) { - rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE; - - shader = PIPE_SHADER_TYPES; /* break the outer loop */ - break; - } - } - } - - /* Check streamout buffers. */ - int i; - for (i = 0; i < rctx->b.streamout.num_targets; i++) { - if (rctx->b.streamout.targets[i]->b.buffer == res) { - rctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH | - R600_CONTEXT_FLUSH_AND_INV | - R600_CONTEXT_WAIT_3D_IDLE; - break; - } - } - - /* Check colorbuffers. */ - for (i = 0; i < rctx->framebuffer.state.nr_cbufs; i++) { - struct r600_texture *tex; - - if (rctx->framebuffer.state.cbufs[i] == NULL) { - continue; - } - - tex = (struct r600_texture*)rctx->framebuffer.state.cbufs[i]->texture; - - if (rctx->framebuffer.state.cbufs[i]->texture == res) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB | - R600_CONTEXT_FLUSH_AND_INV | - R600_CONTEXT_WAIT_3D_IDLE; - - if (tex->cmask_size || tex->fmask_size) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META; - } - break; - } - - if (tex && tex->cmask && tex->cmask != &tex->resource && &tex->cmask->b.b == res) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META | - R600_CONTEXT_FLUSH_AND_INV | - R600_CONTEXT_WAIT_3D_IDLE; - } - } - - /* Check a depth buffer. */ - if (rctx->framebuffer.state.zsbuf) { - if (rctx->framebuffer.state.zsbuf->texture == res) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB | - R600_CONTEXT_FLUSH_AND_INV | - R600_CONTEXT_WAIT_3D_IDLE; - } - - struct r600_texture *tex = - (struct r600_texture*)rctx->framebuffer.state.zsbuf->texture; - if (tex && tex->htile && &tex->htile->b.b == res) { - rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB_META | - R600_CONTEXT_FLUSH_AND_INV | - R600_CONTEXT_WAIT_3D_IDLE; - } - } }