X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.c;h=793f86ef7062cd31f378a252cca234eb08e91009;hb=4379dcc12d36bf9993a06c628c9426d4f54ba58d;hp=e285608bc7467aebe75eafbb26bbecd0f349ea79;hpb=ec7008f03a509539d3dac9aca01a9bbb710cfbc0;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index e285608bc74..793f86ef706 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -32,6 +32,7 @@ #include "pipe/p_shader_tokens.h" #include "util/u_debug.h" #include "util/u_memory.h" +#include "util/u_screen.h" #include "util/u_simple_shaders.h" #include "util/u_upload_mgr.h" #include "util/u_math.h" @@ -65,12 +66,15 @@ static const struct debug_named_value r600_debug_options[] = { static void r600_destroy_context(struct pipe_context *context) { struct r600_context *rctx = (struct r600_context *)context; - unsigned sh; + unsigned sh, i; r600_isa_destroy(rctx->isa); r600_sb_context_destroy(rctx->sb_context); + for (sh = 0; sh < (rctx->b.chip_class < EVERGREEN ? R600_NUM_HW_STAGES : EG_NUM_HW_STAGES); sh++) { + r600_resource_reference(&rctx->scratch_buffers[sh].buffer, NULL); + } r600_resource_reference(&rctx->dummy_cmask, NULL); r600_resource_reference(&rctx->dummy_fmask, NULL); @@ -101,6 +105,16 @@ static void r600_destroy_context(struct pipe_context *context) } util_unreference_framebuffer_state(&rctx->framebuffer.state); + if (rctx->gs_rings.gsvs_ring.buffer) + pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL); + + if (rctx->gs_rings.esgs_ring.buffer) + pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL); + + for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh) + for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i) + rctx->b.b.set_constant_buffer(context, sh, i, NULL); + if (rctx->blitter) { util_blitter_destroy(rctx->blitter); } @@ -198,7 +212,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, } rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX, - r600_context_gfx_flush, rctx); + r600_context_gfx_flush, rctx, false); rctx->b.gfx.flush = r600_context_gfx_flush; rctx->allocator_fetch_shader = @@ -249,21 +263,23 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_NPOT_TEXTURES: case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: - case PIPE_CAP_TWO_SIDED_STENCIL: case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_OCCLUSION_QUERY: - case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_TEXTURE_MIRROR_CLAMP: + case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_DEPTH_CLIP_DISABLE: + case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - case PIPE_CAP_SM3: + case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: + case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: + case PIPE_CAP_VERTEX_SHADER_SATURATE: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_PRIMITIVE_RESTART: case PIPE_CAP_CONDITIONAL_RENDER: @@ -274,7 +290,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_START_INSTANCE: case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: @@ -301,10 +316,15 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: + case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: return 1; + case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: + /* Optimal number for good TexSubImage performance on Polaris10. */ + return 64 * 1024 * 1024; + case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43; + return rscreen->b.info.drm_minor >= 43; case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr; @@ -338,6 +358,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 330; return 140; + case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: + return 140; + /* Supported except the original R600. */ case PIPE_CAP_INDEP_BLEND_ENABLE: case PIPE_CAP_INDEP_BLEND_FUNC: @@ -352,6 +375,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_TGSI_PACK_HALF_FLOAT: + case PIPE_CAP_TGSI_CLOCK: + case PIPE_CAP_TGSI_ARRAY_COMPONENTS: + case PIPE_CAP_QUERY_BUFFER_OBJECT: return family >= CHIP_CEDAR ? 1 : 0; case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: return family >= CHIP_CEDAR ? 4 : 0; @@ -365,6 +391,15 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: return 8; + case PIPE_CAP_MAX_GS_INVOCATIONS: + return 32; + + /* shader buffer objects */ + case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: + return 1 << 27; + case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS: + return 8; + /* Unsupported features. */ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: @@ -384,20 +419,16 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: case PIPE_CAP_GENERATE_MIPMAP: case PIPE_CAP_STRING_MARKER: - case PIPE_CAP_QUERY_BUFFER_OBJECT: - case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: case PIPE_CAP_NATIVE_FENCE_FD: case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: - case PIPE_CAP_TGSI_FS_FBFETCH: + case PIPE_CAP_FBFETCH: case PIPE_CAP_INT64: case PIPE_CAP_INT64_DIVMOD: case PIPE_CAP_TGSI_TEX_TXF_LZ: - case PIPE_CAP_TGSI_CLOCK: case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: @@ -411,6 +442,18 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: case PIPE_CAP_TILE_RASTER_ORDER: case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: + case PIPE_CAP_CONTEXT_PRIORITY_MASK: + case PIPE_CAP_FENCE_SIGNAL: + case PIPE_CAP_CONSTBUF0_FLAGS: + case PIPE_CAP_PACKED_UNIFORMS: + case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: + case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: + case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: + case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: + case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: return 0; case PIPE_CAP_DOUBLES: @@ -452,10 +495,15 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return family >= CHIP_CEDAR ? 4 : 1; case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE: - return 2047; + /* Should be 2047, but 2048 is a requirement for GL 4.4 */ + return 2048; /* Texturing. */ - case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_2D_SIZE: + if (family >= CHIP_CEDAR) + return 16384; + else + return 8192; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: if (family >= CHIP_CEDAR) return 15; @@ -476,6 +524,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_VIEWPORTS: return R600_MAX_VIEWPORTS; case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: + case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS: return 8; /* Timer queries, present when the clock frequency is non zero. */ @@ -493,6 +542,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; + case PIPE_CAP_MAX_VARYINGS: + return 32; + case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; case PIPE_CAP_ENDIANNESS: @@ -518,8 +570,19 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return rscreen->b.info.pci_dev; case PIPE_CAP_PCI_FUNCTION: return rscreen->b.info.pci_func; + + case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS: + if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) + return 8; + return 0; + case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS: + if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) + return EG_MAX_ATOMIC_BUFFERS; + return 0; + + default: + return u_pipe_screen_get_param_defaults(pscreen, param); } - return 0; } static int r600_get_shader_param(struct pipe_screen* pscreen, @@ -596,13 +659,15 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return 16; case PIPE_SHADER_CAP_PREFERRED_IR: - if (shader == PIPE_SHADER_COMPUTE) { - return PIPE_SHADER_IR_NATIVE; - } else { - return PIPE_SHADER_IR_TGSI; - } - case PIPE_SHADER_CAP_SUPPORTED_IRS: - return (1 << PIPE_SHADER_IR_TGSI); + return PIPE_SHADER_IR_TGSI; + case PIPE_SHADER_CAP_SUPPORTED_IRS: { + int ir = 0; + if (shader == PIPE_SHADER_COMPUTE) + ir = 1 << PIPE_SHADER_IR_NATIVE; + if (rscreen->b.family >= CHIP_CEDAR) + ir |= 1 << PIPE_SHADER_IR_TGSI; + return ir; + } case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: if (rscreen->b.family == CHIP_ARUBA || rscreen->b.family == CHIP_CAYMAN || @@ -633,6 +698,8 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, return EG_MAX_ATOMIC_BUFFERS; } return 0; + case PIPE_SHADER_CAP_SCALAR_ISA: + return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: /* due to a bug in the shader compiler, some loops hang * if they are not unrolled, see: @@ -759,7 +826,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws, R600_CONTEXT_INV_VERTEX_CACHE | R600_CONTEXT_INV_TEX_CACHE | R600_CONTEXT_INV_CONST_CACHE; - rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_PS_PARTIAL_FLUSH; + rscreen->b.barrier_flags.compute_to_L2 = R600_CONTEXT_CS_PARTIAL_FLUSH | R600_CONTEXT_FLUSH_AND_INV; rscreen->global_pool = compute_memory_pool_new(rscreen);