X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.c;h=d65b2841613d2d986077b87ed1b110c9f8b4417c;hb=75b59bb1d6573bd7b16758e528a265623889e551;hp=d9dae26d1c5d78e82fc41afa9173a4a0194cf6b3;hpb=1281608849a058fcdbe2f64481a159d58af3d888;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index d9dae26d1c5..d65b2841613 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -32,6 +32,7 @@ #include "pipe/p_shader_tokens.h" #include "util/u_debug.h" #include "util/u_memory.h" +#include "util/u_screen.h" #include "util/u_simple_shaders.h" #include "util/u_upload_mgr.h" #include "util/u_math.h" @@ -104,6 +105,12 @@ static void r600_destroy_context(struct pipe_context *context) } util_unreference_framebuffer_state(&rctx->framebuffer.state); + if (rctx->gs_rings.gsvs_ring.buffer) + pipe_resource_reference(&rctx->gs_rings.gsvs_ring.buffer, NULL); + + if (rctx->gs_rings.esgs_ring.buffer) + pipe_resource_reference(&rctx->gs_rings.esgs_ring.buffer, NULL); + for (sh = 0; sh < PIPE_SHADER_TYPES; ++sh) for (i = 0; i < PIPE_MAX_CONSTANT_BUFFERS; ++i) rctx->b.b.set_constant_buffer(context, sh, i, NULL); @@ -148,7 +155,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, goto fail; rctx->screen = rscreen; - LIST_INITHEAD(&rctx->texture_buffers); + list_inithead(&rctx->texture_buffers); r600_init_blit_functions(rctx); @@ -205,7 +212,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, } rctx->b.gfx.cs = ws->cs_create(rctx->b.ctx, RING_GFX, - r600_context_gfx_flush, rctx); + r600_context_gfx_flush, rctx, false); rctx->b.gfx.flush = r600_context_gfx_flush; rctx->allocator_fetch_shader = @@ -242,6 +249,12 @@ fail: return NULL; } +static bool is_nir_enabled(struct r600_common_screen *screen) { + return (screen->debug_flags & DBG_NIR && + screen->family >= CHIP_CEDAR && + screen->family < CHIP_CAYMAN); +} + /* * pipe_screen */ @@ -264,14 +277,18 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_DEPTH_CLIP_DISABLE: + case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE: case PIPE_CAP_SHADER_STENCIL_EXPORT: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - case PIPE_CAP_SM3: + case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD: + case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES: + case PIPE_CAP_VERTEX_SHADER_SATURATE: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_PRIMITIVE_RESTART: + case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX: case PIPE_CAP_CONDITIONAL_RENDER: case PIPE_CAP_TEXTURE_BARRIER: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: @@ -309,8 +326,12 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: return 1; + case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET: + /* Optimal number for good TexSubImage performance on Polaris10. */ + return 64 * 1024 * 1024; + case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - return rscreen->b.info.drm_major == 2 && rscreen->b.info.drm_minor >= 43; + return rscreen->b.info.drm_minor >= 43; case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return !R600_BIG_ENDIAN && rscreen->b.info.has_userptr; @@ -319,8 +340,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return rscreen->b.chip_class > R700; case PIPE_CAP_TGSI_TEXCOORD: - return 0; + return 1; + case PIPE_CAP_NIR_IMAGES_AS_DEREF: case PIPE_CAP_FAKE_SW_MSAA: return 0; @@ -379,63 +401,14 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_GS_INVOCATIONS: return 32; + + /* shader buffer objects */ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE: return 1 << 27; + case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS: + return 8; - /* Unsupported features. */ - case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: - case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: - case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: - case PIPE_CAP_VERTEX_COLOR_CLAMPED: - case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_TEXTURE_GATHER_OFFSETS: - case PIPE_CAP_VERTEXID_NOBASE: - case PIPE_CAP_DEPTH_BOUNDS_TEST: - case PIPE_CAP_FORCE_PERSAMPLE_INTERP: - case PIPE_CAP_SHAREABLE_SHADERS: - case PIPE_CAP_DRAW_PARAMETERS: - case PIPE_CAP_MULTI_DRAW_INDIRECT: - case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: - case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: - case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: - case PIPE_CAP_GENERATE_MIPMAP: - case PIPE_CAP_STRING_MARKER: - case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: - case PIPE_CAP_TGSI_VOTE: - case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: - case PIPE_CAP_NATIVE_FENCE_FD: case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: - case PIPE_CAP_TGSI_FS_FBFETCH: - case PIPE_CAP_INT64: - case PIPE_CAP_INT64_DIVMOD: - case PIPE_CAP_TGSI_TEX_TXF_LZ: - case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: - case PIPE_CAP_TGSI_BALLOT: - case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: - case PIPE_CAP_POST_DEPTH_COVERAGE: - case PIPE_CAP_BINDLESS_TEXTURE: - case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: - case PIPE_CAP_QUERY_SO_OVERFLOW: - case PIPE_CAP_MEMOBJ: - case PIPE_CAP_LOAD_CONSTBUF: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: - case PIPE_CAP_TILE_RASTER_ORDER: - case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: - case PIPE_CAP_CONTEXT_PRIORITY_MASK: - case PIPE_CAP_FENCE_SIGNAL: - case PIPE_CAP_CONSTBUF0_FLAGS: - case PIPE_CAP_PACKED_UNIFORMS: - case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: - case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: - case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS: return 0; case PIPE_CAP_DOUBLES: @@ -481,7 +454,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return 2048; /* Texturing. */ - case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: + case PIPE_CAP_MAX_TEXTURE_2D_SIZE: + if (family >= CHIP_CEDAR) + return 16384; + else + return 8192; case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: if (family >= CHIP_CEDAR) return 15; @@ -502,6 +479,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_VIEWPORTS: return R600_MAX_VIEWPORTS; case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: + case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS: return 8; /* Timer queries, present when the clock frequency is non zero. */ @@ -519,6 +497,9 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; + case PIPE_CAP_MAX_VARYINGS: + return 32; + case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; case PIPE_CAP_ENDIANNESS: @@ -544,8 +525,19 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) return rscreen->b.info.pci_dev; case PIPE_CAP_PCI_FUNCTION: return rscreen->b.info.pci_func; + + case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS: + if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) + return 8; + return 0; + case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS: + if (rscreen->b.family >= CHIP_CEDAR && rscreen->has_atomics) + return EG_MAX_ATOMIC_BUFFERS; + return 0; + + default: + return u_pipe_screen_get_param_defaults(pscreen, param); } - return 0; } static int r600_get_shader_param(struct pipe_screen* pscreen, @@ -558,7 +550,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, { case PIPE_SHADER_FRAGMENT: case PIPE_SHADER_VERTEX: - case PIPE_SHADER_COMPUTE: break; case PIPE_SHADER_GEOMETRY: if (rscreen->b.family >= CHIP_CEDAR) @@ -567,10 +558,16 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, if (rscreen->b.info.drm_minor >= 37) break; return 0; + /* With NIR we currently disable TES, TCS and COMP shaders */ case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_EVAL: if (rscreen->b.family >= CHIP_CEDAR) break; + /* fallthrough */ + case PIPE_SHADER_COMPUTE: + if (!is_nir_enabled(&rscreen->b)) + break; + /* fallthrough */ default: return 0; } @@ -592,9 +589,11 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: if (shader == PIPE_SHADER_COMPUTE) { uint64_t max_const_buffer_size; - pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI, - PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, - &max_const_buffer_size); + enum pipe_shader_ir ir_type = is_nir_enabled(&rscreen->b) ? + PIPE_SHADER_IR_NIR: PIPE_SHADER_IR_TGSI; + pscreen->get_compute_param(pscreen, ir_type, + PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE, + &max_const_buffer_size); return MIN2(max_const_buffer_size, INT_MAX); } else { @@ -614,6 +613,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_INT64_ATOMICS: case PIPE_SHADER_CAP_FP16: + case PIPE_SHADER_CAP_FP16_DERIVATIVES: + case PIPE_SHADER_CAP_INT16: + case PIPE_SHADER_CAP_GLSL_16BIT_TEMPS: return 0; case PIPE_SHADER_CAP_INTEGERS: case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: @@ -621,14 +623,19 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS: return 16; - case PIPE_SHADER_CAP_PREFERRED_IR: + case PIPE_SHADER_CAP_PREFERRED_IR: + if (is_nir_enabled(&rscreen->b)) + return PIPE_SHADER_IR_NIR; return PIPE_SHADER_IR_TGSI; case PIPE_SHADER_CAP_SUPPORTED_IRS: { int ir = 0; if (shader == PIPE_SHADER_COMPUTE) ir = 1 << PIPE_SHADER_IR_NATIVE; - if (rscreen->b.family >= CHIP_CEDAR) + if (rscreen->b.family >= CHIP_CEDAR) { ir |= 1 << PIPE_SHADER_IR_TGSI; + if (is_nir_enabled(&rscreen->b)) + ir |= 1 << PIPE_SHADER_IR_NIR; + } return ir; } case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED: @@ -661,8 +668,6 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, return EG_MAX_ATOMIC_BUFFERS; } return 0; - case PIPE_SHADER_CAP_SCALAR_ISA: - return 0; case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT: /* due to a bug in the shader compiler, some loops hang * if they are not unrolled, see: