X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.h;h=239005cab7ff205e420c63f7eedc92e659054941;hb=10cc2518426eccdd2d232af9e2366be013e31af8;hp=d0774de857366c8509f55991424e1825f81c0aa5;hpb=005c8e01062e8e88a86904b955d5422742bd32e7;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index d0774de8573..239005cab7f 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -26,21 +26,28 @@ #ifndef R600_PIPE_H #define R600_PIPE_H -#include "radeon/r600_pipe_common.h" -#include "radeon/r600_cs.h" - -#include "r600_llvm.h" +#include "r600_pipe_common.h" +#include "r600_cs.h" #include "r600_public.h" +#include "pipe/p_defines.h" #include "util/u_suballoc.h" #include "util/list.h" #include "util/u_transfer.h" +#include "util/u_memory.h" #include "tgsi/tgsi_scan.h" -#define R600_NUM_ATOMS 42 +#define R600_NUM_ATOMS 56 -#define R600_MAX_VIEWPORTS 16 +#define R600_MAX_IMAGES 8 +/* + * ranges reserved for images on evergreen + * first set for the immediate buffers, + * second for the actual resources for RESQ. + */ +#define R600_IMAGE_IMMED_RESOURCE_OFFSET 160 +#define R600_IMAGE_REAL_RESOURCE_OFFSET 168 /* read caches */ #define R600_CONTEXT_INV_VERTEX_CACHE (R600_CONTEXT_PRIVATE_FLAG << 0) @@ -56,22 +63,38 @@ #define R600_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8) #define R600_CONTEXT_WAIT_3D_IDLE (R600_CONTEXT_PRIVATE_FLAG << 9) #define R600_CONTEXT_WAIT_CP_DMA_IDLE (R600_CONTEXT_PRIVATE_FLAG << 10) +#define R600_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11) /* the number of CS dwords for flushing and drawing */ -#define R600_MAX_FLUSH_CS_DWORDS 16 -#define R600_MAX_DRAW_CS_DWORDS 47 -#define R600_TRACE_CS_DWORDS 7 +#define R600_MAX_FLUSH_CS_DWORDS 18 +#define R600_MAX_DRAW_CS_DWORDS 58 +#define R600_MAX_PFP_SYNC_ME_DWORDS 16 -#define R600_MAX_USER_CONST_BUFFERS 13 -#define R600_MAX_DRIVER_CONST_BUFFERS 2 +#define EG_MAX_ATOMIC_BUFFERS 8 + +#define R600_MAX_USER_CONST_BUFFERS 15 +#define R600_MAX_DRIVER_CONST_BUFFERS 3 #define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS) +#define R600_MAX_HW_CONST_BUFFERS 16 /* start driver buffers after user buffers */ #define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) #define R600_UCP_SIZE (4*4*8) +#define R600_CS_BLOCK_GRID_SIZE (8 * 4) +#define R600_TCS_DEFAULT_LEVELS_SIZE (6 * 4) #define R600_BUFFER_INFO_OFFSET (R600_UCP_SIZE) -#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) +/* + * We only access this buffer through vtx clauses hence it's fine to exist + * at index beyond 15. + */ +#define R600_LDS_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) +/* + * Note GS doesn't use a constant buffer binding, just a resource index, + * so it's fine to have it exist at index beyond 15. I.e. it's not actually + * a const buffer, just a buffer resource. + */ +#define R600_GS_RING_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) /* Currently R600_MAX_CONST_BUFFERS just fits on the hw, which has a limit * of 16 const buffers. * UCP/SAMPLE_POSITIONS are never accessed by same shader stage so they can use the same id. @@ -81,11 +104,16 @@ */ #define R600_MAX_CONST_BUFFER_SIZE (4096 * sizeof(float[4])) -#ifdef PIPE_ARCH_BIG_ENDIAN -#define R600_BIG_ENDIAN 1 -#else -#define R600_BIG_ENDIAN 0 -#endif +/* HW stages */ +#define R600_HW_STAGE_PS 0 +#define R600_HW_STAGE_VS 1 +#define R600_HW_STAGE_GS 2 +#define R600_HW_STAGE_ES 3 +#define EG_HW_STAGE_LS 4 +#define EG_HW_STAGE_HS 5 + +#define R600_NUM_HW_STAGES 4 +#define EG_NUM_HW_STAGES 6 struct r600_context; struct r600_bytecode; @@ -107,14 +135,16 @@ struct r600_db_state { struct r600_db_misc_state { struct r600_atom atom; - bool occlusion_query_enabled; + bool occlusion_queries_disabled; bool flush_depthstencil_through_cb; - bool flush_depthstencil_in_place; + bool flush_depth_inplace; + bool flush_stencil_inplace; bool copy_depth, copy_stencil; unsigned copy_sample; unsigned log_samples; unsigned db_shader_control; bool htile_clear; + uint8_t ps_conservative_z; }; struct r600_cb_misc_state { @@ -122,7 +152,11 @@ struct r600_cb_misc_state { unsigned cb_color_control; /* this comes from blend state */ unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ unsigned nr_cbufs; + unsigned bound_cbufs_target_mask; unsigned nr_ps_color_outputs; + unsigned ps_color_export_mask; + unsigned image_rat_enabled_mask; + unsigned buffer_rat_enabled_mask; bool multiwrite; bool dual_src_blend; }; @@ -132,8 +166,11 @@ struct r600_clip_misc_state { unsigned pa_cl_clip_cntl; /* from rasterizer */ unsigned pa_cl_vs_out_cntl; /* from vertex shader */ unsigned clip_plane_enable; /* from rasterizer */ + unsigned cc_dist_mask; /* from vertex shader */ unsigned clip_dist_write; /* from vertex shader */ + unsigned cull_dist_write; /* from vertex shader */ boolean clip_disable; /* from vertex shader */ + boolean vs_out_viewport; /* from vertex shader */ }; struct r600_alphatest_state { @@ -177,6 +214,8 @@ struct r600_framebuffer { bool export_16bpc; bool cb0_is_integer; bool is_msaa_resolve; + bool dual_src_blend; + bool do_update_surf_dirtiness; }; struct r600_sample_mask { @@ -188,6 +227,8 @@ struct r600_config_state { struct r600_atom atom; unsigned sq_gpr_resource_mgmt_1; unsigned sq_gpr_resource_mgmt_2; + unsigned sq_gpr_resource_mgmt_3; + bool dyn_gpr_enabled; }; struct r600_stencil_ref @@ -203,12 +244,6 @@ struct r600_stencil_ref_state { struct pipe_stencil_ref pipe_state; }; -struct r600_viewport_state { - struct r600_atom atom; - struct pipe_viewport_state state[R600_MAX_VIEWPORTS]; - uint32_t dirty_mask; -}; - struct r600_shader_stages_state { struct r600_atom atom; unsigned geom_enable; @@ -223,7 +258,6 @@ struct r600_gs_rings_state { /* This must start from 16. */ /* features */ -#define DBG_LLVM (1 << 29) #define DBG_NO_CP_DMA (1 << 30) /* shader backend */ #define DBG_NO_SB (1 << 21) @@ -239,6 +273,7 @@ struct r600_screen { struct r600_common_screen b; bool has_msaa; bool has_compressed_msaa_texturing; + bool has_atomics; /*for compute global memory binding, we allocate stuff here, instead of * buffers. @@ -253,6 +288,7 @@ struct r600_pipe_sampler_view { struct r600_resource *tex_resource; uint32_t tex_resource_words[8]; bool skip_mip_address_reloc; + bool is_stencil_sampler; }; struct r600_rasterizer_state { @@ -267,8 +303,11 @@ struct r600_rasterizer_state { float offset_units; float offset_scale; bool offset_enable; + bool offset_units_unscaled; bool scissor_enable; bool multisample_enable; + bool clip_halfz; + bool rasterizer_discard; }; struct r600_poly_offset_state { @@ -276,6 +315,7 @@ struct r600_poly_offset_state { enum pipe_format zs_format; float offset_units; float offset_scale; + bool offset_units_unscaled; }; struct r600_blend_state { @@ -308,14 +348,16 @@ struct r600_pipe_shader_selector { unsigned num_shaders; - /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ - unsigned type; + enum pipe_shader_type type; /* geometry shader properties */ - unsigned gs_output_prim; - unsigned gs_max_out_vertices; - unsigned gs_num_invocations; + enum pipe_prim_type gs_output_prim; + unsigned gs_max_out_vertices; + unsigned gs_num_invocations; + /* TCS/VS */ + uint64_t lds_patch_outputs_written_mask; + uint64_t lds_outputs_written_mask; unsigned nr_ps_max_color_exports; }; @@ -362,9 +404,11 @@ struct r600_shader_driver_constants_info { /* currently 128 bytes for UCP/samplepos + sampler buffer constants */ uint32_t *constants; uint32_t alloc_size; - bool vs_ucp_dirty; bool texture_const_dirty; + bool vs_ucp_dirty; bool ps_sample_pos_dirty; + bool cs_block_grid_size_dirty; + bool tcs_default_levels_dirty; }; struct r600_constbuf_state @@ -391,14 +435,6 @@ struct r600_cso_state struct r600_command_buffer *cb; }; -struct r600_scissor_state -{ - struct r600_atom atom; - struct pipe_scissor_state scissor[R600_MAX_VIEWPORTS]; - uint32_t dirty_mask; - bool enable; /* r6xx only */ -}; - struct r600_fetch_shader { struct r600_resource *buffer; unsigned offset; @@ -409,6 +445,45 @@ struct r600_shader_state { struct r600_pipe_shader *shader; }; +struct r600_atomic_buffer_state { + struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS]; +}; + +struct r600_image_view { + struct pipe_image_view base; + uint32_t cb_color_base; + uint32_t cb_color_pitch; + uint32_t cb_color_slice; + uint32_t cb_color_view; + uint32_t cb_color_info; + uint32_t cb_color_attrib; + uint32_t cb_color_dim; + uint32_t cb_color_fmask; + uint32_t cb_color_fmask_slice; + uint32_t immed_resource_words[8]; + uint32_t resource_words[8]; + bool skip_mip_address_reloc; + uint32_t buf_size; +}; + +struct r600_image_state { + struct r600_atom atom; + uint32_t enabled_mask; + uint32_t dirty_mask; + uint32_t compressed_depthtex_mask; + uint32_t compressed_colortex_mask; + boolean dirty_buffer_constants; + struct r600_image_view views[R600_MAX_IMAGES]; +}; + +/* Used to spill shader temps */ +struct r600_scratch_buffer { + struct r600_resource *buffer; + boolean dirty; + unsigned size; + unsigned item_size; +}; + struct r600_context { struct r600_common_context b; struct r600_screen *screen; @@ -417,8 +492,8 @@ struct r600_context { /* Hardware info. */ boolean has_vertex_cache; - boolean keep_tiling_flags; - unsigned default_ps_gprs, default_vs_gprs; + unsigned default_gprs[EG_NUM_HW_STAGES]; + unsigned current_gprs[EG_NUM_HW_STAGES]; unsigned r6xx_num_clause_temp_gprs; /* Miscellaneous state objects. */ @@ -459,18 +534,19 @@ struct r600_context { struct r600_poly_offset_state poly_offset_state; struct r600_cso_state rasterizer_state; struct r600_sample_mask sample_mask; - struct r600_scissor_state scissor; struct r600_seamless_cube_map seamless_cube_map; struct r600_config_state config_state; struct r600_stencil_ref_state stencil_ref; struct r600_vgt_state vgt_state; - struct r600_viewport_state viewport; + struct r600_atomic_buffer_state atomic_buffer_state; + /* only have images on fragment shader */ + struct r600_image_state fragment_images; + struct r600_image_state compute_images; + struct r600_image_state fragment_buffers; + struct r600_image_state compute_buffers; /* Shaders and shader resources. */ struct r600_cso_state vertex_fetch_shader; - struct r600_shader_state vertex_shader; - struct r600_shader_state pixel_shader; - struct r600_shader_state geometry_shader; - struct r600_shader_state export_shader; + struct r600_shader_state hw_shader_stages[EG_NUM_HW_STAGES]; struct r600_cs_shader_state cs_shader_state; struct r600_shader_stages_state shader_stages; struct r600_gs_rings_state gs_rings; @@ -489,31 +565,61 @@ struct r600_context { struct r600_pipe_shader_selector *ps_shader; struct r600_pipe_shader_selector *vs_shader; struct r600_pipe_shader_selector *gs_shader; + + struct r600_pipe_shader_selector *tcs_shader; + struct r600_pipe_shader_selector *tes_shader; + + struct r600_pipe_shader_selector *fixed_func_tcs_shader; + struct r600_rasterizer_state *rasterizer; bool alpha_to_one; bool force_blend_disable; + bool gs_tri_strip_adj_fix; boolean dual_src_blend; unsigned zwritemask; - int ps_iter_samples; + unsigned ps_iter_samples; - /* Index buffer. */ - struct pipe_index_buffer index_buffer; + /* The list of all texture buffer objects in this context. + * This list is walked when a buffer is invalidated/reallocated and + * the GPU addresses are updated. */ + struct list_head texture_buffers; /* Last draw state (-1 = unset). */ - int last_primitive_type; /* Last primitive type used in draw_vbo. */ - int last_start_instance; + enum pipe_prim_type last_primitive_type; /* Last primitive type used in draw_vbo. */ + enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ + enum pipe_prim_type last_rast_prim; + unsigned last_start_instance; void *sb_context; struct r600_isa *isa; float sample_positions[4 * 16]; + float tess_state[8]; + uint32_t cs_block_grid_sizes[8]; /* 3 for grid + 1 pad, 3 for block + 1 pad*/ + struct r600_pipe_shader_selector *last_ls; + struct r600_pipe_shader_selector *last_tcs; + unsigned last_num_tcs_input_cp; + unsigned lds_alloc; + + struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)]; + + /* Debug state. */ + bool is_debug; + struct radeon_saved_cs last_gfx; + struct r600_resource *last_trace_buf; + struct r600_resource *trace_buf; + unsigned trace_id; + + bool cmd_buf_is_compute; + struct pipe_resource *append_fence; + uint32_t append_fence_id; }; -static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, +static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs, struct r600_command_buffer *cb) { - assert(cs->cdw + cb->num_dw <= cs->max_dw); - memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw); - cs->cdw += cb->num_dw; + assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); + memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw); + cs->current.cdw += cb->num_dw; } static inline void r600_set_atom_dirty(struct r600_context *rctx, @@ -537,15 +643,10 @@ static inline void r600_mark_atom_dirty(struct r600_context *rctx, r600_set_atom_dirty(rctx, atom, true); } -void r600_trace_emit(struct r600_context *rctx); - static inline void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) { atom->emit(&rctx->b, atom); r600_set_atom_dirty(rctx, atom, false); - if (rctx->screen->b.trace_bo) { - r600_trace_emit(rctx); - } } static inline void r600_set_cso_state(struct r600_context *rctx, @@ -577,7 +678,8 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx, const struct pipe_sampler_view *state, unsigned width0, unsigned height0, unsigned force_level); -void evergreen_init_common_regs(struct r600_command_buffer *cb, +void evergreen_init_common_regs(struct r600_context *ctx, + struct r600_command_buffer *cb, enum chip_class ctx_chip_class, enum radeon_family ctx_family, int ctx_drm_minor); @@ -592,6 +694,8 @@ void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader void evergreen_update_es_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_update_gs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void evergreen_update_ls_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void evergreen_update_hs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void *evergreen_create_db_flush_dsa(struct r600_context *rctx); void *evergreen_create_resolve_blend(struct r600_context *rctx); void *evergreen_create_decompress_blend(struct r600_context *rctx); @@ -600,19 +704,27 @@ boolean evergreen_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, + unsigned storage_sample_count, unsigned usage); void evergreen_init_color_surface(struct r600_context *rctx, struct r600_surface *surf); void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_surface *surf); void evergreen_update_db_shader_control(struct r600_context * rctx); - +bool evergreen_adjust_gprs(struct r600_context *rctx); +void evergreen_setup_scratch_buffers(struct r600_context *rctx); +uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a, + unsigned nr_cbufs); /* r600_blit.c */ void r600_init_blit_functions(struct r600_context *rctx); void r600_decompress_depth_textures(struct r600_context *rctx, struct r600_samplerview_state *textures); +void r600_decompress_depth_images(struct r600_context *rctx, + struct r600_image_state *images); void r600_decompress_color_textures(struct r600_context *rctx, struct r600_samplerview_state *textures); +void r600_decompress_color_images(struct r600_context *rctx, + struct r600_image_state *images); void r600_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dst_level, @@ -649,22 +761,26 @@ boolean r600_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, + unsigned storage_sample_count, unsigned usage); void r600_update_db_shader_control(struct r600_context * rctx); +void r600_setup_scratch_buffers(struct r600_context *rctx); /* r600_hw_context.c */ void r600_context_gfx_flush(void *context, unsigned flags, struct pipe_fence_handle **fence); void r600_begin_new_cs(struct r600_context *ctx); void r600_flush_emit(struct r600_context *ctx); -void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in, unsigned num_atomics); +void r600_emit_pfp_sync_me(struct r600_context *rctx); void r600_cp_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t dst_offset, struct pipe_resource *src, uint64_t src_offset, unsigned size); void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t offset, - unsigned size, uint32_t clear_value); + unsigned size, uint32_t clear_value, + enum r600_coherency coher); void r600_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, struct pipe_resource *src, @@ -681,6 +797,18 @@ void evergreen_dma_copy_buffer(struct r600_context *rctx, uint64_t dst_offset, uint64_t src_offset, uint64_t size); +void evergreen_setup_tess_constants(struct r600_context *rctx, + const struct pipe_draw_info *info, + unsigned *num_patches); +uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, + const struct pipe_draw_info *info, + unsigned num_patches); +void evergreen_set_ls_hs_config(struct r600_context *rctx, + struct radeon_cmdbuf *cs, + uint32_t ls_hs_config); +void evergreen_set_lds_alloc(struct r600_context *rctx, + struct radeon_cmdbuf *cs, + uint32_t lds_alloc); /* r600_state_common.c */ void r600_init_common_state_functions(struct r600_context *rctx); @@ -690,7 +818,6 @@ void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom); -void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a); void r600_add_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id); void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id, @@ -703,25 +830,25 @@ void r600_sampler_states_dirty(struct r600_context *rctx, struct r600_sampler_states *state); void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); void r600_set_sample_locations_constant_buffer(struct r600_context *rctx); +void r600_setup_scratch_area_for_shader(struct r600_context *rctx, + struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch, + unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg); uint32_t r600_translate_stencil_op(int s_op); uint32_t r600_translate_fill(uint32_t func); unsigned r600_tex_wrap(unsigned wrap); -unsigned r600_tex_filter(unsigned filter); unsigned r600_tex_mipfilter(unsigned filter); unsigned r600_tex_compare(unsigned compare); bool sampler_state_needs_border_color(const struct pipe_sampler_state *state); -struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, - struct pipe_resource *texture, - const struct pipe_surface *templ, - unsigned width, unsigned height); unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, const unsigned char *swizzle_view, boolean vtx); uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, const unsigned char *swizzle_view, - uint32_t *word4_p, uint32_t *yuv_format_p); -uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format); -uint32_t r600_colorformat_endian_swap(uint32_t colorformat); + uint32_t *word4_p, uint32_t *yuv_format_p, + bool do_endian_swap); +uint32_t r600_translate_colorformat(enum chip_class chip, enum pipe_format format, + bool do_endian_swap); +uint32_t r600_colorformat_endian_swap(uint32_t colorformat, bool do_endian_swap); /* r600_uvd.c */ struct pipe_video_codec *r600_uvd_create_decoder(struct pipe_context *context, @@ -745,9 +872,9 @@ struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, #define R600_LOOP_CONST_OFFSET 0X0003E200 #define EG_LOOP_CONST_OFFSET 0x0003A200 -#define PKT_TYPE_S(x) (((x) & 0x3) << 30) -#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) -#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) +#define PKT_TYPE_S(x) (((unsigned)(x) & 0x3) << 30) +#define PKT_COUNT_S(x) (((unsigned)(x) & 0x3FFF) << 16) +#define PKT3_IT_OPCODE_S(x) (((unsigned)(x) & 0xFF) << 8) #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) @@ -853,28 +980,28 @@ static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); void r600_release_command_buffer(struct r600_command_buffer *cb); -static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { radeon_set_context_reg_seq(cs, reg, num); /* Set the compute bit on the packet header */ - cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; + cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; } -static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); - assert(cs->cdw+2+num <= cs->max_dw); - cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); - cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; + assert(cs->current.cdw + 2 + num <= cs->current.max_dw); + radeon_emit(cs, PKT3(PKT3_SET_CTL_CONST, num, 0)); + radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2); } -static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_compute_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) +static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag) { if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { radeon_compute_set_context_reg(cs, reg, value); @@ -883,7 +1010,7 @@ static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsi } } -static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_ctl_const_seq(cs, reg, 1); radeon_emit(cs, value); @@ -892,11 +1019,6 @@ static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned re /* * common helpers */ -static inline uint32_t S_FIXED(float value, uint32_t frac_bits) -{ - return value * (1 << frac_bits); -} -#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) /* 12.4 fixed-point */ static inline unsigned r600_pack_float_12p4(float x) @@ -905,12 +1027,21 @@ static inline unsigned r600_pack_float_12p4(float x) x >= 4096 ? 0xffff : x * 16; } -/* Return if the depth format can be read without the DB->CB copy on r6xx-r7xx. */ -static inline bool r600_can_read_depth(struct r600_texture *rtex) +static inline unsigned r600_get_flush_flags(enum r600_coherency coher) { - return rtex->resource.b.b.nr_samples <= 1 && - (rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM || - rtex->resource.b.b.format == PIPE_FORMAT_Z32_FLOAT); + switch (coher) { + default: + case R600_COHERENCY_NONE: + return 0; + case R600_COHERENCY_SHADER: + return R600_CONTEXT_INV_CONST_CACHE | + R600_CONTEXT_INV_VERTEX_CACHE | + R600_CONTEXT_INV_TEX_CACHE | + R600_CONTEXT_STREAMOUT_FLUSH; + case R600_COHERENCY_CB_META: + return R600_CONTEXT_FLUSH_AND_INV_CB | + R600_CONTEXT_FLUSH_AND_INV_CB_META; + } } #define V_028A6C_OUTPRIM_TYPE_POINTLIST 0 @@ -918,4 +1049,36 @@ static inline bool r600_can_read_depth(struct r600_texture *rtex) #define V_028A6C_OUTPRIM_TYPE_TRISTRIP 2 unsigned r600_conv_prim_to_gs_out(unsigned mode); + +void eg_trace_emit(struct r600_context *rctx); +void eg_dump_debug_state(struct pipe_context *ctx, FILE *f, + unsigned flags); + +struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx, + const struct tgsi_token *tokens, + unsigned pipe_shader_type); +int r600_shader_select(struct pipe_context *ctx, + struct r600_pipe_shader_selector* sel, + bool *dirty); + +void r600_delete_shader_selector(struct pipe_context *ctx, + struct r600_pipe_shader_selector *sel); + +struct r600_shader_atomic; +void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx, + struct r600_pipe_shader *cs_shader, + struct r600_shader_atomic *combined_atomics, + uint8_t *atomic_used_mask_p); +void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, + bool is_compute, + struct r600_shader_atomic *combined_atomics, + uint8_t atomic_used_mask); +void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, + bool is_compute, + struct r600_shader_atomic *combined_atomics, + uint8_t *atomic_used_mask_p); +void r600_update_compressed_resource_state(struct r600_context *rctx, bool compute_only); + +void eg_setup_buffer_constants(struct r600_context *rctx, int shader_type); +void r600_update_driver_const_buffers(struct r600_context *rctx, bool compute_only); #endif