X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.h;h=bb4e429aeb203ea225f4895263c4764ff1e21a08;hb=df27320560cfef439aa299dcea12b900195294c3;hp=ee021ed8980a3a2bb921d6f9e845bdd3bfa3a431;hpb=fd2e34d557c07fba5a6e344e915f73dcfb66d0b4;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index ee021ed8980..bb4e429aeb2 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -28,16 +28,29 @@ #include "util/u_blitter.h" #include "util/u_slab.h" -#include "r600.h" +#include "util/u_suballoc.h" +#include "util/u_double_list.h" +#include "util/u_transfer.h" #include "r600_llvm.h" #include "r600_public.h" -#include "r600_shader.h" #include "r600_resource.h" -#include "evergreen_compute.h" -#define R600_MAX_ATOM 17 +#define R600_NUM_ATOMS 41 + +/* the number of CS dwords for flushing and drawing */ +#define R600_MAX_FLUSH_CS_DWORDS 16 +#define R600_MAX_DRAW_CS_DWORDS 34 +#define R600_TRACE_CS_DWORDS 7 + +#define R600_MAX_USER_CONST_BUFFERS 13 +#define R600_MAX_DRIVER_CONST_BUFFERS 3 +#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS) + +/* start driver buffers after user buffers */ +#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS) +#define R600_TXQ_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 1) +#define R600_BUFFER_INFO_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS + 2) -#define R600_MAX_CONST_BUFFERS 2 #define R600_MAX_CONST_BUFFER_SIZE 4096 #ifdef PIPE_ARCH_BIG_ENDIAN @@ -46,6 +59,29 @@ #define R600_BIG_ENDIAN 0 #endif +#define R600_MAP_BUFFER_ALIGNMENT 64 + +#define R600_ERR(fmt, args...) \ + fprintf(stderr, "EE %s:%d %s - "fmt, __FILE__, __LINE__, __func__, ##args) + +#define R600_CONTEXT_INVAL_READ_CACHES (1 << 0) +#define R600_CONTEXT_STREAMOUT_FLUSH (1 << 1) +#define R600_CONTEXT_WAIT_3D_IDLE (1 << 2) +#define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 3) +#define R600_CONTEXT_FLUSH_AND_INV (1 << 4) +#define R600_CONTEXT_FLUSH_AND_INV_CB_META (1 << 5) +#define R600_CONTEXT_PS_PARTIAL_FLUSH (1 << 6) +#define R600_CONTEXT_FLUSH_AND_INV_DB_META (1 << 7) + +#define R600_QUERY_DRAW_CALLS (PIPE_QUERY_DRIVER_SPECIFIC + 0) +#define R600_QUERY_REQUESTED_VRAM (PIPE_QUERY_DRIVER_SPECIFIC + 1) +#define R600_QUERY_REQUESTED_GTT (PIPE_QUERY_DRIVER_SPECIFIC + 2) +#define R600_QUERY_BUFFER_WAIT_TIME (PIPE_QUERY_DRIVER_SPECIFIC + 3) + +struct r600_context; +struct r600_bytecode; +struct r600_shader_key; + /* This encapsulates a state or an operation which can emitted into the GPU * command stream. It's not limited to states only, it can be used for anything * that wants to write commands into the CS (e.g. cache flushes). */ @@ -59,19 +95,27 @@ struct r600_atom { /* This is an atom containing GPU commands that never change. * This is supposed to be copied directly into the CS. */ struct r600_command_buffer { - struct r600_atom atom; uint32_t *buf; + unsigned num_dw; unsigned max_num_dw; unsigned pkt_flags; }; +struct r600_db_state { + struct r600_atom atom; + struct r600_surface *rsurf; +}; + struct r600_db_misc_state { - struct r600_atom atom; - bool occlusion_query_enabled; - bool flush_depthstencil_through_cb; - bool copy_depth, copy_stencil; - unsigned copy_sample; - unsigned log_samples; + struct r600_atom atom; + bool occlusion_query_enabled; + bool flush_depthstencil_through_cb; + bool flush_depthstencil_in_place; + bool copy_depth, copy_stencil; + unsigned copy_sample; + unsigned log_samples; + unsigned db_shader_control; + bool htile_clear; }; struct r600_cb_misc_state { @@ -84,6 +128,14 @@ struct r600_cb_misc_state { bool dual_src_blend; }; +struct r600_clip_misc_state { + struct r600_atom atom; + unsigned pa_cl_clip_cntl; /* from rasterizer */ + unsigned pa_cl_vs_out_cntl; /* from vertex shader */ + unsigned clip_plane_enable; /* from rasterizer */ + unsigned clip_dist_write; /* from vertex shader */ +}; + struct r600_alphatest_state { struct r600_atom atom; unsigned sx_alpha_test_control; /* this comes from dsa state */ @@ -92,44 +144,66 @@ struct r600_alphatest_state { bool cb0_export_16bpc; /* from set_framebuffer_state */ }; +struct r600_vgt_state { + struct r600_atom atom; + uint32_t vgt_multi_prim_ib_reset_en; + uint32_t vgt_multi_prim_ib_reset_indx; + uint32_t vgt_indx_offset; +}; + +struct r600_blend_color { + struct r600_atom atom; + struct pipe_blend_color state; +}; + +struct r600_clip_state { + struct r600_atom atom; + struct pipe_clip_state state; +}; + struct r600_cs_shader_state { struct r600_atom atom; + unsigned kernel_index; struct r600_pipe_compute *shader; }; +struct r600_framebuffer { + struct r600_atom atom; + struct pipe_framebuffer_state state; + unsigned compressed_cb_mask; + unsigned nr_samples; + bool export_16bpc; + bool cb0_is_integer; + bool is_msaa_resolve; +}; + struct r600_sample_mask { struct r600_atom atom; uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ }; -enum r600_pipe_state_id { - R600_PIPE_STATE_BLEND = 0, - R600_PIPE_STATE_BLEND_COLOR, - R600_PIPE_STATE_CONFIG, - R600_PIPE_STATE_SEAMLESS_CUBEMAP, - R600_PIPE_STATE_CLIP, - R600_PIPE_STATE_SCISSOR, - R600_PIPE_STATE_VIEWPORT, - R600_PIPE_STATE_RASTERIZER, - R600_PIPE_STATE_VGT, - R600_PIPE_STATE_FRAMEBUFFER, - R600_PIPE_STATE_DSA, - R600_PIPE_STATE_STENCIL_REF, - R600_PIPE_STATE_PS_SHADER, - R600_PIPE_STATE_VS_SHADER, - R600_PIPE_STATE_CONSTANT, - R600_PIPE_STATE_SAMPLER, - R600_PIPE_STATE_RESOURCE, - R600_PIPE_STATE_POLYGON_OFFSET, - R600_PIPE_STATE_FETCH_SHADER, - R600_PIPE_STATE_SPI, - R600_PIPE_NSTATES +struct r600_config_state { + struct r600_atom atom; + unsigned sq_gpr_resource_mgmt_1; }; -struct compute_memory_pool; -void compute_memory_pool_delete(struct compute_memory_pool* pool); -struct compute_memory_pool* compute_memory_pool_new( - struct r600_screen *rscreen); +struct r600_stencil_ref +{ + ubyte ref_value[2]; + ubyte valuemask[2]; + ubyte writemask[2]; +}; + +struct r600_stencil_ref_state { + struct r600_atom atom; + struct r600_stencil_ref state; + struct pipe_stencil_ref pipe_state; +}; + +struct r600_viewport_state { + struct r600_atom atom; + struct pipe_viewport_state state; +}; struct r600_pipe_fences { struct r600_resource *bo; @@ -142,13 +216,73 @@ struct r600_pipe_fences { pipe_mutex mutex; }; +enum r600_msaa_texture_mode { + /* If the hw can fetch the first sample only (no decompression available). + * This means MSAA texturing is not fully implemented. */ + MSAA_TEXTURE_SAMPLE_ZERO, + + /* If the hw can fetch decompressed MSAA textures. + * Supported families: R600, R700, Evergreen. + * Cayman cannot use this, because it cannot do the decompression. */ + MSAA_TEXTURE_DECOMPRESSED, + + /* If the hw can fetch compressed MSAA textures, which means shaders can + * read resolved FMASK. This yields the best performance. + * Supported families: Evergreen, Cayman. */ + MSAA_TEXTURE_COMPRESSED +}; + +typedef boolean (*r600g_dma_blit_t)(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dst_x, unsigned dst_y, unsigned dst_z, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box); + +/* logging */ +#define DBG_TEX_DEPTH (1 << 0) +#define DBG_COMPUTE (1 << 1) +#define DBG_VM (1 << 2) +#define DBG_TRACE_CS (1 << 3) +/* shaders */ +#define DBG_FS (1 << 8) +#define DBG_VS (1 << 9) +#define DBG_GS (1 << 10) +#define DBG_PS (1 << 11) +#define DBG_CS (1 << 12) +/* features */ +#define DBG_NO_HYPERZ (1 << 16) +#define DBG_NO_LLVM (1 << 17) +#define DBG_NO_CP_DMA (1 << 18) +#define DBG_NO_ASYNC_DMA (1 << 19) +#define DBG_NO_DISCARD_RANGE (1 << 20) +/* shader backend */ +#define DBG_SB (1 << 21) +#define DBG_SB_CS (1 << 22) +#define DBG_SB_DRY_RUN (1 << 23) +#define DBG_SB_STAT (1 << 24) +#define DBG_SB_DUMP (1 << 25) +#define DBG_SB_NO_FALLBACK (1 << 26) +#define DBG_SB_DISASM (1 << 27) + +struct r600_tiling_info { + unsigned num_channels; + unsigned num_banks; + unsigned group_bytes; +}; + struct r600_screen { struct pipe_screen screen; struct radeon_winsys *ws; + unsigned debug_flags; unsigned family; enum chip_class chip_class; struct radeon_info info; bool has_streamout; + bool has_msaa; + bool has_cp_dma; + enum r600_msaa_texture_mode msaa_texture_support; struct r600_tiling_info tiling_info; struct r600_pipe_fences fences; @@ -157,16 +291,26 @@ struct r600_screen { * XXX: Not sure if this is the best place for global_pool. Also, * it's not thread safe, so it won't work with multiple contexts. */ struct compute_memory_pool *global_pool; + struct r600_resource *trace_bo; + uint32_t *trace_ptr; + unsigned cs_count; + r600g_dma_blit_t dma_blit; + + /* Auxiliary context. Mainly used to initialize resources. + * It must be locked prior to using and flushed before unlocking. */ + struct pipe_context *aux_context; + pipe_mutex aux_context_lock; }; struct r600_pipe_sampler_view { struct pipe_sampler_view base; struct r600_resource *tex_resource; uint32_t tex_resource_words[8]; + bool skip_mip_address_reloc; }; -struct r600_pipe_rasterizer { - struct r600_pipe_state rstate; +struct r600_rasterizer_state { + struct r600_command_buffer buffer; boolean flatshade; boolean two_side; unsigned sprite_coord_enable; @@ -175,33 +319,35 @@ struct r600_pipe_rasterizer { unsigned pa_cl_clip_cntl; float offset_units; float offset_scale; + bool offset_enable; bool scissor_enable; bool multisample_enable; }; -struct r600_pipe_blend { - struct r600_pipe_state rstate; +struct r600_poly_offset_state { + struct r600_atom atom; + enum pipe_format zs_format; + float offset_units; + float offset_scale; +}; + +struct r600_blend_state { + struct r600_command_buffer buffer; + struct r600_command_buffer buffer_no_blend; unsigned cb_target_mask; unsigned cb_color_control; + unsigned cb_color_control_no_blend; bool dual_src_blend; bool alpha_to_one; }; -struct r600_pipe_dsa { - struct r600_pipe_state rstate; +struct r600_dsa_state { + struct r600_command_buffer buffer; unsigned alpha_ref; ubyte valuemask[2]; ubyte writemask[2]; - unsigned sx_alpha_test_control; -}; - -struct r600_vertex_element -{ - unsigned count; - struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; - struct r600_resource *fetch_shader; - unsigned fs_size; - struct r600_pipe_state rstate; + unsigned zwritemask; + unsigned sx_alpha_test_control; }; struct r600_pipe_shader; @@ -220,26 +366,9 @@ struct r600_pipe_shader_selector { unsigned nr_ps_max_color_exports; }; -struct r600_pipe_shader { - struct r600_pipe_shader_selector *selector; - struct r600_pipe_shader *next_variant; - struct r600_shader shader; - struct r600_pipe_state rstate; - struct r600_resource *bo; - struct r600_resource *bo_fetch; - struct r600_vertex_element vertex_elements; - unsigned sprite_coord_enable; - unsigned flatshade; - unsigned pa_cl_vs_out_cntl; - unsigned nr_ps_color_outputs; - unsigned key; - unsigned db_shader_control; - unsigned ps_depth_export; -}; - struct r600_pipe_sampler_state { uint32_t tex_sampler_words[3]; - uint32_t border_color[4]; + union pipe_color_union border_color; bool border_color_use; bool seamless_cube_map; }; @@ -259,14 +388,27 @@ struct r600_samplerview_state { uint32_t dirty_mask; uint32_t compressed_depthtex_mask; /* which textures are depth */ uint32_t compressed_colortex_mask; + boolean dirty_txq_constants; + boolean dirty_buffer_constants; +}; + +struct r600_sampler_states { + struct r600_atom atom; + struct r600_pipe_sampler_state *states[NUM_TEX_UNITS]; + uint32_t enabled_mask; + uint32_t dirty_mask; + uint32_t has_bordercolor_mask; /* which states contain the border color */ }; struct r600_textures_info { struct r600_samplerview_state views; - struct r600_atom atom_sampler; - struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; - unsigned n_samplers; + struct r600_sampler_states states; bool is_array_sampler[NUM_TEX_UNITS]; + + /* cube array txq workaround */ + uint32_t *txq_constants; + /* buffer related workarounds */ + uint32_t *buffer_constants; }; struct r600_fence { @@ -286,13 +428,6 @@ struct r600_fence_block { #define R600_CONSTANT_ARRAY_SIZE 256 #define R600_RESOURCE_ARRAY_SIZE 160 -struct r600_stencil_ref -{ - ubyte ref_value[2]; - ubyte valuemask[2]; - ubyte writemask[2]; -}; - struct r600_constbuf_state { struct r600_atom atom; @@ -309,169 +444,276 @@ struct r600_vertexbuf_state uint32_t dirty_mask; }; +/* CSO (constant state object, in other words, immutable state). */ +struct r600_cso_state +{ + struct r600_atom atom; + void *cso; /* e.g. r600_blend_state */ + struct r600_command_buffer *cb; +}; + +struct r600_scissor_state +{ + struct r600_atom atom; + struct pipe_scissor_state scissor; + bool enable; /* r6xx only */ +}; + +struct r600_fetch_shader { + struct r600_resource *buffer; + unsigned offset; +}; + +struct r600_shader_state { + struct r600_atom atom; + struct r600_pipe_shader_selector *shader; +}; + +struct r600_query_buffer { + /* The buffer where query results are stored. */ + struct r600_resource *buf; + /* Offset of the next free result after current query data */ + unsigned results_end; + /* If a query buffer is full, a new buffer is created and the old one + * is put in here. When we calculate the result, we sum up the samples + * from all buffers. */ + struct r600_query_buffer *previous; +}; + +struct r600_query { + /* The query buffer and how many results are in it. */ + struct r600_query_buffer buffer; + /* The type of query */ + unsigned type; + /* Size of the result in memory for both begin_query and end_query, + * this can be one or two numbers, or it could even be a size of a structure. */ + unsigned result_size; + /* The number of dwords for begin_query or end_query. */ + unsigned num_cs_dw; + /* linked list of queries */ + struct list_head list; + /* for custom non-GPU queries */ + uint64_t begin_result; + uint64_t end_result; +}; + +struct r600_so_target { + struct pipe_stream_output_target b; + + /* The buffer where BUFFER_FILLED_SIZE is stored. */ + struct r600_resource *buf_filled_size; + unsigned buf_filled_size_offset; + + unsigned stride_in_dw; + unsigned so_index; +}; + +struct r600_streamout { + struct r600_atom begin_atom; + bool begin_emitted; + unsigned num_dw_for_end; + + unsigned enabled_mask; + unsigned num_targets; + struct r600_so_target *targets[PIPE_MAX_SO_BUFFERS]; + + unsigned append_bitmask; + bool suspended; +}; + +struct r600_ring { + struct radeon_winsys_cs *cs; + bool flushing; + void (*flush)(void *ctx, unsigned flags); +}; + +struct r600_rings { + struct r600_ring gfx; + struct r600_ring dma; +}; + struct r600_context { struct pipe_context context; + struct r600_screen *screen; + struct radeon_winsys *ws; + struct r600_rings rings; struct blitter_context *blitter; + struct u_upload_mgr *uploader; + struct u_suballocator *allocator_so_filled_size; + struct u_suballocator *allocator_fetch_shader; + struct util_slab_mempool pool_transfers; + + /* Hardware info. */ enum radeon_family family; enum chip_class chip_class; boolean has_vertex_cache; + boolean keep_tiling_flags; + unsigned default_ps_gprs, default_vs_gprs; unsigned r6xx_num_clause_temp_gprs; + unsigned backend_mask; + unsigned max_db; /* for OQ */ + + /* current unaccounted memory usage */ + uint64_t vram; + uint64_t gtt; + + /* Miscellaneous state objects. */ void *custom_dsa_flush; void *custom_blend_resolve; void *custom_blend_decompress; + void *custom_blend_fmask_decompress; + /* With rasterizer discard, there doesn't have to be a pixel shader. + * In that case, we bind this one: */ + void *dummy_pixel_shader; + /* These dummy CMASK and FMASK buffers are used to get around the R6xx hardware + * bug where valid CMASK and FMASK are required to be present to avoid + * a hardlock in certain operations but aren't actually used + * for anything useful. */ + struct r600_resource *dummy_fmask; + struct r600_resource *dummy_cmask; - struct r600_screen *screen; - struct radeon_winsys *ws; - struct r600_pipe_state *states[R600_PIPE_NSTATES]; - struct r600_vertex_element *vertex_elements; - struct pipe_framebuffer_state framebuffer; - unsigned compressed_cb_mask; - unsigned compute_cb_target_mask; - unsigned db_shader_control; - unsigned pa_sc_line_stipple; - unsigned pa_cl_clip_cntl; - /* for saving when using blitter */ - struct pipe_stencil_ref stencil_ref; - struct pipe_viewport_state viewport; - struct pipe_clip_state clip; - struct r600_pipe_shader_selector *ps_shader; - struct r600_pipe_shader_selector *vs_shader; - struct r600_pipe_rasterizer *rasterizer; - struct r600_pipe_state vgt; - struct r600_pipe_state spi; - struct pipe_query *current_render_cond; - unsigned current_render_cond_mode; - struct pipe_query *saved_render_cond; - unsigned saved_render_cond_mode; - /* shader information */ - boolean two_side; - boolean spi_dirty; - unsigned sprite_coord_enable; - boolean flatshade; - boolean export_16bpc; - unsigned nr_cbufs; - bool alpha_to_one; - bool multisample_enable; - bool cb0_is_integer; - - struct u_upload_mgr *uploader; - struct util_slab_mempool pool_transfers; - - unsigned default_ps_gprs, default_vs_gprs; - - /* States based on r600_atom. */ + /* State binding slots are here. */ + struct r600_atom *atoms[R600_NUM_ATOMS]; + /* States for CS initialization. */ struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ - struct r600_atom *atoms[R600_MAX_ATOM]; /** Compute specific registers initializations. The start_cs_cmd atom * must be emitted before start_compute_cs_cmd. */ - struct r600_command_buffer start_compute_cs_cmd; + struct r600_command_buffer start_compute_cs_cmd; + /* Register states. */ struct r600_alphatest_state alphatest_state; + struct r600_cso_state blend_state; + struct r600_blend_color blend_color; struct r600_cb_misc_state cb_misc_state; + struct r600_clip_misc_state clip_misc_state; + struct r600_clip_state clip_state; struct r600_db_misc_state db_misc_state; + struct r600_db_state db_state; + struct r600_cso_state dsa_state; + struct r600_framebuffer framebuffer; + struct r600_poly_offset_state poly_offset_state; + struct r600_cso_state rasterizer_state; + struct r600_sample_mask sample_mask; + struct r600_scissor_state scissor; + struct r600_seamless_cube_map seamless_cube_map; + struct r600_config_state config_state; + struct r600_stencil_ref_state stencil_ref; + struct r600_vgt_state vgt_state; + struct r600_viewport_state viewport; + /* Shaders and shader resources. */ + struct r600_cso_state vertex_fetch_shader; + struct r600_shader_state vertex_shader; + struct r600_shader_state pixel_shader; + struct r600_cs_shader_state cs_shader_state; + struct r600_constbuf_state constbuf_state[PIPE_SHADER_TYPES]; + struct r600_textures_info samplers[PIPE_SHADER_TYPES]; /** Vertex buffers for fetch shaders */ struct r600_vertexbuf_state vertex_buffer_state; /** Vertex buffers for compute shaders */ struct r600_vertexbuf_state cs_vertex_buffer_state; - struct r600_constbuf_state vs_constbuf_state; - struct r600_constbuf_state ps_constbuf_state; - struct r600_textures_info vs_samplers; - struct r600_textures_info ps_samplers; - struct r600_seamless_cube_map seamless_cube_map; - struct r600_cs_shader_state cs_shader_state; - struct r600_sample_mask sample_mask; - - /* current external blend state (from state tracker) */ - struct r600_pipe_blend *blend; - /* state with disabled blending - used internally with blend_override */ - struct r600_pipe_blend *no_blend; + struct r600_streamout streamout; - /* 1 - override current blend state with no_blend, 0 - use external state */ - unsigned blend_override; + /* Additional context states. */ + unsigned flags; + unsigned compute_cb_target_mask; + struct r600_pipe_shader_selector *ps_shader; + struct r600_pipe_shader_selector *vs_shader; + struct r600_rasterizer_state *rasterizer; + bool alpha_to_one; + bool force_blend_disable; + boolean dual_src_blend; + unsigned zwritemask; - struct radeon_winsys_cs *cs; + /* Index buffer. */ + struct pipe_index_buffer index_buffer; - struct r600_range *range; - unsigned nblocks; - struct r600_block **blocks; - struct list_head dirty; - struct list_head enable_list; - unsigned pm4_dirty_cdwords; - unsigned ctx_pm4_ndwords; + /* Last draw state (-1 = unset). */ + int last_primitive_type; /* Last primitive type used in draw_vbo. */ + int last_start_instance; + /* Queries. */ /* The list of active queries. Only one query of each type can be active. */ - int num_occlusion_queries; - - /* Manage queries in two separate groups: - * The timer ones and the others (streamout, occlusion). - * - * We do this because we should only suspend non-timer queries for u_blitter, - * and later if the non-timer queries are suspended, the context flush should - * only suspend and resume the timer queries. */ - struct list_head active_timer_queries; - unsigned num_cs_dw_timer_queries_suspend; - struct list_head active_nontimer_queries; - unsigned num_cs_dw_nontimer_queries_suspend; - - unsigned num_cs_dw_streamout_end; - - unsigned backend_mask; - unsigned max_db; /* for OQ */ - unsigned flags; - boolean predicate_drawing; - - unsigned num_so_targets; - struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; - boolean streamout_start; - unsigned streamout_append_bitmask; - - /* There is no scissor enable bit on r6xx, so we must use a workaround. - * These track the current scissor state. */ - bool scissor_enable; - struct pipe_scissor_state scissor_state; - - /* With rasterizer discard, there doesn't have to be a pixel shader. - * In that case, we bind this one: */ - void *dummy_pixel_shader; + int num_occlusion_queries; + int num_pipelinestat_queries; + /* Keep track of non-timer queries, because they should be suspended + * during context flushing. + * The timer queries (TIME_ELAPSED) shouldn't be suspended. */ + struct list_head active_nontimer_queries; + unsigned num_cs_dw_nontimer_queries_suspend; + /* If queries have been suspended. */ + bool nontimer_queries_suspended; + unsigned num_draw_calls; + + /* Render condition. */ + struct pipe_query *current_render_cond; + unsigned current_render_cond_mode; + boolean predicate_drawing; - boolean dual_src_blend; + void *sb_context; + struct r600_isa *isa; +}; - /* Index buffer. */ - struct pipe_index_buffer index_buffer; +static INLINE void r600_emit_command_buffer(struct radeon_winsys_cs *cs, + struct r600_command_buffer *cb) +{ + assert(cs->cdw + cb->num_dw <= RADEON_MAX_CMDBUF_DWORDS); + memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->num_dw); + cs->cdw += cb->num_dw; +} - /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware - * bug where valid CMASK and FMASK are required to be present to avoid - * a hardlock in certain operations but aren't actually used - * for anything useful. */ - struct r600_resource *dummy_fmask; - struct r600_resource *dummy_cmask; -}; +void r600_trace_emit(struct r600_context *rctx); static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) { atom->emit(rctx, atom); atom->dirty = false; + if (rctx->screen->trace_bo) { + r600_trace_emit(rctx); + } } -static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) +static INLINE void r600_set_cso_state(struct r600_cso_state *state, void *cso) { - state->dirty = true; + state->cso = cso; + state->atom.dirty = cso != NULL; } +static INLINE void r600_set_cso_state_with_cb(struct r600_cso_state *state, void *cso, + struct r600_command_buffer *cb) +{ + state->cb = cb; + state->atom.num_dw = cb->num_dw; + r600_set_cso_state(state, cso); +} + +/* compute_memory_pool.c */ +struct compute_memory_pool; +void compute_memory_pool_delete(struct compute_memory_pool* pool); +struct compute_memory_pool* compute_memory_pool_new( + struct r600_screen *rscreen); + /* evergreen_state.c */ +struct pipe_sampler_view * +evergreen_create_sampler_view_custom(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state, + unsigned width0, unsigned height0); void evergreen_init_common_regs(struct r600_command_buffer *cb, enum chip_class ctx_chip_class, enum radeon_family ctx_family, int ctx_drm_minor); +void cayman_init_common_regs(struct r600_command_buffer *cb, + enum chip_class ctx_chip_class, + enum radeon_family ctx_family, + int ctx_drm_minor); void evergreen_init_state_functions(struct r600_context *rctx); void evergreen_init_atom_start_cs(struct r600_context *rctx); -void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); -void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); -void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); +void evergreen_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void evergreen_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void *evergreen_create_db_flush_dsa(struct r600_context *rctx); void *evergreen_create_resolve_blend(struct r600_context *rctx); void *evergreen_create_decompress_blend(struct r600_context *rctx); -void evergreen_polygon_offset_update(struct r600_context *rctx); +void *evergreen_create_fmask_decompress_blend(struct r600_context *rctx); boolean evergreen_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, @@ -479,12 +721,15 @@ boolean evergreen_is_format_supported(struct pipe_screen *screen, unsigned usage); void evergreen_init_color_surface(struct r600_context *rctx, struct r600_surface *surf); -void evergreen_update_dual_export_state(struct r600_context * rctx); +void evergreen_init_color_surface_rat(struct r600_context *rctx, + struct r600_surface *surf); +void evergreen_update_db_shader_control(struct r600_context * rctx); /* r600_blit.c */ -void r600_copy_buffer(struct pipe_context *ctx, struct - pipe_resource *dst, unsigned dstx, +void r600_copy_buffer(struct pipe_context *ctx, struct pipe_resource *dst, unsigned dstx, struct pipe_resource *src, const struct pipe_box *src_box); +void r600_screen_clear_buffer(struct r600_screen *rscreen, struct pipe_resource *dst, + unsigned offset, unsigned size, unsigned char value); void r600_init_blit_functions(struct r600_context *rctx); void r600_blit_decompress_depth(struct pipe_context *ctx, struct r600_texture *texture, @@ -501,27 +746,33 @@ void r600_decompress_color_textures(struct r600_context *rctx, bool r600_init_resource(struct r600_screen *rscreen, struct r600_resource *res, unsigned size, unsigned alignment, - unsigned bind, unsigned usage); + bool use_reusable_pool, unsigned usage); struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, const struct pipe_resource *templ, unsigned alignment); /* r600_pipe.c */ -void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, - unsigned flags); +boolean r600_rings_is_buffer_referenced(struct r600_context *ctx, + struct radeon_winsys_cs_handle *buf, + enum radeon_bo_usage usage); +void *r600_buffer_mmap_sync_with_rings(struct r600_context *ctx, + struct r600_resource *resource, + unsigned usage); +const char * r600_llvm_gpu_string(enum radeon_family family); + /* r600_query.c */ void r600_init_query_functions(struct r600_context *rctx); void r600_suspend_nontimer_queries(struct r600_context *ctx); void r600_resume_nontimer_queries(struct r600_context *ctx); -void r600_suspend_timer_queries(struct r600_context *ctx); -void r600_resume_timer_queries(struct r600_context *ctx); /* r600_resource.c */ void r600_init_context_resource_functions(struct r600_context *r600); /* r600_shader.c */ -int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); +int r600_pipe_shader_create(struct pipe_context *ctx, + struct r600_pipe_shader *shader, + struct r600_shader_key key); #ifdef HAVE_OPENCL int r600_compute_shader_create(struct pipe_context * ctx, LLVMModuleRef mod, struct r600_bytecode * bytecode); @@ -529,25 +780,26 @@ int r600_compute_shader_create(struct pipe_context * ctx, void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); /* r600_state.c */ -void r600_set_scissor_state(struct r600_context *rctx, - const struct pipe_scissor_state *state); +struct pipe_sampler_view * +r600_create_sampler_view_custom(struct pipe_context *ctx, + struct pipe_resource *texture, + const struct pipe_sampler_view *state, + unsigned width_first_level, unsigned height_first_level); void r600_init_state_functions(struct r600_context *rctx); void r600_init_atom_start_cs(struct r600_context *rctx); -void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); -void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); -void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); +void r600_update_ps_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); +void r600_update_vs_state(struct pipe_context *ctx, struct r600_pipe_shader *shader); void *r600_create_db_flush_dsa(struct r600_context *rctx); void *r600_create_resolve_blend(struct r600_context *rctx); void *r700_create_resolve_blend(struct r600_context *rctx); void *r600_create_decompress_blend(struct r600_context *rctx); -void r600_polygon_offset_update(struct r600_context *rctx); -void r600_adjust_gprs(struct r600_context *rctx); +bool r600_adjust_gprs(struct r600_context *rctx); boolean r600_is_format_supported(struct pipe_screen *screen, enum pipe_format format, enum pipe_texture_target target, unsigned sample_count, unsigned usage); -void r600_update_dual_export_state(struct r600_context * rctx); +void r600_update_db_shader_control(struct r600_context * rctx); /* r600_texture.c */ void r600_init_screen_texture_functions(struct pipe_screen *screen); @@ -557,76 +809,88 @@ uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format f uint32_t *word4_p, uint32_t *yuv_format_p); unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level, unsigned layer); +struct pipe_surface *r600_create_surface_custom(struct pipe_context *pipe, + struct pipe_resource *texture, + const struct pipe_surface *templ, + unsigned width, unsigned height); + +unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, + const unsigned char *swizzle_view, + boolean vtx); + +/* r600_hw_context.c */ +void r600_get_backend_mask(struct r600_context *ctx); +void r600_context_flush(struct r600_context *ctx, unsigned flags); +void r600_begin_new_cs(struct r600_context *ctx); +void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence, + unsigned offset, unsigned value); +void r600_flush_emit(struct r600_context *ctx); +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_need_dma_space(struct r600_context *ctx, unsigned num_dw); +void r600_cp_dma_copy_buffer(struct r600_context *rctx, + struct pipe_resource *dst, uint64_t dst_offset, + struct pipe_resource *src, uint64_t src_offset, + unsigned size); +void evergreen_cp_dma_clear_buffer(struct r600_context *rctx, + struct pipe_resource *dst, uint64_t offset, + unsigned size, uint32_t clear_value); +void r600_dma_copy(struct r600_context *rctx, + struct pipe_resource *dst, + struct pipe_resource *src, + uint64_t dst_offset, + uint64_t src_offset, + uint64_t size); +boolean r600_dma_blit(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dst_x, unsigned dst_y, unsigned dst_z, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box); +void r600_emit_streamout_begin(struct r600_context *ctx, struct r600_atom *atom); +void r600_emit_streamout_end(struct r600_context *ctx); -/* r600_translate.c */ -void r600_translate_index_buffer(struct r600_context *r600, - struct pipe_index_buffer *ib, - unsigned count); +/* + * evergreen_hw_context.c + */ +void evergreen_flush_vgt_streamout(struct r600_context *ctx); +void evergreen_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit); +void evergreen_dma_copy(struct r600_context *rctx, + struct pipe_resource *dst, + struct pipe_resource *src, + uint64_t dst_offset, + uint64_t src_offset, + uint64_t size); +boolean evergreen_dma_blit(struct pipe_context *ctx, + struct pipe_resource *dst, + unsigned dst_level, + unsigned dst_x, unsigned dst_y, unsigned dst_z, + struct pipe_resource *src, + unsigned src_level, + const struct pipe_box *src_box); /* r600_state_common.c */ +void r600_init_common_state_functions(struct r600_context *rctx); +void r600_emit_cso_state(struct r600_context *rctx, struct r600_atom *atom); void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_blend_color(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_vgt_state(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_clip_misc_state(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_stencil_ref(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_viewport_state(struct r600_context *rctx, struct r600_atom *atom); +void r600_emit_shader(struct r600_context *rctx, struct r600_atom *a); void r600_init_atom(struct r600_context *rctx, struct r600_atom *atom, unsigned id, void (*emit)(struct r600_context *ctx, struct r600_atom *state), unsigned num_dw); -void r600_texture_barrier(struct pipe_context *ctx); -void r600_set_index_buffer(struct pipe_context *ctx, - const struct pipe_index_buffer *ib); void r600_vertex_buffers_dirty(struct r600_context *rctx); -void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, - const struct pipe_vertex_buffer *input); void r600_sampler_views_dirty(struct r600_context *rctx, struct r600_samplerview_state *state); -void r600_set_sampler_views(struct pipe_context *pipe, - unsigned shader, - unsigned start, - unsigned count, - struct pipe_sampler_view **views); -void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); -void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); -void *r600_create_vertex_elements(struct pipe_context *ctx, - unsigned count, - const struct pipe_vertex_element *elements); -void r600_delete_vertex_element(struct pipe_context *ctx, void *state); -void r600_bind_blend_state(struct pipe_context *ctx, void *state); -void r600_set_blend_color(struct pipe_context *ctx, - const struct pipe_blend_color *state); -void r600_bind_dsa_state(struct pipe_context *ctx, void *state); -void r600_set_max_scissor(struct r600_context *rctx); -void r600_bind_rs_state(struct pipe_context *ctx, void *state); -void r600_delete_rs_state(struct pipe_context *ctx, void *state); -void r600_sampler_view_destroy(struct pipe_context *ctx, - struct pipe_sampler_view *state); -void r600_delete_sampler(struct pipe_context *ctx, void *state); -void r600_delete_state(struct pipe_context *ctx, void *state); -void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); -void *r600_create_shader_state_ps(struct pipe_context *ctx, - const struct pipe_shader_state *state); -void *r600_create_shader_state_vs(struct pipe_context *ctx, - const struct pipe_shader_state *state); -void r600_bind_ps_shader(struct pipe_context *ctx, void *state); -void r600_bind_vs_shader(struct pipe_context *ctx, void *state); -void r600_delete_ps_shader(struct pipe_context *ctx, void *state); -void r600_delete_vs_shader(struct pipe_context *ctx, void *state); +void r600_sampler_states_dirty(struct r600_context *rctx, + struct r600_sampler_states *state); void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); -void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, - struct pipe_constant_buffer *cb); -struct pipe_stream_output_target * -r600_create_so_target(struct pipe_context *ctx, - struct pipe_resource *buffer, - unsigned buffer_offset, - unsigned buffer_size); -void r600_so_target_destroy(struct pipe_context *ctx, - struct pipe_stream_output_target *target); -void r600_set_so_targets(struct pipe_context *ctx, - unsigned num_targets, - struct pipe_stream_output_target **targets, - unsigned append_bitmask); -void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); -void r600_set_pipe_stencil_ref(struct pipe_context *ctx, - const struct pipe_stencil_ref *state); -void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); +void r600_streamout_buffers_dirty(struct r600_context *rctx); void r600_draw_rectangle(struct blitter_context *blitter, - unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth, + int x1, int y1, int x2, int y2, float depth, enum blitter_attrib_type type, const union pipe_color_union *attrib); uint32_t r600_translate_stencil_op(int s_op); uint32_t r600_translate_fill(uint32_t func); @@ -634,6 +898,22 @@ unsigned r600_tex_wrap(unsigned wrap); unsigned r600_tex_filter(unsigned filter); unsigned r600_tex_mipfilter(unsigned filter); unsigned r600_tex_compare(unsigned compare); +bool sampler_state_needs_border_color(const struct pipe_sampler_state *state); + +/* r600_uvd.c */ +struct pipe_video_decoder *r600_uvd_create_decoder(struct pipe_context *context, + enum pipe_video_profile profile, + enum pipe_video_entrypoint entrypoint, + enum pipe_video_chroma_format chroma_format, + unsigned width, unsigned height, + unsigned max_references, bool expect_chunked_decode); + +struct pipe_video_buffer *r600_video_buffer_create(struct pipe_context *pipe, + const struct pipe_video_buffer *tmpl); + +int r600_uvd_get_video_param(struct pipe_screen *screen, + enum pipe_video_profile profile, + enum pipe_video_cap param); /* * Helpers for building command buffers @@ -663,15 +943,22 @@ unsigned r600_tex_compare(unsigned compare); static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) { - cb->buf[cb->atom.num_dw++] = value; + cb->buf[cb->num_dw++] = value; +} + +static INLINE void r600_store_array(struct r600_command_buffer *cb, unsigned num, unsigned *ptr) +{ + assert(cb->num_dw+num <= cb->max_num_dw); + memcpy(&cb->buf[cb->num_dw], ptr, num * sizeof(ptr[0])); + cb->num_dw += num; } static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg < R600_CONTEXT_REG_OFFSET); - assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); - cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; + assert(cb->num_dw+2+num <= cb->max_num_dw); + cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); + cb->buf[cb->num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; } /** @@ -681,9 +968,9 @@ static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, uns static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); - assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; - cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; + assert(cb->num_dw+2+num <= cb->max_num_dw); + cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; + cb->buf[cb->num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; } /** @@ -693,17 +980,17 @@ static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, un static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); - assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; - cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; + assert(cb->num_dw+2+num <= cb->max_num_dw); + cb->buf[cb->num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; + cb->buf[cb->num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; } static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= R600_LOOP_CONST_OFFSET); - assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); - cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; + assert(cb->num_dw+2+num <= cb->max_num_dw); + cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); + cb->buf[cb->num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; } /** @@ -713,9 +1000,9 @@ static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, uns static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) { assert(reg >= EG_LOOP_CONST_OFFSET); - assert(cb->atom.num_dw+2+num <= cb->max_num_dw); - cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; - cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; + assert(cb->num_dw+2+num <= cb->max_num_dw); + cb->buf[cb->num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; + cb->buf[cb->num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; } static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) @@ -748,18 +1035,33 @@ static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned r600_store_value(cb, value); } -void r600_init_command_buffer(struct r600_context *rctx, struct r600_command_buffer *cb, unsigned id, unsigned num_dw); +void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); void r600_release_command_buffer(struct r600_command_buffer *cb); /* * Helpers for emitting state into a command stream directly. */ - -static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, +static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, + struct r600_ring *ring, + struct r600_resource *rbo, enum radeon_bo_usage usage) { assert(usage); - return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; + /* make sure that all previous ring use are flushed so everything + * look serialized from driver pov + */ + if (!ring->flushing) { + if (ring == &ctx->rings.gfx) { + if (ctx->rings.dma.cs) { + /* flush dma ring */ + ctx->rings.dma.flush(ctx, RADEON_FLUSH_ASYNC); + } + } else { + /* flush gfx ring */ + ctx->rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC); + } + } + return ctx->ws->cs_add_reloc(ring->cs, rbo->cs_buf, usage, rbo->domains) * 4; } static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) @@ -823,6 +1125,15 @@ static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, u r600_write_value(cs, value); } +static INLINE void r600_write_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) +{ + if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { + r600_write_compute_context_reg(cs, reg, value); + } else { + r600_write_context_reg(cs, reg, value); + } + +} static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) { r600_write_ctl_const_seq(cs, reg, 1); @@ -862,4 +1173,28 @@ static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_ return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); } +static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r) +{ + struct r600_context *rctx = (struct r600_context *)ctx; + struct r600_resource *rr = (struct r600_resource *)r; + + if (r == NULL) { + return; + } + + /* + * The idea is to compute a gross estimate of memory requirement of + * each draw call. After each draw call, memory will be precisely + * accounted. So the uncertainty is only on the current draw call. + * In practice this gave very good estimate (+/- 10% of the target + * memory limit). + */ + if (rr->domains & RADEON_DOMAIN_GTT) { + rctx->gtt += rr->buf->size; + } + if (rr->domains & RADEON_DOMAIN_VRAM) { + rctx->vram += rr->buf->size; + } +} + #endif