X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=src%2Fgallium%2Fdrivers%2Fr600%2Fr600_pipe.h;h=e2c34d7807049aaaf7f18a0cbde1e6fb9c263b90;hb=9bc6c135acd59a48d35ce6d7fb619e064af04239;hp=9e5dc221e9c72bb44c5bdb9e8f2935160988aa77;hpb=5b14e06d8b42e2b08ebc52b6c314ef8647d87a1f;p=mesa.git diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 9e5dc221e9c..e2c34d78070 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -152,6 +152,7 @@ struct r600_cb_misc_state { unsigned cb_color_control; /* this comes from blend state */ unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ unsigned nr_cbufs; + unsigned bound_cbufs_target_mask; unsigned nr_ps_color_outputs; unsigned ps_color_export_mask; unsigned image_rat_enabled_mask; @@ -342,12 +343,14 @@ struct r600_pipe_shader_selector { struct r600_pipe_shader *current; struct tgsi_token *tokens; + struct nir_shader *nir; struct pipe_stream_output_info so; struct tgsi_shader_info info; unsigned num_shaders; enum pipe_shader_type type; + enum pipe_shader_ir ir_type; /* geometry shader properties */ enum pipe_prim_type gs_output_prim; @@ -445,8 +448,6 @@ struct r600_shader_state { }; struct r600_atomic_buffer_state { - uint32_t enabled_mask; - uint32_t dirty_mask; struct pipe_shader_buffer buffer[EG_MAX_ATOMIC_BUFFERS]; }; @@ -477,6 +478,14 @@ struct r600_image_state { struct r600_image_view views[R600_MAX_IMAGES]; }; +/* Used to spill shader temps */ +struct r600_scratch_buffer { + struct r600_resource *buffer; + boolean dirty; + unsigned size; + unsigned item_size; +}; + struct r600_context { struct r600_common_context b; struct r600_screen *screen; @@ -570,7 +579,7 @@ struct r600_context { bool gs_tri_strip_adj_fix; boolean dual_src_blend; unsigned zwritemask; - int ps_iter_samples; + unsigned ps_iter_samples; /* The list of all texture buffer objects in this context. * This list is walked when a buffer is invalidated/reallocated and @@ -593,6 +602,8 @@ struct r600_context { unsigned last_num_tcs_input_cp; unsigned lds_alloc; + struct r600_scratch_buffer scratch_buffers[MAX2(R600_NUM_HW_STAGES, EG_NUM_HW_STAGES)]; + /* Debug state. */ bool is_debug; struct radeon_saved_cs last_gfx; @@ -605,7 +616,7 @@ struct r600_context { uint32_t append_fence_id; }; -static inline void r600_emit_command_buffer(struct radeon_winsys_cs *cs, +static inline void r600_emit_command_buffer(struct radeon_cmdbuf *cs, struct r600_command_buffer *cb) { assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); @@ -691,18 +702,19 @@ void *evergreen_create_db_flush_dsa(struct r600_context *rctx); void *evergreen_create_resolve_blend(struct r600_context *rctx); void *evergreen_create_decompress_blend(struct r600_context *rctx); void *evergreen_create_fastclear_blend(struct r600_context *rctx); -boolean evergreen_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_texture_target target, - unsigned sample_count, - unsigned usage); +bool evergreen_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned sample_count, + unsigned storage_sample_count, + unsigned usage); void evergreen_init_color_surface(struct r600_context *rctx, struct r600_surface *surf); void evergreen_init_color_surface_rat(struct r600_context *rctx, struct r600_surface *surf); void evergreen_update_db_shader_control(struct r600_context * rctx); bool evergreen_adjust_gprs(struct r600_context *rctx); - +void evergreen_setup_scratch_buffers(struct r600_context *rctx); uint32_t evergreen_construct_rat_mask(struct r600_context *rctx, struct r600_cb_misc_state *a, unsigned nr_cbufs); /* r600_blit.c */ @@ -747,19 +759,21 @@ void *r600_create_resolve_blend(struct r600_context *rctx); void *r700_create_resolve_blend(struct r600_context *rctx); void *r600_create_decompress_blend(struct r600_context *rctx); bool r600_adjust_gprs(struct r600_context *rctx); -boolean r600_is_format_supported(struct pipe_screen *screen, - enum pipe_format format, - enum pipe_texture_target target, - unsigned sample_count, - unsigned usage); +bool r600_is_format_supported(struct pipe_screen *screen, + enum pipe_format format, + enum pipe_texture_target target, + unsigned sample_count, + unsigned storage_sample_count, + unsigned usage); void r600_update_db_shader_control(struct r600_context * rctx); +void r600_setup_scratch_buffers(struct r600_context *rctx); /* r600_hw_context.c */ void r600_context_gfx_flush(void *context, unsigned flags, struct pipe_fence_handle **fence); void r600_begin_new_cs(struct r600_context *ctx); void r600_flush_emit(struct r600_context *ctx); -void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in); +void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in, unsigned num_atomics); void r600_emit_pfp_sync_me(struct r600_context *rctx); void r600_cp_dma_copy_buffer(struct r600_context *rctx, struct pipe_resource *dst, uint64_t dst_offset, @@ -792,10 +806,10 @@ uint32_t evergreen_get_ls_hs_config(struct r600_context *rctx, const struct pipe_draw_info *info, unsigned num_patches); void evergreen_set_ls_hs_config(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t ls_hs_config); void evergreen_set_lds_alloc(struct r600_context *rctx, - struct radeon_winsys_cs *cs, + struct radeon_cmdbuf *cs, uint32_t lds_alloc); /* r600_state_common.c */ @@ -818,6 +832,9 @@ void r600_sampler_states_dirty(struct r600_context *rctx, struct r600_sampler_states *state); void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); void r600_set_sample_locations_constant_buffer(struct r600_context *rctx); +void r600_setup_scratch_area_for_shader(struct r600_context *rctx, + struct r600_pipe_shader *shader, struct r600_scratch_buffer *scratch, + unsigned ring_base_reg, unsigned item_size_reg, unsigned ring_size_reg); uint32_t r600_translate_stencil_op(int s_op); uint32_t r600_translate_fill(uint32_t func); unsigned r600_tex_wrap(unsigned wrap); @@ -965,14 +982,14 @@ static inline void eg_store_loop_const(struct r600_command_buffer *cb, unsigned void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw); void r600_release_command_buffer(struct r600_command_buffer *cb); -static inline void radeon_compute_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_compute_set_context_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { radeon_set_context_reg_seq(cs, reg, num); /* Set the compute bit on the packet header */ cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; } -static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) +static inline void radeon_set_ctl_const_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) { assert(reg >= R600_CTL_CONST_OFFSET); assert(cs->current.cdw + 2 + num <= cs->current.max_dw); @@ -980,13 +997,13 @@ static inline void radeon_set_ctl_const_seq(struct radeon_winsys_cs *cs, unsigne radeon_emit(cs, (reg - R600_CTL_CONST_OFFSET) >> 2); } -static inline void radeon_compute_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_compute_set_context_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_compute_set_context_reg_seq(cs, reg, 1); radeon_emit(cs, value); } -static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsigned reg, unsigned value, unsigned flag) +static inline void radeon_set_context_reg_flag(struct radeon_cmdbuf *cs, unsigned reg, unsigned value, unsigned flag) { if (flag & RADEON_CP_PACKET3_COMPUTE_MODE) { radeon_compute_set_context_reg(cs, reg, value); @@ -995,7 +1012,7 @@ static inline void radeon_set_context_reg_flag(struct radeon_winsys_cs *cs, unsi } } -static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) +static inline void radeon_set_ctl_const(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) { radeon_set_ctl_const_seq(cs, reg, 1); radeon_emit(cs, value); @@ -1040,7 +1057,8 @@ void eg_dump_debug_state(struct pipe_context *ctx, FILE *f, unsigned flags); struct r600_pipe_shader_selector *r600_create_shader_state_tokens(struct pipe_context *ctx, - const struct tgsi_token *tokens, + const void *tokens, + enum pipe_shader_ir, unsigned pipe_shader_type); int r600_shader_select(struct pipe_context *ctx, struct r600_pipe_shader_selector* sel, @@ -1050,10 +1068,14 @@ void r600_delete_shader_selector(struct pipe_context *ctx, struct r600_pipe_shader_selector *sel); struct r600_shader_atomic; -bool evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, - struct r600_pipe_shader *cs_shader, +void evergreen_emit_atomic_buffer_setup_count(struct r600_context *rctx, + struct r600_pipe_shader *cs_shader, + struct r600_shader_atomic *combined_atomics, + uint8_t *atomic_used_mask_p); +void evergreen_emit_atomic_buffer_setup(struct r600_context *rctx, + bool is_compute, struct r600_shader_atomic *combined_atomics, - uint8_t *atomic_used_mask_p); + uint8_t atomic_used_mask); void evergreen_emit_atomic_buffer_save(struct r600_context *rctx, bool is_compute, struct r600_shader_atomic *combined_atomics,